Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
182451 |
1 |
|
|
T2 |
742 |
|
T7 |
2028 |
|
T8 |
1780 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
100747 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
57827 |
1 |
|
|
T2 |
732 |
|
T7 |
57 |
|
T8 |
53 |
seven_bytes |
3461 |
1 |
|
|
T7 |
59 |
|
T8 |
48 |
|
T15 |
52 |
six_bytes |
3518 |
1 |
|
|
T7 |
56 |
|
T8 |
52 |
|
T15 |
50 |
five_bytes |
3402 |
1 |
|
|
T7 |
55 |
|
T8 |
38 |
|
T15 |
32 |
four_bytes |
3430 |
1 |
|
|
T7 |
64 |
|
T8 |
57 |
|
T15 |
55 |
three_bytes |
3349 |
1 |
|
|
T7 |
49 |
|
T8 |
46 |
|
T15 |
64 |
two_bytes |
3395 |
1 |
|
|
T7 |
67 |
|
T8 |
44 |
|
T15 |
48 |
one_byte |
3322 |
1 |
|
|
T7 |
55 |
|
T8 |
46 |
|
T15 |
55 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179113 |
1 |
|
|
T2 |
722 |
|
T7 |
2004 |
|
T8 |
1760 |
auto[1] |
3338 |
1 |
|
|
T2 |
20 |
|
T7 |
24 |
|
T8 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
182451 |
1 |
|
|
T2 |
742 |
|
T7 |
2028 |
|
T8 |
1780 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
182434 |
1 |
|
|
T2 |
742 |
|
T7 |
2028 |
|
T8 |
1780 |
auto[1] |
17 |
1 |
|
|
T193 |
1 |
|
T194 |
1 |
|
T195 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1096 |
1 |
|
|
T2 |
10 |
|
T7 |
3 |
|
T8 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3338 |
1 |
|
|
T2 |
20 |
|
T7 |
24 |
|
T8 |
20 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
178987 |
1 |
|
|
T2 |
416 |
|
T7 |
1938 |
|
T8 |
2061 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
98349 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
57362 |
1 |
|
|
T2 |
408 |
|
T7 |
50 |
|
T8 |
65 |
seven_bytes |
3384 |
1 |
|
|
T7 |
57 |
|
T8 |
63 |
|
T15 |
42 |
six_bytes |
3327 |
1 |
|
|
T7 |
54 |
|
T8 |
62 |
|
T15 |
42 |
five_bytes |
3390 |
1 |
|
|
T7 |
56 |
|
T8 |
52 |
|
T15 |
63 |
four_bytes |
3236 |
1 |
|
|
T7 |
59 |
|
T8 |
55 |
|
T15 |
30 |
three_bytes |
3211 |
1 |
|
|
T7 |
43 |
|
T8 |
64 |
|
T15 |
46 |
two_bytes |
3397 |
1 |
|
|
T7 |
65 |
|
T8 |
48 |
|
T15 |
46 |
one_byte |
3331 |
1 |
|
|
T7 |
62 |
|
T8 |
51 |
|
T15 |
38 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175707 |
1 |
|
|
T2 |
400 |
|
T7 |
1916 |
|
T8 |
2033 |
auto[1] |
3280 |
1 |
|
|
T2 |
16 |
|
T7 |
22 |
|
T8 |
28 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
178987 |
1 |
|
|
T2 |
416 |
|
T7 |
1938 |
|
T8 |
2061 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
178973 |
1 |
|
|
T2 |
416 |
|
T7 |
1938 |
|
T8 |
2060 |
auto[1] |
14 |
1 |
|
|
T8 |
1 |
|
T77 |
1 |
|
T196 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1081 |
1 |
|
|
T2 |
8 |
|
T7 |
5 |
|
T8 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3280 |
1 |
|
|
T2 |
16 |
|
T7 |
22 |
|
T8 |
28 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
363859 |
1 |
|
|
T2 |
1092 |
|
T7 |
2080 |
|
T8 |
2165 |
auto[1] |
493 |
1 |
|
|
T9 |
70 |
|
T10 |
23 |
|
T11 |
4 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
205559 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
109577 |
1 |
|
|
T2 |
1078 |
|
T7 |
50 |
|
T8 |
52 |
seven_bytes |
7119 |
1 |
|
|
T7 |
64 |
|
T8 |
68 |
|
T18 |
4 |
six_bytes |
7154 |
1 |
|
|
T7 |
52 |
|
T8 |
63 |
|
T18 |
3 |
five_bytes |
7066 |
1 |
|
|
T7 |
50 |
|
T8 |
67 |
|
T18 |
1 |
four_bytes |
7023 |
1 |
|
|
T7 |
48 |
|
T8 |
45 |
|
T18 |
3 |
three_bytes |
7029 |
1 |
|
|
T7 |
53 |
|
T8 |
69 |
|
T18 |
1 |
two_bytes |
6961 |
1 |
|
|
T7 |
63 |
|
T8 |
58 |
|
T18 |
1 |
one_byte |
6864 |
1 |
|
|
T7 |
44 |
|
T8 |
63 |
|
T15 |
94 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
357766 |
1 |
|
|
T2 |
1064 |
|
T7 |
2032 |
|
T8 |
2141 |
auto[1] |
6586 |
1 |
|
|
T2 |
28 |
|
T7 |
48 |
|
T8 |
24 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
364352 |
1 |
|
|
T2 |
1092 |
|
T7 |
2080 |
|
T8 |
2165 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
364332 |
1 |
|
|
T2 |
1092 |
|
T7 |
2080 |
|
T8 |
2165 |
auto[1] |
20 |
1 |
|
|
T197 |
1 |
|
T136 |
1 |
|
T198 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2146 |
1 |
|
|
T2 |
14 |
|
T7 |
8 |
|
T8 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6586 |
1 |
|
|
T2 |
28 |
|
T7 |
48 |
|
T8 |
24 |