Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

266067549

1

T1

50

T2

41168

T3

519914

full_word

187118680

1

T1

100

T2

60849

T3

326941

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	453185929	1			T1	150		T2	102017		T3	846855
auto[TlIntgErrCmd]	89	1			T129	5		T130	4		T131	7
auto[TlIntgErrData]	110	1			T129	8		T130	5		T131	4
auto[TlIntgErrBoth]	101	1			T129	7		T130	1		T131	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234124858

1

T1

45

T2

68237

T3

423683

auto[1]

219061371

1

T1

105

T2

33780

T3

423172

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161657887	1			T1	20		T2	25688		T3	312847
auto[TlIntgErrNone]	partial	auto[1]	104409387	1			T1	30		T2	15480		T3	207067
auto[TlIntgErrNone]	full_word	auto[0]	72466823	1			T1	25		T2	42549		T3	110836
auto[TlIntgErrNone]	full_word	auto[1]	114651832	1			T1	75		T2	18300		T3	216105
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T129	2		T130	1		T131	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T129	3		T130	3		T131	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T200	1		T204	1		T205	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T131	1		T205	1		T206	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T129	5		T130	3		T131	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T129	2		T130	2		T131	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T200	1		T207	1		T202	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T129	1		T201	1		T204	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T129	5		T131	5		T169	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T129	2		T131	4		T169	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T169	1		T200	1		T204	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T130	1		T208	1		T201	1