Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	665167	0	0
entropy_period_rd_A	2147483647	1604	0	0
intr_enable_rd_A	2147483647	2136	0	0
prefix_0_rd_A	2147483647	1366	0	0
prefix_10_rd_A	2147483647	1562	0	0
prefix_1_rd_A	2147483647	1616	0	0
prefix_2_rd_A	2147483647	1411	0	0
prefix_3_rd_A	2147483647	1490	0	0
prefix_4_rd_A	2147483647	1441	0	0
prefix_5_rd_A	2147483647	1514	0	0
prefix_6_rd_A	2147483647	1475	0	0
prefix_7_rd_A	2147483647	1425	0	0
prefix_8_rd_A	2147483647	1369	0	0
prefix_9_rd_A	2147483647	1365	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	665167	0	0
T24	0	54726	0	0
T29	242999	0	0	0
T48	205713	30075	0	0
T49	0	74682	0	0
T77	141120	0	0	0
T121	60504	0	0	0
T136	0	50531	0	0
T137	0	73044	0	0
T138	0	26075	0	0
T139	0	33985	0	0
T140	0	40884	0	0
T141	0	29217	0	0
T142	0	55668	0	0
T143	10796	0	0	0
T144	284631	0	0	0
T145	229301	0	0	0
T146	706677	0	0	0
T147	176210	0	0	0
T148	966674	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1604	0	0
T85	228331	48	0	0
T99	0	18	0	0
T105	0	108	0	0
T106	0	77	0	0
T112	0	4	0	0
T129	0	127	0	0
T169	0	69	0	0
T170	0	12	0	0
T171	0	36	0	0
T172	0	3	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2136	0	0
T85	228331	101	0	0
T99	0	10	0	0
T112	0	6	0	0
T129	0	149	0	0
T134	0	25	0	0
T169	0	102	0	0
T170	0	30	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T182	0	8	0	0
T183	0	35	0	0
T184	0	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1366	0	0
T85	228331	66	0	0
T99	0	24	0	0
T105	0	47	0	0
T106	0	53	0	0
T112	0	4	0	0
T129	0	62	0	0
T169	0	41	0	0
T170	0	7	0	0
T171	0	10	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T184	0	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1562	0	0
T85	228331	56	0	0
T99	0	2	0	0
T105	0	74	0	0
T106	0	42	0	0
T112	0	4	0	0
T129	0	90	0	0
T169	0	46	0	0
T170	0	9	0	0
T171	0	40	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T184	0	5	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1616	0	0
T85	228331	89	0	0
T99	0	12	0	0
T105	0	56	0	0
T106	0	56	0	0
T112	0	4	0	0
T129	0	89	0	0
T169	0	47	0	0
T170	0	7	0	0
T171	0	6	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T184	0	13	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1411	0	0
T85	228331	99	0	0
T99	0	17	0	0
T105	0	95	0	0
T106	0	52	0	0
T112	0	4	0	0
T129	0	84	0	0
T169	0	40	0	0
T170	0	5	0	0
T171	0	28	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T185	0	16	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1490	0	0
T85	228331	92	0	0
T99	0	17	0	0
T105	0	67	0	0
T106	0	46	0	0
T112	0	7	0	0
T129	0	51	0	0
T169	0	35	0	0
T170	0	8	0	0
T171	0	4	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T184	0	10	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1441	0	0
T85	228331	49	0	0
T99	0	23	0	0
T105	0	77	0	0
T106	0	57	0	0
T112	0	9	0	0
T129	0	80	0	0
T169	0	35	0	0
T170	0	3	0	0
T171	0	19	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T184	0	9	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1514	0	0
T85	228331	71	0	0
T99	0	14	0	0
T105	0	69	0	0
T106	0	50	0	0
T112	0	7	0	0
T129	0	107	0	0
T169	0	43	0	0
T170	0	4	0	0
T171	0	23	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T184	0	5	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1475	0	0
T85	228331	42	0	0
T99	0	17	0	0
T105	0	46	0	0
T106	0	59	0	0
T112	0	1	0	0
T129	0	82	0	0
T169	0	48	0	0
T170	0	12	0	0
T171	0	28	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T185	0	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1425	0	0
T85	228331	58	0	0
T99	0	21	0	0
T105	0	76	0	0
T106	0	39	0	0
T112	0	1	0	0
T129	0	60	0	0
T169	0	44	0	0
T170	0	9	0	0
T171	0	28	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T184	0	13	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1369	0	0
T85	228331	86	0	0
T99	0	24	0	0
T105	0	69	0	0
T106	0	36	0	0
T112	0	9	0	0
T129	0	92	0	0
T169	0	34	0	0
T170	0	5	0	0
T171	0	20	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T184	0	18	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1365	0	0
T85	228331	84	0	0
T99	0	22	0	0
T105	0	66	0	0
T106	0	48	0	0
T112	0	8	0	0
T129	0	82	0	0
T169	0	39	0	0
T170	0	9	0	0
T171	0	20	0	0
T173	139949	0	0	0
T174	603914	0	0	0
T175	187669	0	0	0
T176	497059	0	0	0
T177	108896	0	0	0
T178	136964	0	0	0
T179	983243	0	0	0
T180	110278	0	0	0
T181	170340	0	0	0
T184	0	3	0	0