Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257946868

1

T1

4991

T2

408698

T3

714

full_word

182886096

1

T1

24042

T2

273742

T3

1066

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	440832694	1			T1	29033		T2	682440		T3	1780
auto[TlIntgErrCmd]	86	1			T134	6		T135	4		T136	1
auto[TlIntgErrData]	87	1			T134	6		T135	4		T136	2
auto[TlIntgErrBoth]	97	1			T134	8		T135	2		T136	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228139808

1

T1

16635

T2

361765

T3

757

auto[1]

212693156

1

T1

12398

T2

320675

T3

1023

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157403895	1			T1	2834		T2	253202		T3	410
auto[TlIntgErrNone]	partial	auto[1]	100542730	1			T1	2157		T2	155496		T3	304
auto[TlIntgErrNone]	full_word	auto[0]	70735794	1			T1	13801		T2	108563		T3	347
auto[TlIntgErrNone]	full_word	auto[1]	112150275	1			T1	10241		T2	165179		T3	719
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T134	2		T135	2		T191	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T134	4		T135	1		T136	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T193	1		T194	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T135	1		T166	1		T195	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T134	2		T135	1		T136	1
auto[TlIntgErrData]	partial	auto[1]	40	1			T134	3		T135	3		T136	1
auto[TlIntgErrData]	full_word	auto[0]	10	1			T134	1		T196	1		T197	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T193	1		T198	1		T199	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T134	2		T135	1		T136	5
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T134	5		T135	1		T136	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T191	1		T196	1		T200	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T134	1		T136	1		T191	1