Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	132460	0	0
entropy_period_rd_A	2147483647	1363	0	0
intr_enable_rd_A	2147483647	2028	0	0
prefix_0_rd_A	2147483647	1214	0	0
prefix_10_rd_A	2147483647	1248	0	0
prefix_1_rd_A	2147483647	1232	0	0
prefix_2_rd_A	2147483647	1292	0	0
prefix_3_rd_A	2147483647	1175	0	0
prefix_4_rd_A	2147483647	1220	0	0
prefix_5_rd_A	2147483647	1152	0	0
prefix_6_rd_A	2147483647	1373	0	0
prefix_7_rd_A	2147483647	1213	0	0
prefix_8_rd_A	2147483647	1287	0	0
prefix_9_rd_A	2147483647	1244	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	132460	0	0
T16	501498	67917	0	0
T25	117994	0	0	0
T27	0	42378	0	0
T35	4660	0	0	0
T52	0	4908	0	0
T68	71688	0	0	0
T69	13649	0	0	0
T70	153190	0	0	0
T71	603582	0	0	0
T72	151145	0	0	0
T73	272255	0	0	0
T74	190358	0	0	0
T140	0	13725	0	0
T141	0	166	0	0
T142	0	246	0	0
T143	0	4	0	0
T144	0	1	0	0
T145	0	298	0	0
T146	0	250	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1363	0	0
T33	793034	0	0	0
T52	471671	16	0	0
T136	0	62	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	13	0	0
T162	0	9	0	0
T163	0	68	0	0
T164	0	21	0	0
T165	0	6	0	0
T166	0	124	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2028	0	0
T33	793034	0	0	0
T52	471671	22	0	0
T136	0	106	0	0
T145	0	6	0	0
T159	0	11	0	0
T160	0	6	0	0
T161	0	26	0	0
T162	0	15	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0
T175	0	1	0	0
T176	0	30	0	0
T177	0	4	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1214	0	0
T33	793034	0	0	0
T52	471671	37	0	0
T136	0	37	0	0
T159	0	14	0	0
T160	0	6	0	0
T161	0	14	0	0
T162	0	9	0	0
T163	0	54	0	0
T164	0	6	0	0
T165	0	2	0	0
T166	0	87	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1248	0	0
T33	793034	0	0	0
T52	471671	38	0	0
T136	0	40	0	0
T159	0	7	0	0
T160	0	7	0	0
T161	0	3	0	0
T162	0	4	0	0
T163	0	47	0	0
T164	0	13	0	0
T165	0	5	0	0
T166	0	93	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1232	0	0
T33	793034	0	0	0
T52	471671	48	0	0
T136	0	40	0	0
T145	0	2	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	10	0	0
T162	0	11	0	0
T163	0	36	0	0
T164	0	5	0	0
T165	0	4	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1292	0	0
T33	793034	0	0	0
T52	471671	20	0	0
T136	0	31	0	0
T159	0	13	0	0
T160	0	2	0	0
T161	0	8	0	0
T162	0	9	0	0
T163	0	37	0	0
T164	0	16	0	0
T165	0	5	0	0
T166	0	54	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1175	0	0
T33	793034	0	0	0
T52	471671	18	0	0
T136	0	51	0	0
T159	0	6	0	0
T160	0	7	0	0
T161	0	12	0	0
T162	0	11	0	0
T163	0	44	0	0
T164	0	4	0	0
T165	0	10	0	0
T166	0	93	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1220	0	0
T33	793034	0	0	0
T52	471671	14	0	0
T95	0	27	0	0
T136	0	32	0	0
T159	0	9	0	0
T160	0	8	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	43	0	0
T164	0	14	0	0
T166	0	86	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1152	0	0
T33	793034	0	0	0
T52	471671	31	0	0
T136	0	15	0	0
T159	0	6	0	0
T160	0	14	0	0
T161	0	15	0	0
T162	0	12	0	0
T163	0	61	0	0
T164	0	9	0	0
T165	0	6	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0
T178	0	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1373	0	0
T33	793034	0	0	0
T52	471671	29	0	0
T136	0	49	0	0
T159	0	8	0	0
T160	0	10	0	0
T161	0	10	0	0
T162	0	6	0	0
T163	0	66	0	0
T164	0	6	0	0
T165	0	6	0	0
T166	0	79	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1213	0	0
T33	793034	0	0	0
T52	471671	22	0	0
T136	0	59	0	0
T159	0	12	0	0
T160	0	10	0	0
T161	0	12	0	0
T162	0	3	0	0
T163	0	20	0	0
T164	0	10	0	0
T165	0	5	0	0
T166	0	81	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1287	0	0
T33	793034	0	0	0
T52	471671	30	0	0
T136	0	44	0	0
T159	0	13	0	0
T160	0	18	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	44	0	0
T164	0	7	0	0
T165	0	2	0	0
T166	0	83	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1244	0	0
T33	793034	0	0	0
T52	471671	24	0	0
T136	0	58	0	0
T159	0	16	0	0
T160	0	9	0	0
T161	0	9	0	0
T162	0	8	0	0
T163	0	54	0	0
T164	0	6	0	0
T165	0	9	0	0
T166	0	67	0	0
T167	201783	0	0	0
T168	334194	0	0	0
T169	529408	0	0	0
T170	495154	0	0	0
T171	101863	0	0	0
T172	315823	0	0	0
T173	319041	0	0	0
T174	3936	0	0	0