Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
184697 |
1 |
|
|
T7 |
1241 |
|
T8 |
120 |
|
T9 |
369 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
95867 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
65935 |
1 |
|
|
T7 |
100 |
|
T8 |
118 |
|
T9 |
364 |
seven_bytes |
3299 |
1 |
|
|
T7 |
31 |
|
T67 |
30 |
|
T71 |
36 |
six_bytes |
3260 |
1 |
|
|
T7 |
28 |
|
T67 |
38 |
|
T71 |
36 |
five_bytes |
3346 |
1 |
|
|
T7 |
34 |
|
T67 |
22 |
|
T71 |
67 |
four_bytes |
3294 |
1 |
|
|
T7 |
27 |
|
T67 |
34 |
|
T71 |
38 |
three_bytes |
3239 |
1 |
|
|
T7 |
42 |
|
T67 |
32 |
|
T71 |
52 |
two_bytes |
3221 |
1 |
|
|
T7 |
33 |
|
T67 |
29 |
|
T71 |
50 |
one_byte |
3236 |
1 |
|
|
T7 |
37 |
|
T67 |
37 |
|
T71 |
55 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181203 |
1 |
|
|
T7 |
1225 |
|
T8 |
116 |
|
T9 |
359 |
auto[1] |
3494 |
1 |
|
|
T7 |
16 |
|
T8 |
4 |
|
T9 |
10 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
184697 |
1 |
|
|
T7 |
1241 |
|
T8 |
120 |
|
T9 |
369 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
184692 |
1 |
|
|
T7 |
1241 |
|
T8 |
120 |
|
T9 |
369 |
auto[1] |
5 |
1 |
|
|
T161 |
1 |
|
T62 |
1 |
|
T162 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1234 |
1 |
|
|
T7 |
4 |
|
T8 |
2 |
|
T9 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3494 |
1 |
|
|
T7 |
16 |
|
T8 |
4 |
|
T9 |
10 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176212 |
1 |
|
|
T7 |
1470 |
|
T8 |
215 |
|
T38 |
717 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
91961 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62331 |
1 |
|
|
T7 |
151 |
|
T8 |
212 |
|
T38 |
705 |
seven_bytes |
3111 |
1 |
|
|
T7 |
38 |
|
T19 |
27 |
|
T67 |
50 |
six_bytes |
3110 |
1 |
|
|
T7 |
36 |
|
T19 |
17 |
|
T67 |
65 |
five_bytes |
3140 |
1 |
|
|
T7 |
47 |
|
T19 |
11 |
|
T67 |
54 |
four_bytes |
3152 |
1 |
|
|
T7 |
42 |
|
T19 |
11 |
|
T67 |
45 |
three_bytes |
3184 |
1 |
|
|
T7 |
47 |
|
T19 |
8 |
|
T67 |
56 |
two_bytes |
3183 |
1 |
|
|
T7 |
26 |
|
T19 |
19 |
|
T67 |
60 |
one_byte |
3040 |
1 |
|
|
T7 |
28 |
|
T19 |
15 |
|
T67 |
56 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172770 |
1 |
|
|
T7 |
1452 |
|
T8 |
209 |
|
T38 |
693 |
auto[1] |
3442 |
1 |
|
|
T7 |
18 |
|
T8 |
6 |
|
T38 |
24 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176212 |
1 |
|
|
T7 |
1470 |
|
T8 |
215 |
|
T38 |
717 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176203 |
1 |
|
|
T7 |
1470 |
|
T8 |
215 |
|
T38 |
717 |
auto[1] |
9 |
1 |
|
|
T19 |
1 |
|
T163 |
1 |
|
T164 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1176 |
1 |
|
|
T7 |
5 |
|
T8 |
3 |
|
T38 |
12 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3442 |
1 |
|
|
T7 |
18 |
|
T8 |
6 |
|
T38 |
24 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349533 |
1 |
|
|
T7 |
1910 |
|
T8 |
551 |
|
T9 |
70 |
auto[1] |
436 |
1 |
|
|
T10 |
57 |
|
T11 |
34 |
|
T12 |
60 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
183347 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
122968 |
1 |
|
|
T7 |
216 |
|
T8 |
542 |
|
T9 |
68 |
seven_bytes |
6140 |
1 |
|
|
T7 |
41 |
|
T19 |
2 |
|
T67 |
56 |
six_bytes |
6314 |
1 |
|
|
T7 |
45 |
|
T19 |
6 |
|
T67 |
63 |
five_bytes |
6168 |
1 |
|
|
T7 |
51 |
|
T19 |
4 |
|
T67 |
61 |
four_bytes |
6289 |
1 |
|
|
T7 |
46 |
|
T19 |
2 |
|
T67 |
67 |
three_bytes |
6238 |
1 |
|
|
T7 |
49 |
|
T19 |
1 |
|
T67 |
76 |
two_bytes |
6290 |
1 |
|
|
T7 |
58 |
|
T19 |
4 |
|
T67 |
59 |
one_byte |
6215 |
1 |
|
|
T7 |
43 |
|
T19 |
3 |
|
T67 |
54 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
343218 |
1 |
|
|
T7 |
1880 |
|
T8 |
533 |
|
T9 |
66 |
auto[1] |
6751 |
1 |
|
|
T7 |
30 |
|
T8 |
18 |
|
T9 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349969 |
1 |
|
|
T7 |
1910 |
|
T8 |
551 |
|
T9 |
70 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349944 |
1 |
|
|
T7 |
1910 |
|
T8 |
551 |
|
T9 |
70 |
auto[1] |
25 |
1 |
|
|
T67 |
1 |
|
T68 |
1 |
|
T165 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2325 |
1 |
|
|
T7 |
8 |
|
T8 |
9 |
|
T9 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6751 |
1 |
|
|
T7 |
30 |
|
T8 |
18 |
|
T9 |
4 |