Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	261742681	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

187065438

1

T1

323711

T2

66057

T3

188

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	232814632	1			T1	433921		T2	89802		T3	87
values[0x0]	103828378	1			T1	205879		T2	19249		T3	63
values[0x1]	112165109	1			T1	225306		T2	20297		T3	65

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203451886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

245356233

1

T1

443716

T2

82038

T3

190

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1390319	1			T1	3296		T2	493		T7	3075
valid_sources[0x01]	1425597	1			T1	3527		T2	496		T7	3473
valid_sources[0x02]	1378985	1			T1	3252		T2	508		T7	3375
valid_sources[0x03]	1884353	1			T1	3241		T2	524		T7	3466
valid_sources[0x04]	2040426	1			T1	3517		T2	505		T7	3226
valid_sources[0x05]	1382921	1			T1	3365		T2	526		T7	3186
valid_sources[0x06]	1384489	1			T1	3195		T2	493		T7	3384
valid_sources[0x07]	1391216	1			T1	3426		T2	483		T7	3528
valid_sources[0x08]	1383841	1			T1	3378		T2	473		T7	3231
valid_sources[0x09]	1384331	1			T1	3411		T2	502		T7	3265
valid_sources[0x0a]	1386440	1			T1	3396		T2	509		T7	3074
valid_sources[0x0b]	2234541	1			T1	3412		T2	512		T7	3300
valid_sources[0x0c]	1383393	1			T1	3543		T2	517		T7	3490
valid_sources[0x0d]	1390122	1			T1	3373		T2	529		T7	3033
valid_sources[0x0e]	1406259	1			T1	3540		T2	532		T7	3260
valid_sources[0x0f]	1388664	1			T1	3375		T2	493		T7	3492
valid_sources[0x10]	1824547	1			T1	3326		T2	525		T7	3424
valid_sources[0x11]	1391150	1			T1	3458		T2	577		T7	3170
valid_sources[0x12]	3698399	1			T1	3401		T2	517		T7	3273
valid_sources[0x13]	1392343	1			T1	3251		T2	427		T7	3513
valid_sources[0x14]	1380822	1			T1	3398		T2	493		T7	3228
valid_sources[0x15]	1391488	1			T1	3445		T2	481		T7	3141
valid_sources[0x16]	1383880	1			T1	3344		T2	533		T7	3496
valid_sources[0x17]	1518918	1			T1	3329		T2	482		T7	3348
valid_sources[0x18]	1407601	1			T1	3377		T2	482		T7	3295
valid_sources[0x19]	1495643	1			T1	3390		T2	514		T7	3166
valid_sources[0x1a]	1382229	1			T1	3419		T2	522		T7	3316
valid_sources[0x1b]	1387522	1			T1	3160		T2	499		T7	3256
valid_sources[0x1c]	1382072	1			T1	3289		T2	504		T7	3335
valid_sources[0x1d]	1391998	1			T1	3517		T2	454		T7	3224
valid_sources[0x1e]	4510367	1			T1	3267		T2	551		T7	3373
valid_sources[0x1f]	1377162	1			T1	3199		T2	487		T7	3283
valid_sources[0x20]	1382249	1			T1	3288		T2	492		T7	3434
valid_sources[0x21]	1381823	1			T1	3281		T2	491		T7	3174
valid_sources[0x22]	1387087	1			T1	3567		T2	516		T7	3442
valid_sources[0x23]	3703452	1			T1	3388		T2	504		T7	3306
valid_sources[0x24]	1386777	1			T1	3429		T2	518		T7	3473
valid_sources[0x25]	3347163	1			T1	3411		T2	515		T7	3488
valid_sources[0x26]	2992139	1			T1	3476		T2	497		T3	213
valid_sources[0x27]	1507049	1			T1	3489		T2	530		T7	3312
valid_sources[0x28]	1387901	1			T1	3538		T2	508		T7	3361
valid_sources[0x29]	1391959	1			T1	3411		T2	516		T7	3202
valid_sources[0x2a]	1386015	1			T1	3136		T2	515		T7	3423
valid_sources[0x2b]	1389062	1			T1	3587		T2	518		T7	3373
valid_sources[0x2c]	1384173	1			T1	3415		T2	535		T7	3315
valid_sources[0x2d]	1391290	1			T1	3364		T2	483		T7	3262
valid_sources[0x2e]	1419811	1			T1	3396		T2	485		T7	3181
valid_sources[0x2f]	1855577	1			T1	3602		T2	495		T7	3318
valid_sources[0x30]	1411670	1			T1	3354		T2	467		T7	3388
valid_sources[0x31]	1570512	1			T1	3382		T2	530		T7	3339
valid_sources[0x32]	1386843	1			T1	3409		T2	472		T7	3329
valid_sources[0x33]	1385868	1			T1	3426		T2	488		T7	3063
valid_sources[0x34]	1434778	1			T1	3347		T2	517		T7	3350
valid_sources[0x35]	1386247	1			T1	3389		T2	518		T7	3311
valid_sources[0x36]	1384741	1			T1	3330		T2	518		T7	3347
valid_sources[0x37]	1515012	1			T1	3325		T2	427		T7	3131
valid_sources[0x38]	1391780	1			T1	3284		T2	500		T7	3420
valid_sources[0x39]	1638387	1			T1	3391		T2	528		T7	3278
valid_sources[0x3a]	2294751	1			T1	3362		T2	475		T7	3238
valid_sources[0x3b]	1785287	1			T1	3477		T2	496		T7	3270
valid_sources[0x3c]	1507654	1			T1	3095		T2	465		T7	3432
valid_sources[0x3d]	2293893	1			T1	3145		T2	495		T7	3459
valid_sources[0x3e]	2176213	1			T1	3243		T2	497		T7	3207
valid_sources[0x3f]	1640871	1			T1	3391		T2	484		T7	3246
valid_sources[0x40]	1385438	1			T1	3385		T2	506		T7	3343
valid_sources[0x41]	1437567	1			T1	3316		T2	473		T7	3251
valid_sources[0x42]	1389470	1			T1	3465		T2	497		T7	3398
valid_sources[0x43]	1382259	1			T1	3245		T2	492		T7	3401
valid_sources[0x44]	1604482	1			T1	3484		T2	562		T7	3210
valid_sources[0x45]	1387516	1			T1	3283		T2	504		T7	3547
valid_sources[0x46]	1846097	1			T1	3364		T2	515		T7	3272
valid_sources[0x47]	3696606	1			T1	3268		T2	513		T7	3118
valid_sources[0x48]	2054867	1			T1	3372		T2	496		T7	3329
valid_sources[0x49]	1392001	1			T1	3256		T2	533		T7	3152
valid_sources[0x4a]	1389261	1			T1	3286		T2	494		T7	3338
valid_sources[0x4b]	1379883	1			T1	3549		T2	501		T7	3453
valid_sources[0x4c]	1383891	1			T1	3516		T2	518		T7	3105
valid_sources[0x4d]	1425685	1			T1	3482		T2	523		T7	3376
valid_sources[0x4e]	2248701	1			T1	3253		T2	504		T7	3294
valid_sources[0x4f]	1486272	1			T1	3509		T2	484		T7	3319
valid_sources[0x50]	1386329	1			T1	3381		T2	495		T7	3292
valid_sources[0x51]	1849425	1			T1	3335		T2	486		T7	3191
valid_sources[0x52]	1393276	1			T1	3247		T2	532		T7	3297
valid_sources[0x53]	1389639	1			T1	3345		T2	512		T7	3422
valid_sources[0x54]	1842835	1			T1	3223		T2	502		T7	3294
valid_sources[0x55]	3372624	1			T1	3451		T2	496		T7	3432
valid_sources[0x56]	1387315	1			T1	3259		T2	493		T7	3180
valid_sources[0x57]	1393911	1			T1	3424		T2	482		T7	3512
valid_sources[0x58]	1380359	1			T1	3454		T2	492		T7	3473
valid_sources[0x59]	1383588	1			T1	3503		T2	528		T7	3308
valid_sources[0x5a]	1725371	1			T1	3270		T2	525		T7	3189
valid_sources[0x5b]	1407063	1			T1	3366		T2	532		T7	3368
valid_sources[0x5c]	1381015	1			T1	3640		T2	494		T7	3483
valid_sources[0x5d]	2688448	1			T1	3186		T2	550		T7	3158
valid_sources[0x5e]	1388747	1			T1	3365		T2	513		T7	3364
valid_sources[0x5f]	2294544	1			T1	3521		T2	477		T7	3235
valid_sources[0x60]	1844424	1			T1	3244		T2	490		T7	3394
valid_sources[0x61]	1391917	1			T1	3292		T2	533		T7	3117
valid_sources[0x62]	3349058	1			T1	3348		T2	525		T7	3215
valid_sources[0x63]	2244540	1			T1	3235		T2	547		T7	3334
valid_sources[0x64]	1935545	1			T1	3342		T2	516		T7	3399
valid_sources[0x65]	1385203	1			T1	3337		T2	514		T7	3363
valid_sources[0x66]	1384916	1			T1	3412		T2	515		T7	3435
valid_sources[0x67]	1389493	1			T1	3438		T2	491		T7	3437
valid_sources[0x68]	1407206	1			T1	3394		T2	468		T7	3478
valid_sources[0x69]	1464972	1			T1	3242		T2	490		T7	3166
valid_sources[0x6a]	1998289	1			T1	3407		T2	502		T7	3488
valid_sources[0x6b]	3735916	1			T1	3367		T2	523		T7	3275
valid_sources[0x6c]	1384704	1			T1	3375		T2	528		T7	3276
valid_sources[0x6d]	3733278	1			T1	3431		T2	516		T7	3294
valid_sources[0x6e]	1386458	1			T1	3343		T2	460		T7	3351
valid_sources[0x6f]	1470269	1			T1	3134		T2	511		T7	3285
valid_sources[0x70]	2431456	1			T1	3474		T2	484		T7	3533
valid_sources[0x71]	1376664	1			T1	3323		T2	458		T7	3261
valid_sources[0x72]	1389534	1			T1	3380		T2	496		T7	3386
valid_sources[0x73]	1378295	1			T1	3358		T2	512		T7	3068
valid_sources[0x74]	1385744	1			T1	3459		T2	498		T7	3397
valid_sources[0x75]	1386899	1			T1	3340		T2	529		T7	3203
valid_sources[0x76]	1388508	1			T1	3212		T2	552		T7	3280
valid_sources[0x77]	1385612	1			T1	3157		T2	527		T7	3353
valid_sources[0x78]	1385345	1			T1	3413		T2	508		T7	3496
valid_sources[0x79]	3719343	1			T1	3584		T2	463		T7	3520
valid_sources[0x7a]	1386196	1			T1	3529		T2	540		T7	3299
valid_sources[0x7b]	1389492	1			T1	3565		T2	496		T7	3242
valid_sources[0x7c]	1591231	1			T1	3408		T2	520		T7	3224
valid_sources[0x7d]	2268909	1			T1	3436		T2	474		T7	3306
valid_sources[0x7e]	1540959	1			T1	3260		T2	485		T7	3289
valid_sources[0x7f]	2233212	1			T1	3335		T2	524		T7	3160
valid_sources[0x80]	1380554	1			T1	3537		T2	481		T7	3520

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72589792

1

T1

113353

T2

43995

T3

73

values[0x0]

all_enables

biggest_size

61491600

1

T1

114458

T2

11880

T3

52

values[0x1]

all_enables

biggest_size

52984046

1

T1

95900

T2

10182

T3

63