Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262869731

1

T1

541395

T2

63291

T3

27

full_word

187136100

1

T1

323711

T2

66057

T3

188

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450005561	1			T1	865106		T2	129348		T3	215
auto[TlIntgErrCmd]	99	1			T123	9		T124	5		T125	2
auto[TlIntgErrData]	81	1			T123	9		T124	3		T125	2
auto[TlIntgErrBoth]	90	1			T123	2		T124	2		T125	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233033610

1

T1

433921

T2

89802

T3

87

auto[1]

216972221

1

T1

431185

T2

39546

T3

128

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	160425906	1			T1	320568		T2	45807		T3	14
auto[TlIntgErrNone]	partial	auto[1]	102443573	1			T1	220827		T2	17484		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	72607581	1			T1	113353		T2	43995		T3	73
auto[TlIntgErrNone]	full_word	auto[1]	114528501	1			T1	210358		T2	22062		T3	115
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T123	1		T124	3		T125	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T123	5		T124	2		T171	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T123	2		T172	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T123	1		T125	1		T173	1
auto[TlIntgErrData]	partial	auto[0]	36	1			T123	4		T124	1		T125	1
auto[TlIntgErrData]	partial	auto[1]	39	1			T123	5		T124	1		T125	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T124	1		T168	1		T173	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T169	1		T174	1		T175	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T124	1		T125	3		T171	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T123	2		T124	1		T125	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T125	1		T169	1		T176	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T177	1		T176	1		T175	1