Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	259046	0	0
entropy_period_rd_A	2147483647	1482	0	0
intr_enable_rd_A	2147483647	2391	0	0
prefix_0_rd_A	2147483647	1830	0	0
prefix_10_rd_A	2147483647	1979	0	0
prefix_1_rd_A	2147483647	1911	0	0
prefix_2_rd_A	2147483647	1937	0	0
prefix_3_rd_A	2147483647	1938	0	0
prefix_4_rd_A	2147483647	1971	0	0
prefix_5_rd_A	2147483647	2005	0	0
prefix_6_rd_A	2147483647	1973	0	0
prefix_7_rd_A	2147483647	1882	0	0
prefix_8_rd_A	2147483647	1958	0	0
prefix_9_rd_A	2147483647	1989	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	259046	0	0
T7	608557	54712	0	0
T8	141157	0	0	0
T9	68797	0	0	0
T20	503412	0	0	0
T34	365392	0	0	0
T35	219839	0	0	0
T36	260186	0	0	0
T37	531702	0	0	0
T38	157453	0	0	0
T39	147087	0	0	0
T45	0	2775	0	0
T46	0	47878	0	0
T129	0	57263	0	0
T130	0	93213	0	0
T131	0	37	0	0
T132	0	2	0	0
T133	0	2	0	0
T134	0	452	0	0
T135	0	57	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1482	0	0
T96	5026	11	0	0
T97	2024	2	0	0
T99	12090	70	0	0
T132	4411	7	0	0
T144	3261	12	0	0
T145	3951	3	0	0
T146	10636	27	0	0
T147	5811	2	0	0
T148	8144	25	0	0
T149	2774	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2391	0	0
T96	5026	4	0	0
T99	12090	70	0	0
T126	1157	12	0	0
T132	4411	16	0	0
T144	3261	8	0	0
T145	3951	9	0	0
T146	10636	22	0	0
T150	1188	7	0	0
T151	1541	8	0	0
T152	1063	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1830	0	0
T96	5026	12	0	0
T97	2024	5	0	0
T99	12090	69	0	0
T132	4411	15	0	0
T144	3261	5	0	0
T145	3951	7	0	0
T146	10636	12	0	0
T148	8144	10	0	0
T149	2774	11	0	0
T153	3113	21	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1979	0	0
T96	5026	6	0	0
T97	2024	5	0	0
T99	12090	80	0	0
T132	4411	3	0	0
T144	3261	1	0	0
T145	3951	17	0	0
T146	10636	6	0	0
T147	5811	3	0	0
T148	8144	14	0	0
T149	2774	7	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1911	0	0
T96	5026	4	0	0
T97	2024	7	0	0
T99	12090	66	0	0
T132	4411	11	0	0
T144	3261	10	0	0
T145	3951	3	0	0
T146	10636	14	0	0
T147	5811	36	0	0
T148	8144	7	0	0
T149	2774	13	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1937	0	0
T96	5026	2	0	0
T97	2024	5	0	0
T99	12090	36	0	0
T132	4411	9	0	0
T144	3261	11	0	0
T145	3951	12	0	0
T146	10636	7	0	0
T148	8144	18	0	0
T149	2774	5	0	0
T153	3113	4	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1938	0	0
T97	2024	3	0	0
T99	12090	64	0	0
T132	4411	8	0	0
T144	3261	9	0	0
T145	3951	14	0	0
T146	10636	32	0	0
T147	5811	21	0	0
T148	8144	20	0	0
T149	2774	5	0	0
T153	3113	2	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1971	0	0
T96	5026	5	0	0
T99	12090	61	0	0
T132	4411	3	0	0
T144	3261	9	0	0
T145	3951	6	0	0
T146	10636	17	0	0
T147	5811	15	0	0
T148	8144	17	0	0
T149	2774	11	0	0
T153	3113	10	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2005	0	0
T96	5026	18	0	0
T97	2024	5	0	0
T99	12090	67	0	0
T132	4411	2	0	0
T144	3261	12	0	0
T145	3951	8	0	0
T146	10636	68	0	0
T147	5811	18	0	0
T148	8144	10	0	0
T149	2774	12	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1973	0	0
T97	2024	7	0	0
T99	12090	88	0	0
T132	4411	5	0	0
T144	3261	9	0	0
T145	3951	8	0	0
T146	10636	16	0	0
T147	5811	6	0	0
T148	8144	17	0	0
T149	2774	6	0	0
T153	3113	12	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1882	0	0
T96	5026	10	0	0
T97	2024	3	0	0
T99	12090	65	0	0
T144	3261	6	0	0
T145	3951	8	0	0
T146	10636	37	0	0
T147	5811	5	0	0
T148	8144	25	0	0
T149	2774	14	0	0
T153	3113	11	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1958	0	0
T96	5026	9	0	0
T97	2024	9	0	0
T99	12090	68	0	0
T132	4411	2	0	0
T144	3261	13	0	0
T145	3951	15	0	0
T146	10636	35	0	0
T148	8144	15	0	0
T149	2774	13	0	0
T153	3113	19	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1989	0	0
T96	5026	7	0	0
T97	2024	2	0	0
T99	12090	71	0	0
T132	4411	2	0	0
T144	3261	6	0	0
T145	3951	6	0	0
T146	10636	44	0	0
T147	5811	1	0	0
T148	8144	14	0	0
T149	2774	11	0	0