Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	261855267	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

187369915

1

T2

13765

T3

273788

T17

792842

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	232162542	1			T1	1		T2	9687		T3	350084
values[0x0]	104351607	1			T2	3337		T3	152369		T17	447354
values[0x1]	112711033	1			T1	2		T2	3429		T3	165213

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203634547	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

245590635

1

T1

2

T2

14518

T3

360187

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1578873	1			T2	103		T3	334		T17	7743
valid_sources[0x01]	1319690	1			T2	59		T3	344		T17	7478
valid_sources[0x02]	1349995	1			T2	55		T3	353		T17	7457
valid_sources[0x03]	1318728	1			T2	55		T3	368		T17	7435
valid_sources[0x04]	1320494	1			T2	51		T3	345		T17	7637
valid_sources[0x05]	2224722	1			T2	66		T3	321		T17	7484
valid_sources[0x06]	1805221	1			T2	52		T3	333		T17	7745
valid_sources[0x07]	1315769	1			T2	47		T3	298		T17	7415
valid_sources[0x08]	2217293	1			T2	71		T3	379		T17	7624
valid_sources[0x09]	1322457	1			T2	81		T3	383		T17	7523
valid_sources[0x0a]	1327161	1			T2	67		T3	334		T17	7570
valid_sources[0x0b]	1337890	1			T2	55		T3	321		T17	7565
valid_sources[0x0c]	6316083	1			T2	61		T3	346		T17	7635
valid_sources[0x0d]	1974863	1			T2	47		T3	333		T17	7574
valid_sources[0x0e]	1321074	1			T2	63		T3	360		T17	7388
valid_sources[0x0f]	1368730	1			T2	64		T3	375		T17	7387
valid_sources[0x10]	1316992	1			T2	72		T3	362		T17	7322
valid_sources[0x11]	2224107	1			T2	47		T3	391		T17	7600
valid_sources[0x12]	2474573	1			T2	64		T3	337		T17	7683
valid_sources[0x13]	2191382	1			T2	86		T3	378		T17	7677
valid_sources[0x14]	1444458	1			T2	99		T3	359		T17	7782
valid_sources[0x15]	1320981	1			T2	45		T3	356		T17	7588
valid_sources[0x16]	1316233	1			T2	47		T3	372		T17	7600
valid_sources[0x17]	1323807	1			T2	65		T3	377		T17	7812
valid_sources[0x18]	2240107	1			T2	69		T3	342		T17	7632
valid_sources[0x19]	1445156	1			T2	60		T3	331		T17	7741
valid_sources[0x1a]	1321926	1			T2	56		T3	363		T17	7579
valid_sources[0x1b]	1324067	1			T2	75		T3	386		T17	7530
valid_sources[0x1c]	1325152	1			T2	56		T3	335		T17	7526
valid_sources[0x1d]	1322096	1			T2	51		T3	322		T17	7780
valid_sources[0x1e]	1506987	1			T2	51		T3	329		T17	7588
valid_sources[0x1f]	3646260	1			T2	65		T3	378		T17	7639
valid_sources[0x20]	1315317	1			T2	57		T3	334		T17	7528
valid_sources[0x21]	1322693	1			T2	82		T3	338		T17	7688
valid_sources[0x22]	3267485	1			T2	60		T3	388		T17	7617
valid_sources[0x23]	1320368	1			T2	55		T3	348		T17	7618
valid_sources[0x24]	4540456	1			T2	81		T3	350		T17	7679
valid_sources[0x25]	1325813	1			T2	65		T3	359		T17	7588
valid_sources[0x26]	1351191	1			T2	81		T3	351		T17	7415
valid_sources[0x27]	1311968	1			T2	57		T3	338		T17	7440
valid_sources[0x28]	1322098	1			T2	63		T3	348		T17	7700
valid_sources[0x29]	1580285	1			T2	54		T3	334		T17	7588
valid_sources[0x2a]	2053464	1			T2	77		T3	319		T17	7678
valid_sources[0x2b]	2182201	1			T2	55		T3	314		T17	7620
valid_sources[0x2c]	1318020	1			T2	51		T3	339		T17	7634
valid_sources[0x2d]	1320800	1			T2	75		T3	314		T17	7699
valid_sources[0x2e]	1316315	1			T2	56		T3	359		T17	7446
valid_sources[0x2f]	1324278	1			T2	50		T3	353		T17	7700
valid_sources[0x30]	1323008	1			T2	80		T3	349		T17	7647
valid_sources[0x31]	1321106	1			T2	90		T3	370		T17	7692
valid_sources[0x32]	1325829	1			T2	67		T3	365		T17	7478
valid_sources[0x33]	1325593	1			T2	58		T3	337		T17	7485
valid_sources[0x34]	2202880	1			T2	66		T3	339		T17	7791
valid_sources[0x35]	1326638	1			T2	54		T3	317		T17	7569
valid_sources[0x36]	1320335	1			T2	68		T3	330		T17	7460
valid_sources[0x37]	1362738	1			T2	50		T3	368		T17	7553
valid_sources[0x38]	1316180	1			T2	85		T3	348		T17	7470
valid_sources[0x39]	1322691	1			T2	58		T3	333		T17	7428
valid_sources[0x3a]	1323421	1			T2	75		T3	334		T17	7638
valid_sources[0x3b]	1323420	1			T2	69		T3	342		T17	7336
valid_sources[0x3c]	3592167	1			T2	75		T3	332		T17	7719
valid_sources[0x3d]	3294369	1			T2	35		T3	335		T17	7598
valid_sources[0x3e]	1323314	1			T2	48		T3	324		T17	7519
valid_sources[0x3f]	2203058	1			T2	71		T3	345		T17	7601
valid_sources[0x40]	1317512	1			T1	1		T2	76		T3	359
valid_sources[0x41]	1314303	1			T2	103		T3	350		T17	7622
valid_sources[0x42]	1321217	1			T2	59		T3	323		T17	7571
valid_sources[0x43]	1314172	1			T2	54		T3	319		T17	7489
valid_sources[0x44]	1331639	1			T2	56		T3	336		T17	7461
valid_sources[0x45]	1784243	1			T2	72		T3	363		T17	7446
valid_sources[0x46]	1911017	1			T2	53		T3	358		T17	7643
valid_sources[0x47]	3287854	1			T2	47		T3	372		T17	7616
valid_sources[0x48]	1423502	1			T2	66		T3	337		T17	7614
valid_sources[0x49]	1319173	1			T2	62		T3	304		T17	7614
valid_sources[0x4a]	1327231	1			T2	84		T3	330		T17	7509
valid_sources[0x4b]	1324997	1			T2	60		T3	332		T17	7618
valid_sources[0x4c]	1572562	1			T2	64		T3	358		T17	7574
valid_sources[0x4d]	1317585	1			T2	42		T3	339		T17	7591
valid_sources[0x4e]	1782559	1			T2	66		T3	374		T17	7517
valid_sources[0x4f]	1434316	1			T2	59		T3	334		T17	7561
valid_sources[0x50]	2262897	1			T2	54		T3	336		T17	7740
valid_sources[0x51]	1320292	1			T2	65		T3	317		T17	7727
valid_sources[0x52]	1809532	1			T2	72		T3	366		T17	7675
valid_sources[0x53]	1316207	1			T2	69		T3	357		T17	7512
valid_sources[0x54]	1322135	1			T2	55		T3	358		T17	7703
valid_sources[0x55]	1323958	1			T2	59		T3	344		T17	7623
valid_sources[0x56]	2256809	1			T2	44		T3	333		T17	7600
valid_sources[0x57]	1318683	1			T2	80		T3	330		T17	7695
valid_sources[0x58]	1322499	1			T2	73		T3	335		T17	7541
valid_sources[0x59]	1315785	1			T2	56		T3	351		T17	7776
valid_sources[0x5a]	1317560	1			T2	63		T3	329		T17	7482
valid_sources[0x5b]	1409511	1			T2	80		T3	363		T17	7716
valid_sources[0x5c]	1325551	1			T1	1		T2	80		T3	352
valid_sources[0x5d]	2321954	1			T2	35		T3	343		T17	7581
valid_sources[0x5e]	1320340	1			T2	61		T3	343		T17	7668
valid_sources[0x5f]	1454956	1			T2	45		T3	342		T17	7534
valid_sources[0x60]	1323336	1			T2	55		T3	350		T17	7739
valid_sources[0x61]	1323727	1			T2	91		T3	309		T17	7717
valid_sources[0x62]	1333935	1			T2	67		T3	339		T17	7731
valid_sources[0x63]	3510140	1			T2	52		T3	341		T17	7713
valid_sources[0x64]	1326567	1			T2	69		T3	335		T17	7594
valid_sources[0x65]	1316650	1			T2	65		T3	342		T17	7474
valid_sources[0x66]	1321930	1			T2	62		T3	327		T17	7650
valid_sources[0x67]	2168344	1			T2	73		T3	364		T17	7446
valid_sources[0x68]	4525491	1			T2	69		T3	336		T17	7465
valid_sources[0x69]	1318856	1			T2	69		T3	308		T17	7482
valid_sources[0x6a]	1777878	1			T2	77		T3	329		T17	7552
valid_sources[0x6b]	1321510	1			T2	70		T3	355		T17	7587
valid_sources[0x6c]	2188711	1			T2	45		T3	368		T17	7549
valid_sources[0x6d]	1710741	1			T2	82		T3	366		T17	7637
valid_sources[0x6e]	1321444	1			T2	69		T3	327		T17	7575
valid_sources[0x6f]	6470151	1			T2	57		T3	327		T17	7500
valid_sources[0x70]	1321378	1			T2	49		T3	335		T17	7500
valid_sources[0x71]	2410104	1			T2	55		T3	341		T17	7631
valid_sources[0x72]	2288587	1			T2	60		T3	377		T17	7804
valid_sources[0x73]	1312209	1			T2	41		T3	315		T17	7515
valid_sources[0x74]	1685113	1			T2	55		T3	343		T17	7649
valid_sources[0x75]	1324448	1			T2	61		T3	338		T17	7689
valid_sources[0x76]	1317397	1			T2	66		T3	335		T17	7695
valid_sources[0x77]	1319165	1			T2	65		T3	364		T17	7553
valid_sources[0x78]	1321201	1			T2	56		T3	343		T17	7463
valid_sources[0x79]	1318407	1			T2	62		T3	305		T17	7508
valid_sources[0x7a]	1327115	1			T2	50		T3	345		T17	7621
valid_sources[0x7b]	4537010	1			T2	81		T3	328		T17	7624
valid_sources[0x7c]	1318245	1			T2	43		T3	389		T17	7580
valid_sources[0x7d]	1320116	1			T2	70		T3	344		T17	7801
valid_sources[0x7e]	1325199	1			T2	65		T3	323		T17	7631
valid_sources[0x7f]	3640207	1			T2	79		T3	336		T17	7677
valid_sources[0x80]	3018364	1			T2	81		T3	365		T17	7644

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72317954

1

T2

8182

T3

110914

T17

323379

values[0x0]

all_enables

biggest_size

61804214

1

T2

2799

T3

88028

T17

254691

values[0x1]

all_enables

biggest_size

53247747

1

T2

2784

T3

74846

T17

214772