Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262263906

1

T1

3

T2

2688

T3

393878

full_word

187395649

1

T2

13765

T3

273788

T17

792842

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	449659245	1			T1	3		T2	16453		T3	667666
auto[TlIntgErrCmd]	115	1			T111	9		T128	6		T129	7
auto[TlIntgErrData]	100	1			T111	5		T128	3		T129	5
auto[TlIntgErrBoth]	95	1			T111	6		T128	1		T129	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232242383

1

T1

1

T2

9687

T3

350084

auto[1]

217417172

1

T1

2

T2

6766

T3

317582

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159917855	1			T1	1		T2	1505		T3	239170
auto[TlIntgErrNone]	partial	auto[1]	102345768	1			T1	2		T2	1183		T3	154708
auto[TlIntgErrNone]	full_word	auto[0]	72324395	1			T2	8182		T3	110914		T17	323379
auto[TlIntgErrNone]	full_word	auto[1]	115071227	1			T2	5583		T3	162874		T17	469463
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T128	1		T172	6		T153	2
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T111	7		T128	4		T129	6
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T111	1		T128	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T111	1		T129	1		T139	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T111	1		T128	2		T129	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T111	4		T128	1		T129	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T153	1		T175	1		T176	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T129	1		T175	1		T177	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T111	2		T129	5		T139	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T111	4		T128	1		T129	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T129	1		T174	1		T173	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T139	1		T175	1		-	-