Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	95457	0	0
entropy_period_rd_A	2147483647	1941	0	0
intr_enable_rd_A	2147483647	2844	0	0
prefix_0_rd_A	2147483647	2110	0	0
prefix_10_rd_A	2147483647	2154	0	0
prefix_1_rd_A	2147483647	2250	0	0
prefix_2_rd_A	2147483647	2260	0	0
prefix_3_rd_A	2147483647	2010	0	0
prefix_4_rd_A	2147483647	2113	0	0
prefix_5_rd_A	2147483647	1954	0	0
prefix_6_rd_A	2147483647	2060	0	0
prefix_7_rd_A	2147483647	1891	0	0
prefix_8_rd_A	2147483647	2015	0	0
prefix_9_rd_A	2147483647	2114	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	95457	0	0
T7	148886	15223	0	0
T8	149646	0	0	0
T9	207783	0	0	0
T18	418972	0	0	0
T38	663313	0	0	0
T39	150180	0	0	0
T40	223424	0	0	0
T41	191283	0	0	0
T42	12707	0	0	0
T47	1643	0	0	0
T68	0	76992	0	0
T111	0	4	0	0
T127	0	1	0	0
T128	0	2	0	0
T129	0	1	0	0
T130	0	149	0	0
T131	0	58	0	0
T139	0	1	0	0
T140	0	6	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1941	0	0
T98	1675	2	0	0
T106	3244	14	0	0
T111	23042	105	0	0
T127	9048	26	0	0
T128	11786	61	0	0
T140	9280	19	0	0
T150	3513	8	0	0
T151	9420	17	0	0
T152	6024	25	0	0
T153	23143	120	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2844	0	0
T106	3244	1	0	0
T111	23042	171	0	0
T127	9048	28	0	0
T128	11786	69	0	0
T133	2068	17	0	0
T140	9280	8	0	0
T150	3513	9	0	0
T151	9420	36	0	0
T154	1185	11	0	0
T155	1117	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2110	0	0
T98	1675	2	0	0
T106	3244	14	0	0
T111	23042	116	0	0
T127	9048	20	0	0
T128	11786	54	0	0
T140	9280	15	0	0
T150	3513	13	0	0
T151	9420	40	0	0
T152	6024	48	0	0
T153	23143	66	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2154	0	0
T98	1675	3	0	0
T106	3244	13	0	0
T111	23042	80	0	0
T127	9048	14	0	0
T128	11786	28	0	0
T140	9280	3	0	0
T151	9420	13	0	0
T152	6024	17	0	0
T153	23143	92	0	0
T156	10386	26	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2250	0	0
T98	1675	9	0	0
T106	3244	2	0	0
T111	23042	97	0	0
T127	9048	16	0	0
T128	11786	47	0	0
T140	9280	15	0	0
T150	3513	8	0	0
T151	9420	33	0	0
T152	6024	27	0	0
T153	23143	79	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2260	0	0
T106	3244	11	0	0
T111	23042	95	0	0
T127	9048	23	0	0
T128	11786	28	0	0
T140	9280	19	0	0
T150	3513	19	0	0
T151	9420	45	0	0
T152	6024	32	0	0
T153	23143	83	0	0
T156	10386	64	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2010	0	0
T106	3244	14	0	0
T111	23042	73	0	0
T127	9048	16	0	0
T128	11786	41	0	0
T140	9280	18	0	0
T150	3513	4	0	0
T151	9420	17	0	0
T152	6024	8	0	0
T153	23143	64	0	0
T156	10386	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2113	0	0
T98	1675	3	0	0
T106	3244	11	0	0
T111	23042	92	0	0
T127	9048	17	0	0
T128	11786	33	0	0
T140	9280	12	0	0
T151	9420	24	0	0
T152	6024	35	0	0
T153	23143	81	0	0
T156	10386	27	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1954	0	0
T106	3244	10	0	0
T111	23042	76	0	0
T127	9048	12	0	0
T128	11786	17	0	0
T140	9280	18	0	0
T150	3513	8	0	0
T151	9420	37	0	0
T152	6024	22	0	0
T153	23143	75	0	0
T156	10386	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2060	0	0
T106	3244	16	0	0
T111	23042	61	0	0
T127	9048	20	0	0
T128	11786	46	0	0
T140	9280	17	0	0
T151	9420	25	0	0
T152	6024	11	0	0
T153	23143	68	0	0
T156	10386	24	0	0
T157	13667	18	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1891	0	0
T106	3244	23	0	0
T111	23042	47	0	0
T127	9048	9	0	0
T128	11786	23	0	0
T140	9280	8	0	0
T150	3513	9	0	0
T151	9420	16	0	0
T152	6024	38	0	0
T153	23143	55	0	0
T156	10386	28	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2015	0	0
T98	1675	9	0	0
T106	3244	9	0	0
T111	23042	68	0	0
T127	9048	7	0	0
T128	11786	35	0	0
T140	9280	19	0	0
T150	3513	3	0	0
T151	9420	30	0	0
T152	6024	10	0	0
T153	23143	77	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2114	0	0
T98	1675	8	0	0
T106	3244	16	0	0
T111	23042	82	0	0
T127	9048	15	0	0
T128	11786	40	0	0
T140	9280	13	0	0
T150	3513	8	0	0
T151	9420	26	0	0
T152	6024	15	0	0
T153	23143	82	0	0