Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	259454311	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

184533371

1

T1

2679

T2

342487

T3

290219

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	229839307	1			T1	2173		T2	454331		T3	255576
values[0x0]	102905628	1			T1	350		T2	216750		T3	92615
values[0x1]	111242747	1			T1	317		T2	235480		T3	96615

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201703611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

242284071

1

T1

2713

T2

466396

T3

326979

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1338501	1			T1	19		T2	3620		T3	1815
valid_sources[0x01]	3700111	1			T1	23		T2	3450		T3	1737
valid_sources[0x02]	3680062	1			T1	13		T2	3606		T3	1607
valid_sources[0x03]	1342720	1			T1	8		T2	3447		T3	1704
valid_sources[0x04]	2175494	1			T1	4		T2	3589		T3	1666
valid_sources[0x05]	1882680	1			T1	2		T2	3611		T3	1756
valid_sources[0x06]	1337460	1			T1	10		T2	3547		T3	1778
valid_sources[0x07]	1333218	1			T1	9		T2	3563		T3	1744
valid_sources[0x08]	2125386	1			T1	25		T2	3523		T3	1790
valid_sources[0x09]	1453948	1			T1	9		T2	3488		T3	1617
valid_sources[0x0a]	1334863	1			T1	9		T2	3558		T3	1941
valid_sources[0x0b]	3306261	1			T1	8		T2	3591		T3	1717
valid_sources[0x0c]	1336012	1			T1	9		T2	3441		T3	1717
valid_sources[0x0d]	1407532	1			T1	33		T2	3448		T3	1752
valid_sources[0x0e]	1340812	1			T1	6		T2	3431		T3	1692
valid_sources[0x0f]	1326412	1			T1	17		T2	3459		T3	1898
valid_sources[0x10]	5755646	1			T1	14		T2	3475		T3	1644
valid_sources[0x11]	1333995	1			T1	5		T2	3639		T3	1601
valid_sources[0x12]	1338513	1			T1	15		T2	3610		T3	1757
valid_sources[0x13]	1337293	1			T1	16		T2	3565		T3	1786
valid_sources[0x14]	1346014	1			T1	9		T2	3530		T3	1785
valid_sources[0x15]	1343505	1			T1	22		T2	3451		T3	1831
valid_sources[0x16]	2310239	1			T1	15		T2	3582		T3	1722
valid_sources[0x17]	2186582	1			T1	4		T2	3568		T3	1705
valid_sources[0x18]	2112407	1			T1	10		T2	3506		T3	1782
valid_sources[0x19]	1343163	1			T1	8		T2	3528		T3	1781
valid_sources[0x1a]	3293112	1			T1	13		T2	3625		T3	1690
valid_sources[0x1b]	1336419	1			T1	8		T2	3530		T3	1703
valid_sources[0x1c]	1336166	1			T1	10		T2	3597		T3	1629
valid_sources[0x1d]	2189515	1			T1	7		T2	3531		T3	1728
valid_sources[0x1e]	2247163	1			T1	19		T2	3635		T3	1762
valid_sources[0x1f]	1348211	1			T1	8		T2	3649		T3	1598
valid_sources[0x20]	2814055	1			T1	4		T2	3444		T3	1672
valid_sources[0x21]	1335613	1			T1	9		T2	3511		T3	1705
valid_sources[0x22]	1342687	1			T1	19		T2	3619		T3	1711
valid_sources[0x23]	2190611	1			T1	28		T2	3606		T3	1816
valid_sources[0x24]	1340838	1			T1	15		T2	3619		T3	1667
valid_sources[0x25]	2004195	1			T1	10		T2	3508		T3	1703
valid_sources[0x26]	1422798	1			T1	28		T2	3364		T3	1659
valid_sources[0x27]	1979789	1			T1	11		T2	3679		T3	1672
valid_sources[0x28]	1333712	1			T1	9		T2	3535		T3	1588
valid_sources[0x29]	3309059	1			T1	5		T2	3438		T3	1614
valid_sources[0x2a]	4242663	1			T1	14		T2	3601		T3	1698
valid_sources[0x2b]	3332674	1			T1	16		T2	3505		T3	1725
valid_sources[0x2c]	1463683	1			T1	15		T2	3602		T3	1818
valid_sources[0x2d]	2188323	1			T1	5		T2	3539		T3	1891
valid_sources[0x2e]	3680193	1			T1	14		T2	3393		T3	1703
valid_sources[0x2f]	1345886	1			T1	16		T2	3641		T3	1696
valid_sources[0x30]	1448018	1			T1	6		T2	3532		T3	1772
valid_sources[0x31]	1333865	1			T1	13		T2	3577		T3	1759
valid_sources[0x32]	1333914	1			T1	10		T2	3504		T3	1643
valid_sources[0x33]	1330411	1			T1	25		T2	3603		T3	1800
valid_sources[0x34]	1341134	1			T1	8		T2	3581		T3	1616
valid_sources[0x35]	1658270	1			T1	6		T2	3549		T3	1784
valid_sources[0x36]	1513981	1			T1	11		T2	3536		T3	1713
valid_sources[0x37]	1331741	1			T1	19		T2	3458		T3	1649
valid_sources[0x38]	1338321	1			T1	15		T2	3481		T3	1697
valid_sources[0x39]	1342043	1			T1	7		T2	3513		T3	1748
valid_sources[0x3a]	3306297	1			T1	6		T2	3506		T3	1793
valid_sources[0x3b]	1363443	1			T1	5		T2	3608		T3	1720
valid_sources[0x3c]	1429488	1			T1	17		T2	3664		T3	1680
valid_sources[0x3d]	3644369	1			T1	16		T2	3614		T3	1899
valid_sources[0x3e]	1341032	1			T1	7		T2	3664		T3	1856
valid_sources[0x3f]	2204031	1			T1	11		T2	3571		T3	1644
valid_sources[0x40]	1791960	1			T1	6		T2	3534		T3	1728
valid_sources[0x41]	1335107	1			T1	17		T2	3583		T3	1730
valid_sources[0x42]	1327306	1			T1	9		T2	3646		T3	1643
valid_sources[0x43]	1328661	1			T1	7		T2	3448		T3	1569
valid_sources[0x44]	1330910	1			T1	11		T2	3482		T3	1696
valid_sources[0x45]	1342212	1			T1	19		T2	3565		T3	1747
valid_sources[0x46]	1487233	1			T1	13		T2	3375		T3	1738
valid_sources[0x47]	1426242	1			T1	26		T2	3459		T3	1810
valid_sources[0x48]	3319731	1			T1	11		T2	3464		T3	1542
valid_sources[0x49]	1336728	1			T1	9		T2	3330		T3	1789
valid_sources[0x4a]	1337215	1			T1	14		T2	3579		T3	1725
valid_sources[0x4b]	1338586	1			T1	1		T2	3616		T3	1680
valid_sources[0x4c]	1331961	1			T1	7		T2	3629		T3	1689
valid_sources[0x4d]	1365100	1			T1	1		T2	3577		T3	1799
valid_sources[0x4e]	1328270	1			T1	6		T2	3600		T3	1817
valid_sources[0x4f]	1799114	1			T1	6		T2	3672		T3	1703
valid_sources[0x50]	1336815	1			T1	7		T2	3647		T3	1786
valid_sources[0x51]	1366666	1			T1	9		T2	3485		T3	1628
valid_sources[0x52]	3334995	1			T1	15		T2	3631		T3	1771
valid_sources[0x53]	1339838	1			T1	10		T2	3538		T3	1668
valid_sources[0x54]	1339551	1			T1	13		T2	3583		T3	1743
valid_sources[0x55]	2230647	1			T1	8		T2	3605		T3	1934
valid_sources[0x56]	1337677	1			T1	13		T2	3672		T3	1726
valid_sources[0x57]	1332575	1			T1	2		T2	3486		T3	1795
valid_sources[0x58]	1975302	1			T1	9		T2	3627		T3	1778
valid_sources[0x59]	1335495	1			T1	20		T2	3500		T3	1693
valid_sources[0x5a]	3665643	1			T1	11		T2	3562		T3	1635
valid_sources[0x5b]	1366919	1			T1	11		T2	3537		T3	1762
valid_sources[0x5c]	1331889	1			T1	5		T2	3437		T3	1797
valid_sources[0x5d]	1784464	1			T1	15		T2	3484		T3	1747
valid_sources[0x5e]	1332340	1			T1	6		T2	3524		T3	1818
valid_sources[0x5f]	1333952	1			T1	10		T2	3479		T3	1749
valid_sources[0x60]	2188066	1			T1	5		T2	3371		T3	1647
valid_sources[0x61]	1337966	1			T1	5		T2	3448		T3	1728
valid_sources[0x62]	1338443	1			T1	11		T2	3728		T3	1786
valid_sources[0x63]	1332786	1			T1	4		T2	3418		T3	1692
valid_sources[0x64]	1367607	1			T1	3		T2	3609		T3	1691
valid_sources[0x65]	1338819	1			T1	8		T2	3560		T3	1700
valid_sources[0x66]	1336379	1			T1	1		T2	3577		T3	1787
valid_sources[0x67]	3310625	1			T1	7		T2	3517		T3	1657
valid_sources[0x68]	1389717	1			T1	3		T2	3609		T3	1865
valid_sources[0x69]	1334701	1			T1	3		T2	3348		T3	1649
valid_sources[0x6a]	1335609	1			T1	20		T2	3566		T3	1923
valid_sources[0x6b]	1344585	1			T1	2		T2	3467		T3	1747
valid_sources[0x6c]	1334035	1			T1	20		T2	3415		T3	1669
valid_sources[0x6d]	1335559	1			T1	1		T2	3641		T3	1673
valid_sources[0x6e]	1491367	1			T1	12		T2	3657		T3	1724
valid_sources[0x6f]	1333438	1			T1	8		T2	3400		T3	1786
valid_sources[0x70]	1400578	1			T1	20		T2	3558		T3	1702
valid_sources[0x71]	1343468	1			T1	20		T2	3473		T3	1809
valid_sources[0x72]	1334153	1			T1	16		T2	3532		T3	1708
valid_sources[0x73]	2209658	1			T1	1		T2	3515		T3	1722
valid_sources[0x74]	1407965	1			T1	2		T2	3511		T3	1639
valid_sources[0x75]	3291252	1			T1	9		T2	3599		T3	1797
valid_sources[0x76]	1335178	1			T1	14		T2	3651		T3	1711
valid_sources[0x77]	1344094	1			T1	8		T2	3521		T3	1820
valid_sources[0x78]	1340705	1			T1	3		T2	3753		T3	1649
valid_sources[0x79]	1331939	1			T1	15		T2	3569		T3	1679
valid_sources[0x7a]	1332994	1			T1	3		T2	3574		T3	1726
valid_sources[0x7b]	1342360	1			T1	10		T2	3485		T3	1848
valid_sources[0x7c]	2283419	1			T1	6		T2	3509		T3	1753
valid_sources[0x7d]	1345226	1			T1	7		T2	3321		T3	1779
valid_sources[0x7e]	1801087	1			T1	11		T2	3558		T3	1826
valid_sources[0x7f]	1333699	1			T1	14		T2	3707		T3	1803
valid_sources[0x80]	1330598	1			T1	21		T2	3389		T3	1698

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71597214

1

T1

2096

T2

118245

T3

151430

values[0x0]

all_enables

biggest_size

60701482

1

T1

310

T2

121377

T3

71465

values[0x1]

all_enables

biggest_size

52234675

1

T1

273

T2

102865

T3

67324