Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

260573473

1

T1

161

T2

564074

T3

154587

full_word

184604320

1

T1

2679

T2

342487

T3

290219

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	445177483	1			T1	2840		T2	906561		T3	444806
auto[TlIntgErrCmd]	108	1			T128	1		T129	2		T130	5
auto[TlIntgErrData]	96	1			T128	4		T129	3		T130	7
auto[TlIntgErrBoth]	106	1			T128	5		T129	5		T130	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230058746

1

T1

2173

T2

454331

T3

255576

auto[1]

215119047

1

T1

667

T2

452230

T3

189230

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158443367	1			T1	77		T2	336086		T3	104146
auto[TlIntgErrNone]	partial	auto[1]	102129821	1			T1	84		T2	227988		T3	50441
auto[TlIntgErrNone]	full_word	auto[0]	71615230	1			T1	2096		T2	118245		T3	151430
auto[TlIntgErrNone]	full_word	auto[1]	112989065	1			T1	583		T2	224242		T3	138789
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T129	2		T130	3		T181	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T128	1		T130	1		T181	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T185	1		T183	1		T187	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T130	1		T182	1		T185	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T128	2		T129	1		T130	4
auto[TlIntgErrData]	partial	auto[1]	38	1			T128	2		T129	2		T130	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T188	1		T185	1		T184	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T185	1		T189	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T128	2		T129	3		T130	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T128	3		T129	2		T130	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T184	1		T190	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T186	1		T188	1		T185	2