Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.48	98.75	96.74	100.00	92.31	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	263470	0	0
entropy_period_rd_A	2147483647	2291	0	0
intr_enable_rd_A	2147483647	3628	0	0
prefix_0_rd_A	2147483647	2304	0	0
prefix_10_rd_A	2147483647	2218	0	0
prefix_1_rd_A	2147483647	2290	0	0
prefix_2_rd_A	2147483647	2327	0	0
prefix_3_rd_A	2147483647	2379	0	0
prefix_4_rd_A	2147483647	2182	0	0
prefix_5_rd_A	2147483647	2201	0	0
prefix_6_rd_A	2147483647	2329	0	0
prefix_7_rd_A	2147483647	2392	0	0
prefix_8_rd_A	2147483647	2335	0	0
prefix_9_rd_A	2147483647	2445	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	263470	0	0
T25	381582	37749	0	0
T28	29931	0	0	0
T44	0	33627	0	0
T45	0	66710	0	0
T46	0	29644	0	0
T84	0	36047	0	0
T129	0	1	0	0
T130	0	5	0	0
T134	0	56398	0	0
T136	0	135	0	0
T137	0	187	0	0
T138	273642	0	0	0
T139	1402	0	0	0
T140	2065	0	0	0
T141	342365	0	0	0
T142	483217	0	0	0
T143	2956	0	0	0
T144	144155	0	0	0
T145	150636	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2291	0	0
T44	392162	86	0	0
T46	0	76	0	0
T77	146528	0	0	0
T84	0	99	0	0
T99	0	17	0	0
T129	0	56	0	0
T130	0	116	0	0
T134	0	143	0	0
T159	0	124	0	0
T160	0	29	0	0
T161	0	92	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3628	0	0
T44	392162	34	0	0
T46	0	79	0	0
T77	146528	0	0	0
T84	0	167	0	0
T99	0	17	0	0
T129	0	95	0	0
T132	0	19	0	0
T133	0	18	0	0
T134	0	87	0	0
T159	0	251	0	0
T160	0	6	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2304	0	0
T44	392162	87	0	0
T46	0	87	0	0
T77	146528	0	0	0
T84	0	84	0	0
T99	0	6	0	0
T129	0	45	0	0
T130	0	78	0	0
T134	0	125	0	0
T159	0	231	0	0
T160	0	6	0	0
T161	0	130	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2218	0	0
T44	392162	91	0	0
T46	0	63	0	0
T77	146528	0	0	0
T84	0	98	0	0
T99	0	16	0	0
T129	0	36	0	0
T130	0	83	0	0
T134	0	129	0	0
T159	0	258	0	0
T160	0	3	0	0
T161	0	93	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2290	0	0
T44	392162	63	0	0
T46	0	82	0	0
T77	146528	0	0	0
T84	0	143	0	0
T99	0	13	0	0
T102	0	1	0	0
T129	0	28	0	0
T130	0	84	0	0
T134	0	170	0	0
T159	0	217	0	0
T161	0	133	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2327	0	0
T44	392162	87	0	0
T46	0	76	0	0
T77	146528	0	0	0
T84	0	116	0	0
T99	0	20	0	0
T129	0	40	0	0
T130	0	83	0	0
T134	0	177	0	0
T159	0	227	0	0
T160	0	5	0	0
T161	0	83	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2379	0	0
T44	392162	93	0	0
T46	0	59	0	0
T77	146528	0	0	0
T84	0	120	0	0
T99	0	25	0	0
T129	0	45	0	0
T130	0	76	0	0
T134	0	176	0	0
T136	0	6	0	0
T159	0	225	0	0
T160	0	26	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2182	0	0
T44	392162	94	0	0
T46	0	69	0	0
T77	146528	0	0	0
T84	0	70	0	0
T99	0	11	0	0
T129	0	30	0	0
T130	0	93	0	0
T134	0	123	0	0
T159	0	201	0	0
T160	0	1	0	0
T161	0	89	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2201	0	0
T44	392162	92	0	0
T46	0	73	0	0
T77	146528	0	0	0
T84	0	106	0	0
T99	0	8	0	0
T129	0	32	0	0
T130	0	61	0	0
T134	0	122	0	0
T159	0	182	0	0
T160	0	18	0	0
T161	0	113	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2329	0	0
T44	392162	70	0	0
T46	0	97	0	0
T77	146528	0	0	0
T84	0	102	0	0
T99	0	5	0	0
T129	0	33	0	0
T130	0	66	0	0
T134	0	151	0	0
T159	0	251	0	0
T160	0	5	0	0
T161	0	93	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2392	0	0
T44	392162	84	0	0
T46	0	73	0	0
T77	146528	0	0	0
T84	0	123	0	0
T99	0	18	0	0
T129	0	58	0	0
T130	0	89	0	0
T134	0	130	0	0
T159	0	259	0	0
T160	0	7	0	0
T161	0	112	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2335	0	0
T44	392162	69	0	0
T46	0	75	0	0
T77	146528	0	0	0
T84	0	79	0	0
T99	0	19	0	0
T129	0	48	0	0
T130	0	80	0	0
T134	0	156	0	0
T159	0	253	0	0
T160	0	7	0	0
T161	0	110	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2445	0	0
T44	392162	157	0	0
T46	0	77	0	0
T77	146528	0	0	0
T84	0	145	0	0
T99	0	14	0	0
T129	0	40	0	0
T130	0	75	0	0
T134	0	129	0	0
T159	0	221	0	0
T160	0	6	0	0
T161	0	165	0	0
T162	987600	0	0	0
T163	9812	0	0	0
T164	972	0	0	0
T165	3905	0	0	0
T166	2112	0	0	0
T167	969710	0	0	0
T168	329842	0	0	0
T169	23976	0	0	0