Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258311878

1

T1

143914

T2

551251

T3

777

full_word

181490292

1

T1

927719

T2

342786

T3

1111

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	439801840	1			T1	236686		T2	894037		T3	1888
auto[TlIntgErrCmd]	101	1			T151	2		T153	2		T154	2
auto[TlIntgErrData]	119	1			T151	3		T153	6		T154	5
auto[TlIntgErrBoth]	110	1			T151	5		T153	2		T154	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228316337

1

T1

119357

T2

448057

T3

829

auto[1]

211485833

1

T1

117328

T2

445980

T3

1059

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157777545	1			T1	854006		T2	331448		T3	486
auto[TlIntgErrNone]	partial	auto[1]	100534032	1			T1	585141		T2	219803		T3	291
auto[TlIntgErrNone]	full_word	auto[0]	70538637	1			T1	339573		T2	116609		T3	343
auto[TlIntgErrNone]	full_word	auto[1]	110951626	1			T1	588146		T2	226177		T3	768
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T154	1		T210	4		T189	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T151	2		T153	2		T154	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T210	1		T211	1		T159	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T213	1		T214	1		T215	2
auto[TlIntgErrData]	partial	auto[0]	60	1			T153	4		T154	2		T210	4
auto[TlIntgErrData]	partial	auto[1]	46	1			T151	3		T154	2		T210	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T153	1		T154	1		T197	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T153	1		T210	1		T211	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T151	2		T210	1		T189	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T151	2		T153	2		T154	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T151	1		T216	1		T215	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T197	1		T158	1		T215	2