Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	10669	0	0
entropy_period_rd_A	2147483647	1589	0	0
intr_enable_rd_A	2147483647	2318	0	0
prefix_0_rd_A	2147483647	1399	0	0
prefix_10_rd_A	2147483647	1418	0	0
prefix_1_rd_A	2147483647	1579	0	0
prefix_2_rd_A	2147483647	1610	0	0
prefix_3_rd_A	2147483647	1560	0	0
prefix_4_rd_A	2147483647	1428	0	0
prefix_5_rd_A	2147483647	1557	0	0
prefix_6_rd_A	2147483647	1641	0	0
prefix_7_rd_A	2147483647	1566	0	0
prefix_8_rd_A	2147483647	1547	0	0
prefix_9_rd_A	2147483647	1409	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10669	0	0
T76	351458	7070	0	0
T136	0	223	0	0
T137	0	12	0	0
T151	0	1	0	0
T152	0	308	0	0
T153	0	2	0	0
T162	0	2	0	0
T164	0	3	0	0
T165	0	3	0	0
T166	0	5	0	0
T168	974315	0	0	0
T169	115959	0	0	0
T170	4134	0	0	0
T171	496200	0	0	0
T172	2677	0	0	0
T173	59976	0	0	0
T174	10508	0	0	0
T175	13351	0	0	0
T176	308004	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1589	0	0
T101	3218	1	0	0
T111	2433	5	0	0
T153	12980	43	0	0
T164	3895	7	0	0
T165	5679	22	0	0
T188	4737	7	0	0
T189	12899	87	0	0
T190	30700	121	0	0
T191	4877	24	0	0
T192	11210	32	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2318	0	0
T101	3218	15	0	0
T153	12980	88	0	0
T164	3895	2	0	0
T165	5679	18	0	0
T188	4737	4	0	0
T189	12899	81	0	0
T193	1536	15	0	0
T194	1160	18	0	0
T195	1082	6	0	0
T196	967	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1399	0	0
T101	3218	12	0	0
T153	12980	30	0	0
T165	5679	11	0	0
T188	4737	11	0	0
T189	12899	50	0	0
T190	30700	67	0	0
T191	4877	13	0	0
T192	11210	45	0	0
T197	24451	82	0	0
T198	1713	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1418	0	0
T101	3218	8	0	0
T153	12980	43	0	0
T164	3895	15	0	0
T165	5679	2	0	0
T188	4737	6	0	0
T189	12899	28	0	0
T190	30700	67	0	0
T191	4877	6	0	0
T192	11210	37	0	0
T197	24451	89	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1579	0	0
T101	3218	6	0	0
T111	2433	6	0	0
T153	12980	47	0	0
T164	3895	10	0	0
T165	5679	9	0	0
T188	4737	7	0	0
T189	12899	56	0	0
T190	30700	96	0	0
T191	4877	8	0	0
T192	11210	38	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1610	0	0
T101	3218	21	0	0
T153	12980	40	0	0
T164	3895	13	0	0
T165	5679	8	0	0
T188	4737	6	0	0
T189	12899	46	0	0
T190	30700	76	0	0
T191	4877	15	0	0
T192	11210	34	0	0
T197	24451	90	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1560	0	0
T101	3218	12	0	0
T153	12980	36	0	0
T164	3895	10	0	0
T165	5679	6	0	0
T188	4737	11	0	0
T189	12899	37	0	0
T190	30700	77	0	0
T191	4877	8	0	0
T192	11210	38	0	0
T197	24451	73	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1428	0	0
T101	3218	16	0	0
T111	2433	4	0	0
T153	12980	47	0	0
T164	3895	3	0	0
T165	5679	12	0	0
T188	4737	4	0	0
T189	12899	39	0	0
T190	30700	54	0	0
T191	4877	9	0	0
T192	11210	51	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1557	0	0
T101	3218	16	0	0
T111	2433	4	0	0
T153	12980	37	0	0
T164	3895	5	0	0
T165	5679	6	0	0
T188	4737	7	0	0
T189	12899	48	0	0
T190	30700	87	0	0
T191	4877	11	0	0
T192	11210	99	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1641	0	0
T101	3218	7	0	0
T111	2433	4	0	0
T153	12980	43	0	0
T164	3895	12	0	0
T165	5679	9	0	0
T188	4737	5	0	0
T189	12899	52	0	0
T190	30700	55	0	0
T191	4877	15	0	0
T192	11210	49	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1566	0	0
T101	3218	3	0	0
T111	2433	2	0	0
T153	12980	38	0	0
T164	3895	13	0	0
T165	5679	4	0	0
T188	4737	8	0	0
T189	12899	39	0	0
T190	30700	72	0	0
T191	4877	23	0	0
T192	11210	83	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1547	0	0
T101	3218	6	0	0
T153	12980	37	0	0
T164	3895	12	0	0
T165	5679	6	0	0
T188	4737	9	0	0
T189	12899	37	0	0
T190	30700	80	0	0
T191	4877	15	0	0
T192	11210	17	0	0
T197	24451	85	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1409	0	0
T101	3218	11	0	0
T153	12980	38	0	0
T164	3895	10	0	0
T165	5679	2	0	0
T188	4737	9	0	0
T189	12899	42	0	0
T190	30700	90	0	0
T191	4877	13	0	0
T192	11210	62	0	0
T197	24451	48	0	0