Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
144493 |
1 |
|
|
T7 |
272 |
|
T8 |
1572 |
|
T17 |
211 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
75087 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
51182 |
1 |
|
|
T7 |
8 |
|
T8 |
41 |
|
T17 |
206 |
seven_bytes |
2657 |
1 |
|
|
T7 |
12 |
|
T8 |
43 |
|
T36 |
28 |
six_bytes |
2596 |
1 |
|
|
T7 |
5 |
|
T8 |
34 |
|
T36 |
25 |
five_bytes |
2582 |
1 |
|
|
T7 |
5 |
|
T8 |
32 |
|
T36 |
16 |
four_bytes |
2630 |
1 |
|
|
T7 |
10 |
|
T8 |
51 |
|
T36 |
23 |
three_bytes |
2625 |
1 |
|
|
T7 |
11 |
|
T8 |
52 |
|
T36 |
12 |
two_bytes |
2514 |
1 |
|
|
T7 |
8 |
|
T8 |
34 |
|
T36 |
31 |
one_byte |
2620 |
1 |
|
|
T7 |
6 |
|
T8 |
44 |
|
T36 |
27 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
141730 |
1 |
|
|
T7 |
268 |
|
T8 |
1550 |
|
T17 |
201 |
auto[1] |
2763 |
1 |
|
|
T7 |
4 |
|
T8 |
22 |
|
T17 |
10 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
144493 |
1 |
|
|
T7 |
272 |
|
T8 |
1572 |
|
T17 |
211 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
144477 |
1 |
|
|
T7 |
272 |
|
T8 |
1572 |
|
T17 |
211 |
auto[1] |
16 |
1 |
|
|
T50 |
1 |
|
T176 |
1 |
|
T177 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
976 |
1 |
|
|
T7 |
1 |
|
T8 |
3 |
|
T17 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2763 |
1 |
|
|
T7 |
4 |
|
T8 |
22 |
|
T17 |
10 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
140963 |
1 |
|
|
T8 |
544 |
|
T36 |
525 |
|
T18 |
739 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
74217 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
49005 |
1 |
|
|
T8 |
16 |
|
T36 |
22 |
|
T18 |
12 |
seven_bytes |
2507 |
1 |
|
|
T8 |
12 |
|
T36 |
12 |
|
T18 |
27 |
six_bytes |
2509 |
1 |
|
|
T8 |
9 |
|
T36 |
9 |
|
T18 |
21 |
five_bytes |
2669 |
1 |
|
|
T8 |
17 |
|
T36 |
12 |
|
T18 |
33 |
four_bytes |
2581 |
1 |
|
|
T8 |
15 |
|
T36 |
12 |
|
T18 |
18 |
three_bytes |
2466 |
1 |
|
|
T8 |
10 |
|
T36 |
10 |
|
T18 |
16 |
two_bytes |
2508 |
1 |
|
|
T8 |
17 |
|
T36 |
25 |
|
T18 |
31 |
one_byte |
2501 |
1 |
|
|
T8 |
12 |
|
T36 |
14 |
|
T18 |
21 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
138301 |
1 |
|
|
T8 |
536 |
|
T36 |
517 |
|
T18 |
733 |
auto[1] |
2662 |
1 |
|
|
T8 |
8 |
|
T36 |
8 |
|
T18 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
140963 |
1 |
|
|
T8 |
544 |
|
T36 |
525 |
|
T18 |
739 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
140953 |
1 |
|
|
T8 |
544 |
|
T36 |
525 |
|
T18 |
739 |
auto[1] |
10 |
1 |
|
|
T37 |
1 |
|
T178 |
1 |
|
T179 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
916 |
1 |
|
|
T8 |
1 |
|
T18 |
1 |
|
T15 |
11 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2662 |
1 |
|
|
T8 |
8 |
|
T36 |
8 |
|
T18 |
6 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
279279 |
1 |
|
|
T3 |
261 |
|
T7 |
690 |
|
T8 |
2012 |
auto[1] |
375 |
1 |
|
|
T9 |
44 |
|
T10 |
36 |
|
T11 |
61 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
149835 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
94128 |
1 |
|
|
T3 |
257 |
|
T7 |
33 |
|
T8 |
60 |
seven_bytes |
5170 |
1 |
|
|
T7 |
16 |
|
T8 |
55 |
|
T36 |
93 |
six_bytes |
5105 |
1 |
|
|
T7 |
16 |
|
T8 |
55 |
|
T36 |
85 |
five_bytes |
5238 |
1 |
|
|
T7 |
25 |
|
T8 |
54 |
|
T36 |
77 |
four_bytes |
5094 |
1 |
|
|
T7 |
13 |
|
T8 |
59 |
|
T36 |
91 |
three_bytes |
5005 |
1 |
|
|
T7 |
23 |
|
T8 |
61 |
|
T36 |
88 |
two_bytes |
5043 |
1 |
|
|
T7 |
23 |
|
T8 |
54 |
|
T36 |
95 |
one_byte |
5036 |
1 |
|
|
T7 |
16 |
|
T8 |
54 |
|
T36 |
78 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
274328 |
1 |
|
|
T3 |
253 |
|
T7 |
680 |
|
T8 |
1986 |
auto[1] |
5326 |
1 |
|
|
T3 |
8 |
|
T7 |
10 |
|
T8 |
26 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
279654 |
1 |
|
|
T3 |
261 |
|
T7 |
690 |
|
T8 |
2012 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
279636 |
1 |
|
|
T3 |
261 |
|
T7 |
689 |
|
T8 |
2012 |
auto[1] |
18 |
1 |
|
|
T7 |
1 |
|
T15 |
1 |
|
T89 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1814 |
1 |
|
|
T3 |
4 |
|
T7 |
2 |
|
T8 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
5326 |
1 |
|
|
T3 |
8 |
|
T7 |
10 |
|
T8 |
26 |