Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257041285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

181913026

1

T1

890

T2

324847

T3

16626

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	227133168	1			T1	651		T2	417695		T3	23063
values[0x0]	101805145	1			T1	222		T2	200306		T3	4552
values[0x1]	110015998	1			T1	218		T2	214638		T3	4994

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199824058	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

239130253

1

T1

945

T2

434486

T3

20780

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2542521	1			T1	1		T2	3328		T3	6
valid_sources[0x01]	3228089	1			T1	7		T2	3224		T3	9
valid_sources[0x02]	1253033	1			T1	3		T2	3232		T3	5
valid_sources[0x03]	1256834	1			T2	3233		T3	5		T30	1317
valid_sources[0x04]	2176237	1			T1	6		T2	3254		T3	4
valid_sources[0x05]	1255668	1			T1	6		T2	3288		T3	4
valid_sources[0x06]	4034554	1			T1	5		T2	3203		T3	2
valid_sources[0x07]	1469208	1			T1	4		T2	3258		T3	5
valid_sources[0x08]	1251698	1			T1	1		T2	3144		T3	6
valid_sources[0x09]	2146991	1			T1	4		T2	3207		T3	9
valid_sources[0x0a]	3659353	1			T1	3		T2	3203		T3	4
valid_sources[0x0b]	1914738	1			T1	8		T2	3301		T3	7
valid_sources[0x0c]	1306054	1			T1	3		T2	3238		T3	10
valid_sources[0x0d]	1255001	1			T1	4		T2	3208		T3	4
valid_sources[0x0e]	2157017	1			T1	3		T2	3265		T3	4
valid_sources[0x0f]	3230898	1			T1	4		T2	3317		T3	1
valid_sources[0x10]	1249338	1			T1	7		T2	3200		T3	6
valid_sources[0x11]	1254627	1			T1	1		T2	3315		T3	7
valid_sources[0x12]	1883319	1			T1	3		T2	3323		T3	8
valid_sources[0x13]	1258097	1			T1	11		T2	3309		T3	5
valid_sources[0x14]	1255213	1			T1	9		T2	3204		T3	9
valid_sources[0x15]	1259337	1			T1	4		T2	3163		T3	7
valid_sources[0x16]	1282023	1			T1	3		T2	3286		T3	7
valid_sources[0x17]	1255873	1			T1	4		T2	3186		T3	12
valid_sources[0x18]	1250099	1			T1	4		T2	3224		T3	9
valid_sources[0x19]	1337373	1			T1	3		T2	3223		T3	6
valid_sources[0x1a]	3543082	1			T2	3188		T3	7		T30	1426
valid_sources[0x1b]	1506226	1			T1	1		T2	3269		T3	8
valid_sources[0x1c]	2158024	1			T1	5		T2	3267		T3	10
valid_sources[0x1d]	3574261	1			T1	8		T2	3294		T3	12
valid_sources[0x1e]	1921148	1			T1	10		T2	3256		T3	10
valid_sources[0x1f]	1251386	1			T1	2		T2	3213		T3	9
valid_sources[0x20]	1248825	1			T1	5		T2	3228		T3	5
valid_sources[0x21]	1248618	1			T1	11		T2	3248		T3	8
valid_sources[0x22]	1265325	1			T1	4		T2	3246		T3	9
valid_sources[0x23]	1272908	1			T1	7		T2	3256		T3	7
valid_sources[0x24]	1255994	1			T1	2		T2	3257		T3	9
valid_sources[0x25]	1560999	1			T1	1		T2	3198		T3	4
valid_sources[0x26]	1269990	1			T1	3		T2	3186		T3	5
valid_sources[0x27]	1862344	1			T1	1		T2	3206		T3	7
valid_sources[0x28]	1257231	1			T1	8		T2	3402		T3	6
valid_sources[0x29]	1253521	1			T1	3		T2	3355		T3	8
valid_sources[0x2a]	1256554	1			T1	5		T2	3242		T3	6
valid_sources[0x2b]	3213473	1			T1	3		T2	3305		T3	6
valid_sources[0x2c]	1255362	1			T1	8		T2	3258		T3	8
valid_sources[0x2d]	1944974	1			T1	2		T2	3221		T3	5
valid_sources[0x2e]	2800669	1			T1	3		T2	3267		T3	7
valid_sources[0x2f]	1584943	1			T1	2		T2	3316		T3	11
valid_sources[0x30]	1254561	1			T1	2		T2	3216		T3	8
valid_sources[0x31]	1259991	1			T1	1		T2	3353		T3	8
valid_sources[0x32]	1455909	1			T1	7		T2	3228		T3	12
valid_sources[0x33]	3573797	1			T1	3		T2	3260		T3	6
valid_sources[0x34]	2217877	1			T1	8		T2	3240		T3	4
valid_sources[0x35]	2152883	1			T1	5		T2	3295		T3	9
valid_sources[0x36]	1245944	1			T1	8		T2	3225		T3	8
valid_sources[0x37]	1255746	1			T1	4		T2	3278		T3	10
valid_sources[0x38]	1271270	1			T1	10		T2	3238		T3	5
valid_sources[0x39]	1253305	1			T1	3		T2	3233		T3	9
valid_sources[0x3a]	2114429	1			T1	1		T2	3267		T3	5
valid_sources[0x3b]	1253482	1			T1	2		T2	3329		T3	7
valid_sources[0x3c]	4494732	1			T1	5		T2	3350		T3	6
valid_sources[0x3d]	1987531	1			T1	3		T2	3293		T3	5
valid_sources[0x3e]	1250965	1			T1	6		T2	3256		T3	5
valid_sources[0x3f]	1254495	1			T1	5		T2	3167		T3	6
valid_sources[0x40]	1763146	1			T1	10		T2	3251		T3	4
valid_sources[0x41]	1249481	1			T1	6		T2	3364		T3	5
valid_sources[0x42]	1265313	1			T1	5		T2	3250		T3	9
valid_sources[0x43]	1301845	1			T1	3		T2	3329		T3	8
valid_sources[0x44]	1661037	1			T1	7		T2	3263		T3	5
valid_sources[0x45]	1254799	1			T1	4		T2	3294		T3	8
valid_sources[0x46]	1253924	1			T1	6		T2	3184		T3	5
valid_sources[0x47]	1787584	1			T2	3264		T3	5		T30	1642
valid_sources[0x48]	1253417	1			T1	2		T2	3232		T3	8
valid_sources[0x49]	1254709	1			T1	3		T2	3223		T3	6
valid_sources[0x4a]	1258166	1			T1	7		T2	3288		T3	6
valid_sources[0x4b]	3243774	1			T1	9		T2	3177		T3	5
valid_sources[0x4c]	1539290	1			T1	3		T2	3278		T3	9
valid_sources[0x4d]	1249681	1			T1	1		T2	3281		T3	4
valid_sources[0x4e]	1381504	1			T1	6		T2	3257		T3	7
valid_sources[0x4f]	1316934	1			T1	3		T2	3414		T3	4
valid_sources[0x50]	3220932	1			T1	3		T2	3240		T3	6
valid_sources[0x51]	1251634	1			T1	7		T2	3289		T3	2
valid_sources[0x52]	1281293	1			T1	4		T2	3278		T3	5
valid_sources[0x53]	1286395	1			T1	3		T2	3269		T3	8
valid_sources[0x54]	1269438	1			T1	2		T2	3125		T3	11
valid_sources[0x55]	1250970	1			T1	8		T2	3298		T3	6
valid_sources[0x56]	1334107	1			T1	8		T2	3427		T3	3
valid_sources[0x57]	1253899	1			T1	4		T2	3182		T3	7
valid_sources[0x58]	2147700	1			T1	3		T2	3274		T3	9
valid_sources[0x59]	1255368	1			T1	3		T2	3246		T3	2
valid_sources[0x5a]	1254308	1			T1	10		T2	3200		T3	6
valid_sources[0x5b]	1265026	1			T1	4		T2	3117		T3	7
valid_sources[0x5c]	1331120	1			T1	7		T2	3300		T3	11
valid_sources[0x5d]	2030439	1			T1	6		T2	3306		T3	4
valid_sources[0x5e]	1285886	1			T1	3		T2	3299		T3	4
valid_sources[0x5f]	1252340	1			T2	3229		T3	8		T30	1384
valid_sources[0x60]	1253558	1			T1	4		T2	3221		T3	7
valid_sources[0x61]	1282324	1			T1	5		T2	3253		T3	6
valid_sources[0x62]	1262734	1			T1	3		T2	3314		T3	8
valid_sources[0x63]	1255523	1			T1	3		T2	3239		T3	6
valid_sources[0x64]	1424127	1			T1	5		T2	3335		T3	6
valid_sources[0x65]	2379927	1			T1	1		T2	3217		T3	3
valid_sources[0x66]	1254323	1			T1	1		T2	3191		T3	1
valid_sources[0x67]	1253368	1			T2	3106		T3	4		T30	1340
valid_sources[0x68]	1251522	1			T1	4		T2	3226		T3	6
valid_sources[0x69]	1362444	1			T1	2		T2	3338		T3	5
valid_sources[0x6a]	1248899	1			T1	14		T2	3320		T3	6
valid_sources[0x6b]	1402608	1			T1	1		T2	3303		T3	6
valid_sources[0x6c]	1259421	1			T1	5		T2	3297		T3	7
valid_sources[0x6d]	1249665	1			T2	3197		T3	7		T30	1415
valid_sources[0x6e]	1257030	1			T1	1		T2	3303		T3	5
valid_sources[0x6f]	1257501	1			T1	1		T2	3259		T3	4
valid_sources[0x70]	2150264	1			T1	1		T2	3307		T3	9
valid_sources[0x71]	4508634	1			T1	10		T2	3300		T3	7
valid_sources[0x72]	3020809	1			T1	5		T2	3280		T3	3
valid_sources[0x73]	2415341	1			T1	2		T2	3300		T3	2
valid_sources[0x74]	1252963	1			T1	9		T2	3226		T3	8
valid_sources[0x75]	5540711	1			T1	4		T2	3283		T3	7
valid_sources[0x76]	1255961	1			T1	4		T2	3125		T3	5
valid_sources[0x77]	1285574	1			T1	3		T2	3225		T3	30963
valid_sources[0x78]	2469461	1			T1	8		T2	3250		T3	3
valid_sources[0x79]	2157904	1			T1	13		T2	3257		T3	9
valid_sources[0x7a]	1257650	1			T1	2		T2	3168		T3	2
valid_sources[0x7b]	1259901	1			T1	3		T2	3238		T3	9
valid_sources[0x7c]	1258531	1			T1	7		T2	3230		T3	11
valid_sources[0x7d]	1254656	1			T1	6		T2	3236		T3	8
valid_sources[0x7e]	1297717	1			T1	4		T2	3208		T3	3
valid_sources[0x7f]	1274615	1			T1	16		T2	3313		T3	7
valid_sources[0x80]	1351370	1			T1	12		T2	3329		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

69865059

1

T1

534

T2

109605

T3

11516

values[0x0]

all_enables

biggest_size

60204293

1

T1

185

T2

116406

T3

2704

values[0x1]

all_enables

biggest_size

51843674

1

T1

171

T2

98836

T3

2406