Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257899925

1

T1

201

T2

507792

T3

15983

full_word

181967052

1

T1

890

T2

324847

T3

16626

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	439866697	1			T1	1091		T2	832639		T3	32609
auto[TlIntgErrCmd]	100	1			T106	10		T125	8		T126	4
auto[TlIntgErrData]	87	1			T106	5		T125	8		T126	2
auto[TlIntgErrBoth]	93	1			T106	5		T125	4		T126	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227302442

1

T1

651

T2

417695

T3

23063

auto[1]

212564535

1

T1

440

T2

414944

T3

9546

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157423473	1			T1	117		T2	308090		T3	11547
auto[TlIntgErrNone]	partial	auto[1]	100476206	1			T1	84		T2	199702		T3	4436
auto[TlIntgErrNone]	full_word	auto[0]	69878853	1			T1	534		T2	109605		T3	11516
auto[TlIntgErrNone]	full_word	auto[1]	112088165	1			T1	356		T2	215242		T3	5110
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T106	3		T125	5		T126	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T106	5		T125	2		T126	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T106	1		T184	1		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T106	1		T125	1		T181	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T125	4		T181	1		T186	1
auto[TlIntgErrData]	partial	auto[1]	40	1			T106	5		T125	2		T126	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T125	1		T186	1		T187	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T125	1		T186	1		T187	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1			T126	2		T181	1		T182	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T106	3		T125	4		T126	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T186	1		T184	1		T188	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T106	2		T182	1		T189	1