Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	197731	0	0
entropy_period_rd_A	2147483647	1596	0	0
intr_enable_rd_A	2147483647	2315	0	0
prefix_0_rd_A	2147483647	1496	0	0
prefix_10_rd_A	2147483647	1484	0	0
prefix_1_rd_A	2147483647	1616	0	0
prefix_2_rd_A	2147483647	1521	0	0
prefix_3_rd_A	2147483647	1547	0	0
prefix_4_rd_A	2147483647	1504	0	0
prefix_5_rd_A	2147483647	1542	0	0
prefix_6_rd_A	2147483647	1639	0	0
prefix_7_rd_A	2147483647	1551	0	0
prefix_8_rd_A	2147483647	1581	0	0
prefix_9_rd_A	2147483647	1565	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	197731	0	0
T23	701348	101207	0	0
T64	0	93566	0	0
T106	0	3	0	0
T123	0	14	0	0
T125	0	1	0	0
T127	0	9	0	0
T128	0	27	0	0
T134	0	8	0	0
T135	0	3	0	0
T140	0	2	0	0
T141	108646	0	0	0
T142	918744	0	0	0
T143	994643	0	0	0
T144	57706	0	0	0
T145	390365	0	0	0
T146	639592	0	0	0
T147	107181	0	0	0
T148	527090	0	0	0
T149	151266	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1596	0	0
T82	12134	115	0	0
T87	10633	32	0	0
T106	22801	111	0	0
T124	6843	29	0	0
T125	30695	129	0	0
T140	4508	10	0	0
T160	144426	257	0	0
T161	1976	5	0	0
T162	10890	42	0	0
T163	10155	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2315	0	0
T82	12134	96	0	0
T87	10633	32	0	0
T106	22801	177	0	0
T131	1180	10	0	0
T140	4508	9	0	0
T160	144426	447	0	0
T161	1976	8	0	0
T162	10890	16	0	0
T164	1606	19	0	0
T165	1180	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1496	0	0
T82	12134	57	0	0
T87	10633	45	0	0
T106	22801	84	0	0
T124	6843	28	0	0
T125	30695	91	0	0
T140	4508	10	0	0
T160	144426	401	0	0
T161	1976	6	0	0
T162	10890	52	0	0
T163	10155	46	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1484	0	0
T82	12134	54	0	0
T87	10633	34	0	0
T106	22801	78	0	0
T124	6843	27	0	0
T125	30695	58	0	0
T140	4508	6	0	0
T160	144426	468	0	0
T161	1976	5	0	0
T162	10890	24	0	0
T163	10155	20	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1616	0	0
T82	12134	70	0	0
T87	10633	40	0	0
T106	22801	64	0	0
T124	6843	27	0	0
T125	30695	79	0	0
T133	8253	2	0	0
T140	4508	15	0	0
T160	144426	443	0	0
T162	10890	71	0	0
T163	10155	25	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1521	0	0
T82	12134	57	0	0
T87	10633	39	0	0
T106	22801	85	0	0
T124	6843	13	0	0
T125	30695	81	0	0
T140	4508	6	0	0
T160	144426	447	0	0
T161	1976	3	0	0
T162	10890	20	0	0
T163	10155	26	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1547	0	0
T82	12134	49	0	0
T87	10633	31	0	0
T106	22801	76	0	0
T124	6843	33	0	0
T125	30695	90	0	0
T140	4508	6	0	0
T160	144426	440	0	0
T161	1976	8	0	0
T162	10890	90	0	0
T163	10155	53	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1504	0	0
T82	12134	68	0	0
T87	10633	36	0	0
T106	22801	90	0	0
T124	6843	18	0	0
T125	30695	76	0	0
T140	4508	12	0	0
T160	144426	434	0	0
T161	1976	7	0	0
T162	10890	37	0	0
T163	10155	34	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1542	0	0
T82	12134	58	0	0
T87	10633	33	0	0
T106	22801	67	0	0
T124	6843	30	0	0
T125	30695	77	0	0
T140	4508	12	0	0
T160	144426	478	0	0
T161	1976	4	0	0
T162	10890	30	0	0
T163	10155	27	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1639	0	0
T82	12134	59	0	0
T87	10633	21	0	0
T106	22801	79	0	0
T124	6843	30	0	0
T125	30695	55	0	0
T140	4508	7	0	0
T160	144426	441	0	0
T162	10890	100	0	0
T163	10155	10	0	0
T166	9929	47	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1551	0	0
T82	12134	64	0	0
T87	10633	41	0	0
T106	22801	87	0	0
T124	6843	21	0	0
T125	30695	95	0	0
T140	4508	7	0	0
T160	144426	475	0	0
T161	1976	3	0	0
T162	10890	17	0	0
T163	10155	4	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1581	0	0
T82	12134	47	0	0
T87	10633	33	0	0
T106	22801	92	0	0
T124	6843	7	0	0
T125	30695	66	0	0
T140	4508	7	0	0
T160	144426	457	0	0
T161	1976	1	0	0
T162	10890	63	0	0
T163	10155	28	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T82	12134	74	0	0
T87	10633	23	0	0
T106	22801	69	0	0
T124	6843	33	0	0
T125	30695	85	0	0
T140	4508	8	0	0
T160	144426	462	0	0
T161	1976	3	0	0
T162	10890	58	0	0
T163	10155	31	0	0