Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	255568755	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

181463514

1

T1

911800

T2

166

T3

40002

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	226382734	1			T1	117692		T2	74		T3	21061
values[0x0]	101227705	1			T1	549142		T2	56		T3	10815
values[0x1]	109421830	1			T1	593569		T2	56		T3	11662

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	198763614	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

238268655

1

T1

122056

T2

171

T3

41402

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1345584	1			T3	182		T4	1		T16	160
valid_sources[0x01]	1381516	1			T2	1		T3	122		T4	3
valid_sources[0x02]	1620130	1			T3	155		T4	8		T16	92
valid_sources[0x03]	1352978	1			T3	213		T4	2		T16	33
valid_sources[0x04]	1363463	1			T3	209		T4	6		T16	110
valid_sources[0x05]	1447977	1			T2	7		T3	140		T4	2
valid_sources[0x06]	1504768	1			T3	249		T4	6		T16	76
valid_sources[0x07]	1352975	1			T3	151		T4	4		T16	51
valid_sources[0x08]	1376828	1			T3	146		T4	6		T16	78
valid_sources[0x09]	1356925	1			T2	1		T3	192		T4	6
valid_sources[0x0a]	1352009	1			T3	172		T4	10		T16	91
valid_sources[0x0b]	2321288	1			T2	8		T3	158		T4	5
valid_sources[0x0c]	1345267	1			T3	128		T4	7		T16	108
valid_sources[0x0d]	1351482	1			T3	163		T4	1		T16	161
valid_sources[0x0e]	3312694	1			T2	1		T3	157		T4	11
valid_sources[0x0f]	2845201	1			T3	167		T4	6		T16	150
valid_sources[0x10]	1351847	1			T3	249		T4	4		T16	89
valid_sources[0x11]	1572485	1			T3	172		T4	5		T16	104
valid_sources[0x12]	1904805	1			T2	1		T3	153		T4	2
valid_sources[0x13]	4137958	1			T3	181		T4	8		T16	79
valid_sources[0x14]	1478381	1			T3	130		T4	2		T16	96
valid_sources[0x15]	1353329	1			T3	189		T4	1		T16	75
valid_sources[0x16]	3306681	1			T3	147		T4	6		T16	106
valid_sources[0x17]	1350477	1			T3	174		T4	7		T16	120
valid_sources[0x18]	1350703	1			T3	119		T4	7		T16	113
valid_sources[0x19]	4031172	1			T3	248		T4	1		T16	125
valid_sources[0x1a]	1350988	1			T3	173		T4	1		T16	52
valid_sources[0x1b]	2009601	1			T3	190		T4	9		T16	51
valid_sources[0x1c]	3343788	1			T3	169		T4	1		T16	103
valid_sources[0x1d]	2391377	1			T3	129		T4	1		T16	181
valid_sources[0x1e]	1440162	1			T2	5		T3	144		T4	2
valid_sources[0x1f]	1689546	1			T3	167		T4	5		T16	63
valid_sources[0x20]	1356358	1			T3	126		T4	5		T16	176
valid_sources[0x21]	1360459	1			T3	198		T4	2		T16	17
valid_sources[0x22]	1348247	1			T3	206		T4	6		T16	168
valid_sources[0x23]	1470597	1			T2	2		T3	98		T4	8
valid_sources[0x24]	1808228	1			T3	111		T4	2		T16	100
valid_sources[0x25]	1404935	1			T2	6		T3	162		T4	8
valid_sources[0x26]	1356167	1			T3	123		T4	5		T16	105
valid_sources[0x27]	1791737	1			T2	3		T3	138		T4	1
valid_sources[0x28]	1504964	1			T3	174		T4	1		T16	122
valid_sources[0x29]	1363355	1			T3	138		T4	7		T16	70
valid_sources[0x2a]	1353778	1			T3	202		T4	1		T16	211
valid_sources[0x2b]	1384466	1			T2	3		T3	185		T4	5
valid_sources[0x2c]	1348807	1			T3	74		T4	2		T16	107
valid_sources[0x2d]	1353739	1			T3	184		T4	1		T16	87
valid_sources[0x2e]	1358385	1			T2	2		T3	105		T4	3
valid_sources[0x2f]	1396888	1			T2	5		T3	156		T4	8
valid_sources[0x30]	1358830	1			T3	206		T4	3		T16	40
valid_sources[0x31]	1352955	1			T2	1		T3	215		T4	3
valid_sources[0x32]	1349123	1			T2	1		T3	142		T4	6
valid_sources[0x33]	1354656	1			T3	230		T4	5		T16	27
valid_sources[0x34]	1351777	1			T3	112		T4	6		T16	117
valid_sources[0x35]	1372769	1			T3	119		T4	2		T16	36
valid_sources[0x36]	2192519	1			T3	231		T4	7		T16	72
valid_sources[0x37]	1355385	1			T3	98		T4	1		T16	109
valid_sources[0x38]	3697784	1			T3	216		T4	3		T16	118
valid_sources[0x39]	1352058	1			T3	186		T4	3		T16	124
valid_sources[0x3a]	1362611	1			T3	188		T4	1		T16	85
valid_sources[0x3b]	2000378	1			T3	183		T4	4		T16	113
valid_sources[0x3c]	3338145	1			T3	211		T4	8		T16	168
valid_sources[0x3d]	1358588	1			T3	225		T4	3		T16	74
valid_sources[0x3e]	1808916	1			T2	4		T3	67		T4	6
valid_sources[0x3f]	1346185	1			T2	1		T3	152		T4	1
valid_sources[0x40]	1345070	1			T3	147		T4	4		T16	156
valid_sources[0x41]	1340144	1			T3	220		T4	4		T16	69
valid_sources[0x42]	2001371	1			T3	122		T4	3		T16	176
valid_sources[0x43]	1439197	1			T3	152		T4	4		T16	167
valid_sources[0x44]	1792713	1			T3	182		T4	5		T16	132
valid_sources[0x45]	1350639	1			T3	222		T4	2		T16	42
valid_sources[0x46]	1807136	1			T3	157		T4	1		T16	32
valid_sources[0x47]	1346104	1			T3	152		T4	8		T16	117
valid_sources[0x48]	1353446	1			T3	231		T4	3		T16	82
valid_sources[0x49]	1499483	1			T2	1		T3	228		T4	3
valid_sources[0x4a]	1357848	1			T3	199		T4	9		T16	48
valid_sources[0x4b]	1408515	1			T3	237		T4	5		T16	162
valid_sources[0x4c]	1349428	1			T3	238		T4	5		T16	70
valid_sources[0x4d]	1348744	1			T3	236		T4	2		T16	139
valid_sources[0x4e]	1453538	1			T2	1		T3	119		T4	4
valid_sources[0x4f]	1354630	1			T3	151		T4	4		T16	197
valid_sources[0x50]	3719615	1			T3	247		T4	3		T16	74
valid_sources[0x51]	1473299	1			T3	137		T4	6		T16	115
valid_sources[0x52]	1350569	1			T2	5		T3	160		T4	6
valid_sources[0x53]	1674483	1			T3	128		T4	2		T16	30
valid_sources[0x54]	1356757	1			T3	251		T4	5		T16	177
valid_sources[0x55]	1498375	1			T3	189		T4	2		T16	62
valid_sources[0x56]	1350946	1			T3	206		T4	5		T16	144
valid_sources[0x57]	1354230	1			T3	252		T4	2		T16	49
valid_sources[0x58]	1352033	1			T2	1		T3	102		T4	2
valid_sources[0x59]	1428175	1			T3	178		T4	4		T16	169
valid_sources[0x5a]	1530892	1			T3	163		T4	5		T16	127
valid_sources[0x5b]	3294966	1			T2	2		T3	119		T4	2
valid_sources[0x5c]	1406958	1			T3	169		T4	2		T16	100
valid_sources[0x5d]	1465815	1			T3	172		T4	6		T16	33
valid_sources[0x5e]	1353686	1			T3	201		T4	3		T16	67
valid_sources[0x5f]	2355080	1			T3	111		T4	4		T16	172
valid_sources[0x60]	1365100	1			T3	171		T4	3		T16	158
valid_sources[0x61]	1353703	1			T3	130		T4	9		T16	86
valid_sources[0x62]	1382465	1			T3	171		T4	5		T16	81
valid_sources[0x63]	1353666	1			T3	225		T4	6		T16	90
valid_sources[0x64]	1995040	1			T3	209		T4	4		T16	130
valid_sources[0x65]	1401787	1			T2	1		T3	185		T4	5
valid_sources[0x66]	1351211	1			T3	151		T4	5		T16	126
valid_sources[0x67]	1350095	1			T3	120		T4	7		T16	67
valid_sources[0x68]	1357706	1			T3	184		T4	4		T16	70
valid_sources[0x69]	2236990	1			T2	6		T3	157		T4	2
valid_sources[0x6a]	1531434	1			T3	123		T4	6		T16	143
valid_sources[0x6b]	1355484	1			T3	220		T4	8		T16	128
valid_sources[0x6c]	1351637	1			T3	185		T4	4		T16	122
valid_sources[0x6d]	1347937	1			T3	199		T4	3		T16	97
valid_sources[0x6e]	1954883	1			T3	147		T4	3		T16	177
valid_sources[0x6f]	1354456	1			T3	88		T4	4		T16	68
valid_sources[0x70]	4570331	1			T2	1		T3	207		T4	4
valid_sources[0x71]	1353813	1			T2	1		T3	195		T4	3
valid_sources[0x72]	1353776	1			T2	4		T3	149		T4	5
valid_sources[0x73]	3329939	1			T3	191		T4	4		T16	64
valid_sources[0x74]	1350007	1			T2	3		T3	175		T4	5
valid_sources[0x75]	1352331	1			T3	177		T4	4		T16	156
valid_sources[0x76]	3658509	1			T3	155		T4	3		T16	99
valid_sources[0x77]	1353897	1			T3	251		T4	6		T16	162
valid_sources[0x78]	1408536	1			T3	208		T4	3		T16	118
valid_sources[0x79]	1513272	1			T2	5		T3	205		T4	2
valid_sources[0x7a]	1351635	1			T2	1		T3	142		T4	4
valid_sources[0x7b]	5249795	1			T2	1		T3	210		T4	6
valid_sources[0x7c]	2005079	1			T3	178		T4	3		T16	218
valid_sources[0x7d]	1353993	1			T2	2		T3	150		T4	3
valid_sources[0x7e]	1350804	1			T3	140		T4	7		T16	66
valid_sources[0x7f]	1352863	1			T2	5		T3	149		T4	4
valid_sources[0x80]	1350952	1			T3	168		T4	6		T16	124

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70598434

1

T1

335314

T2

71

T3

20706

values[0x0]

all_enables

biggest_size

59613772

1

T1

312060

T2

47

T3

9624

values[0x1]

all_enables

biggest_size

51251308

1

T1

264426

T2

48

T3

9672