Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256373383

1

T1

140784

T2

20

T3

3536

full_word

181513785

1

T1

911800

T2

166

T3

40002

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	437886888	1			T1	231964		T2	186		T3	43538
auto[TlIntgErrCmd]	88	1			T113	2		T114	2		T115	8
auto[TlIntgErrData]	90	1			T113	6		T114	2		T115	2
auto[TlIntgErrBoth]	102	1			T113	2		T114	6		T168	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

226538616

1

T1

117692

T2

74

T3

21061

auto[1]

211348552

1

T1

114271

T2

112

T3

22477

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	155927483	1			T1	841615		T2	3		T3	355
auto[TlIntgErrNone]	partial	auto[1]	100445637	1			T1	566225		T2	17		T3	3181
auto[TlIntgErrNone]	full_word	auto[0]	70611000	1			T1	335314		T2	71		T3	20706
auto[TlIntgErrNone]	full_word	auto[1]	110902768	1			T1	576486		T2	95		T3	19296
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T114	1		T115	2		T168	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T113	1		T114	1		T115	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T169	2		T170	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T113	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1			T113	2		T114	2		T115	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T113	4		T115	1		T168	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T171	1		T172	1		T173	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T174	1		T162	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T114	2		T168	1		T171	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T113	2		T114	4		T171	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T171	1		T162	1		T175	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T171	1		T165	1		T169	1