Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	343493	0	0
RunThenComplete_M	2147483647	3002994	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	343493	0	0
T1	261705	2337	0	0
T2	3113	0	0	0
T3	682869	0	0	0
T4	65150	9	0	0
T5	27617	2	0	0
T6	17637	2	0	0
T7	0	214	0	0
T15	174431	2337	0	0
T16	274064	24	0	0
T18	117815	159	0	0
T33	19513	9	0	0
T35	0	2337	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3002994	0	0
T1	261705	13147	0	0
T2	3113	0	0	0
T3	682869	0	0	0
T4	65150	27	0	0
T5	27617	6	0	0
T6	17637	6	0	0
T7	0	3855	0	0
T15	174431	13147	0	0
T16	274064	132	0	0
T18	117815	814	0	0
T33	19513	31	0	0
T35	0	13147	0	0