Module Definition
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Module : keccak_round
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.81 94.55 100.00 73.33 91.18 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sha3.u_keccak 91.81 94.55 100.00 73.33 91.18 100.00



Module Instance : tb.dut.u_sha3.u_keccak

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.81 94.55 100.00 73.33 91.18 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.79 98.83 98.84 100.00 73.33 97.76 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.96 97.56 88.89 100.00 93.33 100.00 u_sha3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_keccak_p 99.42 100.00 98.75 98.93 100.00
u_prim_sec_anchor_buf 100.00 100.00
u_round_count 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : keccak_round
Line No.TotalCoveredPercent
TOTAL11010494.55
CONT_ASSIGN17700
ALWAYS18033100.00
ALWAYS186706592.86
CONT_ASSIGN40711100.00
ALWAYS41177100.00
ALWAYS42433100.00
CONT_ASSIGN45011100.00
ALWAYS46866100.00
CONT_ASSIGN47711100.00
ALWAYS48577100.00
ALWAYS5074375.00
CONT_ASSIGN51811100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55111100.00
ALWAYS57533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
177 unreachable
180 3 3
186 1 1
188 1 1
189 1 1
190 1 1
192 1 1
193 1 1
195 1 1
196 1 1
198 1 1
199 1 1
200 1 1
201 1 1
202 1 1
204 1 1
206 1 1
208 1 1
210 1 1
212 1 1
214 1 1
215 1 1
216 1 1
221 1 1
223 1 1
224 1 1
226 1 1
229 1 1
230 1 1
231 1 1
233 unreachable
235 1 1
241 0 1
243 0 1
244 unreachable
246 unreachable
247 unreachable
249 0 1
251 0 1
260 1 1
261 1 1
272 1 1
273 1 1
274 1 1
275 1 1
278 1 1
281 1 1
282 1 1
284 1 1
292 1 1
293 1 1
301 1 1
304 1 1
307 1 1
308 1 1
317 1 1
318 1 1
327 1 1
333 1 1
336 1 1
339 1 1
342 1 1
343 1 1
352 1 1
353 1 1
361 1 1
363 1 1
365 unreachable
367 unreachable
368 unreachable
371 1 1
373 1 1
376 1 1
377 1 1
382 0 1
387 1 1
388 1 1
400 1 1
401 1 1
MISSING_ELSE
407 1 1
411 1 1
412 1 1
413 1 1
414 1 1
416 1 1
417 1 1
418 1 1
424 1 1
425 1 1
427 1 1
450 1 1
468 1 1
469 1 1
470 1 1
471 1 1
472 1 1
473 1 1
MISSING_ELSE
477 1 1
485 1 1
486 1 1
487 1 1
488 1 1
492 1 1
493 1 1
496 1 1
MISSING_ELSE
507 1 1
509 1 1
511 1 1
513 0 1
MISSING_ELSE
MISSING_ELSE
518 1 1
548 1 1
549 1 1
551 1 1
575 1 1
576 1 1
578 1 1


Cond Coverage for Module : keccak_round
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       177
 EXPRESSION (int'(round) == (MaxRound - 1))
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1UnreachableT1,T4,T15

 LINE       224
 EXPRESSION (EnMasking && run_i)
             ----1----    --2--
-1--2-StatusTests
-0CoveredT1,T2,T3
-1CoveredT1,T2,T4

 LINE       272
 EXPRESSION (rand_early_i || rand_valid_i)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT1,T34,T48
01CoveredT1,T2,T4
10CoveredT1,T34,T48

 LINE       450
 EXPRESSION ((keccak_st == KeccakStIdle) ? 1'b1 : 1'b0)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       450
 SUB-EXPRESSION (keccak_st == KeccakStIdle)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       492
 EXPRESSION (addr_i == i[(DInAddr - 1):0])
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

FSM Coverage for Module : keccak_round
Summary for FSM :: keccak_st
TotalCoveredPercent
States 8 6 75.00 (Not included in score)
Transitions 15 11 73.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: keccak_st
statesLine No.CoveredTests
KeccakStActive 233 Not Covered
KeccakStError 382 Not Covered
KeccakStIdle 212 Covered T1,T2,T3
KeccakStPhase1 226 Covered T1,T2,T4
KeccakStPhase2Cycle1 273 Covered T1,T4,T15
KeccakStPhase2Cycle2 304 Covered T1,T4,T15
KeccakStPhase2Cycle3 339 Covered T1,T4,T15
KeccakStTerminalError 401 Covered T2,T3,T12


transitionsLine No.CoveredTests
KeccakStActive->KeccakStIdle 244 Not Covered
KeccakStActive->KeccakStTerminalError 401 Not Covered
KeccakStError->KeccakStTerminalError 401 Not Covered
KeccakStIdle->KeccakStActive 233 Not Covered
KeccakStIdle->KeccakStPhase1 226 Covered T1,T2,T4
KeccakStIdle->KeccakStTerminalError 401 Covered T3,T12,T31
KeccakStPhase1->KeccakStPhase2Cycle1 273 Covered T1,T4,T15
KeccakStPhase1->KeccakStTerminalError 401 Covered T2,T26,T49
KeccakStPhase2Cycle1->KeccakStPhase2Cycle2 304 Covered T1,T4,T15
KeccakStPhase2Cycle1->KeccakStTerminalError 401 Covered T50,T51
KeccakStPhase2Cycle2->KeccakStPhase2Cycle3 339 Covered T1,T4,T15
KeccakStPhase2Cycle2->KeccakStTerminalError 401 Covered T52,T53,T54
KeccakStPhase2Cycle3->KeccakStIdle 365 Covered T1,T4,T15
KeccakStPhase2Cycle3->KeccakStPhase1 371 Covered T1,T4,T15
KeccakStPhase2Cycle3->KeccakStTerminalError 401 Covered T30,T55,T56



Branch Coverage for Module : keccak_round
Line No.TotalCoveredPercent
Branches 34 31 91.18
TERNARY 450 2 2 100.00
IF 180 2 2 100.00
CASE 208 13 11 84.62
IF 400 2 2 100.00
IF 468 4 4 100.00
IF 486 2 2 100.00
IF 509 3 2 66.67
IF 575 2 2 100.00
IF 411 2 2 100.00
IF 424 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 450 ((keccak_st == KeccakStIdle)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 180 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 208 case (keccak_st) -2-: 210 if (valid_i) -3-: 216 if (prim_mubi_pkg::mubi4_test_true_strict(clear_i)) -4-: 224 if ((EnMasking && run_i)) -5-: 231 if (((!EnMasking) && run_i)) -6-: 243 if (rnd_eq_end) -7-: 272 if ((rand_early_i || rand_valid_i)) -8-: 363 if (rnd_eq_end)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
KeccakStIdle 1 - - - - - - Covered T1,T2,T4
KeccakStIdle 0 1 - - - - - Covered T1,T4,T15
KeccakStIdle 0 0 1 - - - - Covered T1,T2,T4
KeccakStIdle 0 0 0 1 - - - Unreachable
KeccakStIdle 0 0 0 0 - - - Covered T1,T2,T3
KeccakStActive - - - - 1 - - Unreachable
KeccakStActive - - - - 0 - - Not Covered
KeccakStPhase1 - - - - - 1 - Covered T1,T2,T4
KeccakStPhase1 - - - - - 0 - Covered T1,T34,T48
KeccakStPhase2Cycle1 - - - - - - - Covered T1,T4,T15
KeccakStPhase2Cycle2 - - - - - - - Covered T1,T4,T15
KeccakStPhase2Cycle3 - - - - - - 1 Unreachable T1,T4,T15
KeccakStPhase2Cycle3 - - - - - - 0 Covered T1,T4,T15
KeccakStError - - - - - - - Not Covered
KeccakStTerminalError - - - - - - - Covered T2,T3,T12
default - - - - - - - Covered T3,T28,T29


LineNo. Expression -1-: 400 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:
-1-StatusTests
1 Covered T2,T3,T12
0 Covered T1,T2,T3


LineNo. Expression -1-: 468 if ((!rst_n)) -2-: 470 if (rst_storage) -3-: 472 if (update_storage)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T4,T15
0 0 1 Covered T1,T2,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 486 if (xor_message)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 if (rst_storage) -2-: 511 if (((keccak_st != KeccakStIdle) || prim_mubi_pkg::mubi4_test_false_loose(clear_i)))

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Covered T1,T4,T15
0 - Covered T1,T2,T3


LineNo. Expression -1-: 575 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 411 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 424 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : keccak_round
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ClearAssertStIdle_A 2147483647 343482 0 0
OneHot0ValidAndRun_A 2147483647 2147483647 0 0
ValidRunAssertStIdle_A 2147483647 54850107 0 0
WidthDivisableByDInWidth_A 1013 1013 0 0
gen_mask_st_chk.EnMaskingValidStates_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


ClearAssertStIdle_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 343482 0 0
T1 261705 2337 0 0
T2 3113 0 0 0
T3 682869 0 0 0
T4 65150 9 0 0
T5 27617 2 0 0
T6 17637 2 0 0
T7 0 214 0 0
T15 174431 2337 0 0
T16 274064 24 0 0
T18 117815 159 0 0
T33 19513 9 0 0
T35 0 2337 0 0

OneHot0ValidAndRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 261705 261704 0 0
T2 3113 2994 0 0
T3 682869 658598 0 0
T4 65150 65072 0 0
T5 27617 27548 0 0
T6 17637 17572 0 0
T15 174431 174430 0 0
T16 274064 273980 0 0
T18 117815 117810 0 0
T33 19513 19441 0 0

ValidRunAssertStIdle_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 54850107 0 0
T1 261705 289234 0 0
T2 3113 18 0 0
T3 682869 0 0 0
T4 65150 486 0 0
T5 27617 108 0 0
T6 17637 108 0 0
T15 174431 289234 0 0
T16 274064 2685 0 0
T18 117815 16676 0 0
T33 19513 638 0 0
T35 0 289234 0 0

WidthDivisableByDInWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1013 1013 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T33 1 1 0 0

gen_mask_st_chk.EnMaskingValidStates_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 261705 261704 0 0
T2 3113 2994 0 0
T3 682869 658598 0 0
T4 65150 65072 0 0
T5 27617 27548 0 0
T6 17637 17572 0 0
T15 174431 174430 0 0
T16 274064 273980 0 0
T18 117815 117810 0 0
T33 19513 19441 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 261705 261704 0 0
T2 3113 2994 0 0
T3 682869 658598 0 0
T4 65150 65072 0 0
T5 27617 27548 0 0
T6 17637 17572 0 0
T15 174431 174430 0 0
T16 274064 273980 0 0
T18 117815 117810 0 0
T33 19513 19441 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%