Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	184312	0	0
entropy_period_rd_A	2147483647	1584	0	0
intr_enable_rd_A	2147483647	2072	0	0
prefix_0_rd_A	2147483647	1253	0	0
prefix_10_rd_A	2147483647	1168	0	0
prefix_1_rd_A	2147483647	1076	0	0
prefix_2_rd_A	2147483647	1297	0	0
prefix_3_rd_A	2147483647	1251	0	0
prefix_4_rd_A	2147483647	1224	0	0
prefix_5_rd_A	2147483647	1178	0	0
prefix_6_rd_A	2147483647	1096	0	0
prefix_7_rd_A	2147483647	1130	0	0
prefix_8_rd_A	2147483647	1144	0	0
prefix_9_rd_A	2147483647	1158	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	184312	0	0
T45	417567	58357	0	0
T46	0	86975	0	0
T47	0	35762	0	0
T113	0	1	0	0
T114	0	2	0	0
T119	0	2	0	0
T120	0	2	0	0
T121	0	2	0	0
T122	0	82	0	0
T123	0	178	0	0
T125	162435	0	0	0
T126	576773	0	0	0
T127	10244	0	0	0
T128	1596	0	0	0
T129	544283	0	0	0
T130	612435	0	0	0
T131	184911	0	0	0
T132	8853	0	0	0
T133	689895	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1584	0	0
T93	13266	46	0	0
T95	2572	7	0	0
T101	5306	9	0	0
T114	12659	50	0	0
T115	12466	64	0	0
T120	4620	18	0	0
T121	7724	20	0	0
T145	1957	1	0	0
T146	62564	106	0	0
T147	5707	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2072	0	0
T93	13266	63	0	0
T95	2572	7	0	0
T101	5306	9	0	0
T114	12659	53	0	0
T117	1053	6	0	0
T120	4620	4	0	0
T121	7724	34	0	0
T145	1957	1	0	0
T146	62564	113	0	0
T148	1674	6	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1253	0	0
T93	13266	61	0	0
T95	2572	8	0	0
T101	5306	19	0	0
T114	12659	46	0	0
T115	12466	51	0	0
T120	4620	10	0	0
T121	7724	24	0	0
T145	1957	1	0	0
T146	62564	160	0	0
T147	5707	9	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1168	0	0
T93	13266	12	0	0
T95	2572	13	0	0
T101	5306	15	0	0
T114	12659	37	0	0
T115	12466	39	0	0
T120	4620	8	0	0
T121	7724	21	0	0
T145	1957	1	0	0
T146	62564	108	0	0
T149	11758	1	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1076	0	0
T93	13266	28	0	0
T95	2572	6	0	0
T96	12386	35	0	0
T101	5306	17	0	0
T114	12659	51	0	0
T115	12466	35	0	0
T120	4620	11	0	0
T121	7724	15	0	0
T146	62564	74	0	0
T147	5707	16	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1297	0	0
T93	13266	32	0	0
T95	2572	8	0	0
T101	5306	13	0	0
T114	12659	48	0	0
T115	12466	36	0	0
T120	4620	6	0	0
T121	7724	11	0	0
T145	1957	4	0	0
T146	62564	107	0	0
T147	5707	18	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1251	0	0
T93	13266	38	0	0
T95	2572	7	0	0
T96	12386	63	0	0
T101	5306	18	0	0
T114	12659	38	0	0
T115	12466	46	0	0
T120	4620	10	0	0
T121	7724	15	0	0
T146	62564	152	0	0
T147	5707	7	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1224	0	0
T93	13266	29	0	0
T95	2572	9	0	0
T96	12386	55	0	0
T101	5306	18	0	0
T114	12659	36	0	0
T115	12466	49	0	0
T120	4620	17	0	0
T121	7724	20	0	0
T146	62564	151	0	0
T147	5707	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1178	0	0
T93	13266	3	0	0
T95	2572	11	0	0
T96	12386	53	0	0
T101	5306	12	0	0
T114	12659	45	0	0
T115	12466	25	0	0
T120	4620	8	0	0
T121	7724	10	0	0
T146	62564	141	0	0
T147	5707	23	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1096	0	0
T93	13266	29	0	0
T101	5306	21	0	0
T114	12659	33	0	0
T115	12466	48	0	0
T120	4620	6	0	0
T121	7724	17	0	0
T145	1957	8	0	0
T146	62564	120	0	0
T147	5707	6	0	0
T149	11758	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1130	0	0
T93	13266	30	0	0
T95	2572	4	0	0
T96	12386	51	0	0
T101	5306	14	0	0
T114	12659	39	0	0
T115	12466	39	0	0
T120	4620	9	0	0
T121	7724	15	0	0
T145	1957	5	0	0
T146	62564	105	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1144	0	0
T93	13266	41	0	0
T95	2572	18	0	0
T96	12386	45	0	0
T101	5306	25	0	0
T114	12659	39	0	0
T115	12466	31	0	0
T120	4620	2	0	0
T121	7724	17	0	0
T146	62564	139	0	0
T147	5707	19	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1158	0	0
T93	13266	22	0	0
T95	2572	9	0	0
T101	5306	9	0	0
T114	12659	36	0	0
T115	12466	42	0	0
T120	4620	12	0	0
T121	7724	19	0	0
T145	1957	5	0	0
T146	62564	153	0	0
T147	5707	26	0	0