Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259713079

1

T1

86424

T2

407299

T3

630

full_word

184347412

1

T1

78585

T2

268319

T3

1068

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	444060201	1			T1	165009		T2	675618		T3	1698
auto[TlIntgErrCmd]	100	1			T117	6		T118	6		T119	7
auto[TlIntgErrData]	93	1			T117	8		T118	7		T119	7
auto[TlIntgErrBoth]	97	1			T117	6		T118	7		T119	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229918566

1

T1

90640

T2

363138

T3

717

auto[1]

214141925

1

T1

74369

T2

312480

T3

981

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158736597	1			T1	55450		T2	250162		T3	367
auto[TlIntgErrNone]	partial	auto[1]	100976215	1			T1	30974		T2	157137		T3	263
auto[TlIntgErrNone]	full_word	auto[0]	71181842	1			T1	35190		T2	112976		T3	350
auto[TlIntgErrNone]	full_word	auto[1]	113165547	1			T1	43395		T2	155343		T3	718
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T117	1		T119	2		T167	1
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T117	5		T118	6		T119	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T168	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T119	1		T166	1		T123	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T117	4		T118	4		T119	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T117	4		T118	3		T119	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T119	1		T169	1		T170	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T119	1		T171	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T117	2		T118	3		T119	2
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T117	4		T118	1		T119	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T118	2		T119	1		T173	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T118	1		T166	1		T172	1