Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	333638	0	0
entropy_period_rd_A	2147483647	2028	0	0
intr_enable_rd_A	2147483647	2341	0	0
prefix_0_rd_A	2147483647	1858	0	0
prefix_10_rd_A	2147483647	1858	0	0
prefix_1_rd_A	2147483647	1868	0	0
prefix_2_rd_A	2147483647	1781	0	0
prefix_3_rd_A	2147483647	2018	0	0
prefix_4_rd_A	2147483647	1927	0	0
prefix_5_rd_A	2147483647	1847	0	0
prefix_6_rd_A	2147483647	1816	0	0
prefix_7_rd_A	2147483647	1982	0	0
prefix_8_rd_A	2147483647	1865	0	0
prefix_9_rd_A	2147483647	1780	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333638	0	0
T45	106509	151841	0	0
T46	0	85634	0	0
T47	0	92774	0	0
T117	0	4	0	0
T118	0	3	0	0
T119	0	1	0	0
T126	0	110	0	0
T127	0	4	0	0
T128	0	357	0	0
T129	0	5	0	0
T130	148461	0	0	0
T131	3631	0	0	0
T132	18133	0	0	0
T133	114341	0	0	0
T134	24138	0	0	0
T135	142974	0	0	0
T136	388610	0	0	0
T137	689467	0	0	0
T138	111857	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2028	0	0
T118	22666	112	0	0
T141	7652	8	0	0
T148	10965	94	0	0
T149	2825	6	0	0
T150	1918	3	0	0
T151	5836	4	0	0
T152	2024	2	0	0
T153	2901	4	0	0
T154	11010	32	0	0
T155	48606	435	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2341	0	0
T118	22666	173	0	0
T120	1116	28	0	0
T121	1208	3	0	0
T126	7527	9	0	0
T141	7652	5	0	0
T148	10965	10	0	0
T149	2825	12	0	0
T151	5836	22	0	0
T152	2024	8	0	0
T156	1398	10	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1858	0	0
T118	22666	90	0	0
T141	7652	19	0	0
T148	10965	17	0	0
T149	2825	2	0	0
T150	1918	1	0	0
T151	5836	34	0	0
T152	2024	4	0	0
T153	2901	4	0	0
T154	11010	57	0	0
T155	48606	435	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1858	0	0
T118	22666	79	0	0
T141	7652	10	0	0
T148	10965	58	0	0
T149	2825	3	0	0
T150	1918	2	0	0
T151	5836	1	0	0
T152	2024	3	0	0
T153	2901	4	0	0
T154	11010	57	0	0
T155	48606	504	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1868	0	0
T118	22666	82	0	0
T148	10965	81	0	0
T149	2825	6	0	0
T150	1918	3	0	0
T151	5836	11	0	0
T152	2024	2	0	0
T153	2901	13	0	0
T154	11010	30	0	0
T155	48606	445	0	0
T157	3575	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1781	0	0
T118	22666	80	0	0
T141	7652	20	0	0
T148	10965	41	0	0
T149	2825	8	0	0
T150	1918	5	0	0
T151	5836	3	0	0
T152	2024	5	0	0
T153	2901	9	0	0
T154	11010	37	0	0
T155	48606	430	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2018	0	0
T118	22666	68	0	0
T141	7652	2	0	0
T148	10965	98	0	0
T149	2825	10	0	0
T150	1918	1	0	0
T151	5836	25	0	0
T152	2024	5	0	0
T153	2901	4	0	0
T154	11010	65	0	0
T155	48606	493	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1927	0	0
T118	22666	70	0	0
T141	7652	8	0	0
T148	10965	14	0	0
T149	2825	10	0	0
T150	1918	5	0	0
T151	5836	12	0	0
T152	2024	5	0	0
T153	2901	17	0	0
T154	11010	9	0	0
T155	48606	443	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1847	0	0
T118	22666	81	0	0
T141	7652	6	0	0
T148	10965	51	0	0
T149	2825	6	0	0
T150	1918	4	0	0
T151	5836	19	0	0
T152	2024	6	0	0
T153	2901	11	0	0
T154	11010	52	0	0
T155	48606	467	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1816	0	0
T118	22666	83	0	0
T126	7527	3	0	0
T141	7652	5	0	0
T148	10965	37	0	0
T149	2825	3	0	0
T151	5836	21	0	0
T152	2024	3	0	0
T153	2901	8	0	0
T154	11010	22	0	0
T155	48606	427	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1982	0	0
T118	22666	91	0	0
T141	7652	9	0	0
T148	10965	48	0	0
T149	2825	7	0	0
T150	1918	2	0	0
T151	5836	64	0	0
T152	2024	1	0	0
T153	2901	7	0	0
T154	11010	73	0	0
T155	48606	494	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1865	0	0
T118	22666	89	0	0
T141	7652	6	0	0
T148	10965	45	0	0
T149	2825	2	0	0
T150	1918	4	0	0
T151	5836	52	0	0
T152	2024	8	0	0
T153	2901	14	0	0
T154	11010	37	0	0
T155	48606	474	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1780	0	0
T118	22666	84	0	0
T141	7652	12	0	0
T148	10965	19	0	0
T149	2825	9	0	0
T150	1918	2	0	0
T151	5836	13	0	0
T152	2024	1	0	0
T153	2901	5	0	0
T154	11010	62	0	0
T155	48606	385	0	0