Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163058 |
1 |
|
|
T7 |
2497 |
|
T8 |
422 |
|
T9 |
3023 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
89242 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
52685 |
1 |
|
|
T7 |
64 |
|
T8 |
253 |
|
T9 |
67 |
seven_bytes |
3051 |
1 |
|
|
T7 |
64 |
|
T8 |
5 |
|
T9 |
78 |
six_bytes |
2954 |
1 |
|
|
T7 |
50 |
|
T8 |
4 |
|
T9 |
74 |
five_bytes |
2985 |
1 |
|
|
T7 |
69 |
|
T8 |
3 |
|
T9 |
78 |
four_bytes |
3030 |
1 |
|
|
T7 |
57 |
|
T8 |
3 |
|
T9 |
77 |
three_bytes |
3014 |
1 |
|
|
T7 |
79 |
|
T8 |
3 |
|
T9 |
75 |
two_bytes |
3047 |
1 |
|
|
T7 |
66 |
|
T8 |
4 |
|
T9 |
90 |
one_byte |
3050 |
1 |
|
|
T7 |
67 |
|
T8 |
7 |
|
T9 |
84 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
160014 |
1 |
|
|
T7 |
2459 |
|
T8 |
414 |
|
T9 |
2985 |
auto[1] |
3044 |
1 |
|
|
T7 |
38 |
|
T8 |
8 |
|
T9 |
38 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163058 |
1 |
|
|
T7 |
2497 |
|
T8 |
422 |
|
T9 |
3023 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163048 |
1 |
|
|
T7 |
2497 |
|
T8 |
422 |
|
T9 |
3023 |
auto[1] |
10 |
1 |
|
|
T48 |
1 |
|
T182 |
1 |
|
T183 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1030 |
1 |
|
|
T7 |
4 |
|
T8 |
3 |
|
T9 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3044 |
1 |
|
|
T7 |
38 |
|
T8 |
8 |
|
T9 |
38 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166935 |
1 |
|
|
T7 |
1826 |
|
T8 |
125 |
|
T9 |
1777 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
90366 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
55050 |
1 |
|
|
T7 |
170 |
|
T8 |
3 |
|
T9 |
48 |
seven_bytes |
3043 |
1 |
|
|
T7 |
54 |
|
T8 |
6 |
|
T9 |
41 |
six_bytes |
3020 |
1 |
|
|
T7 |
53 |
|
T8 |
2 |
|
T9 |
47 |
five_bytes |
3075 |
1 |
|
|
T7 |
44 |
|
T8 |
1 |
|
T9 |
51 |
four_bytes |
3136 |
1 |
|
|
T7 |
47 |
|
T8 |
4 |
|
T9 |
48 |
three_bytes |
3037 |
1 |
|
|
T7 |
53 |
|
T8 |
3 |
|
T9 |
55 |
two_bytes |
3033 |
1 |
|
|
T7 |
44 |
|
T8 |
5 |
|
T9 |
45 |
one_byte |
3175 |
1 |
|
|
T7 |
45 |
|
T8 |
1 |
|
T9 |
55 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163785 |
1 |
|
|
T7 |
1800 |
|
T8 |
119 |
|
T9 |
1751 |
auto[1] |
3150 |
1 |
|
|
T7 |
26 |
|
T8 |
6 |
|
T9 |
26 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166935 |
1 |
|
|
T7 |
1826 |
|
T8 |
125 |
|
T9 |
1777 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166926 |
1 |
|
|
T7 |
1826 |
|
T8 |
125 |
|
T9 |
1777 |
auto[1] |
9 |
1 |
|
|
T6 |
1 |
|
T184 |
1 |
|
T185 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1059 |
1 |
|
|
T7 |
3 |
|
T8 |
1 |
|
T9 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3150 |
1 |
|
|
T7 |
26 |
|
T8 |
6 |
|
T9 |
26 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
319516 |
1 |
|
|
T7 |
5792 |
|
T8 |
1112 |
|
T9 |
4974 |
auto[1] |
374 |
1 |
|
|
T6 |
49 |
|
T10 |
11 |
|
T11 |
40 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
170375 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
109166 |
1 |
|
|
T7 |
264 |
|
T8 |
302 |
|
T9 |
125 |
seven_bytes |
5785 |
1 |
|
|
T7 |
149 |
|
T8 |
24 |
|
T9 |
132 |
six_bytes |
5798 |
1 |
|
|
T7 |
149 |
|
T8 |
28 |
|
T9 |
107 |
five_bytes |
5783 |
1 |
|
|
T7 |
171 |
|
T8 |
19 |
|
T9 |
108 |
four_bytes |
5769 |
1 |
|
|
T7 |
145 |
|
T8 |
11 |
|
T9 |
121 |
three_bytes |
5768 |
1 |
|
|
T7 |
155 |
|
T8 |
22 |
|
T9 |
131 |
two_bytes |
5673 |
1 |
|
|
T7 |
137 |
|
T8 |
22 |
|
T9 |
129 |
one_byte |
5773 |
1 |
|
|
T7 |
145 |
|
T8 |
23 |
|
T9 |
160 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
313749 |
1 |
|
|
T7 |
5720 |
|
T8 |
1096 |
|
T9 |
4914 |
auto[1] |
6141 |
1 |
|
|
T7 |
72 |
|
T8 |
16 |
|
T9 |
60 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
319890 |
1 |
|
|
T7 |
5792 |
|
T8 |
1112 |
|
T9 |
4974 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
319866 |
1 |
|
|
T7 |
5792 |
|
T8 |
1112 |
|
T9 |
4974 |
auto[1] |
24 |
1 |
|
|
T19 |
1 |
|
T16 |
1 |
|
T6 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2062 |
1 |
|
|
T7 |
9 |
|
T8 |
4 |
|
T9 |
7 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6141 |
1 |
|
|
T7 |
72 |
|
T8 |
16 |
|
T9 |
60 |