Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258087623

1

T1

16

T2

5988

T3

765

full_word

181404622

1

T1

12

T2

8726

T3

1061

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	439491955	1			T1	28		T2	14714		T3	1826
auto[TlIntgErrCmd]	77	1			T89	3		T125	5		T126	4
auto[TlIntgErrData]	98	1			T89	5		T125	8		T126	3
auto[TlIntgErrBoth]	115	1			T89	12		T125	7		T126	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228084290

1

T1

1

T2

9908

T3

781

auto[1]

211407955

1

T1

27

T2

4806

T3

1045

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158102175	1			T2	3701		T3	417		T18	2475
auto[TlIntgErrNone]	partial	auto[1]	99985191	1			T1	16		T2	2287		T3	348
auto[TlIntgErrNone]	full_word	auto[0]	69981994	1			T1	1		T2	6207		T3	364
auto[TlIntgErrNone]	full_word	auto[1]	111422595	1			T1	11		T2	2519		T3	697
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T89	1		T125	3		T126	2
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T89	2		T125	2		T126	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T167	1		T189	1		T190	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T138	1		T191	1		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1			T89	2		T125	3		T126	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T89	2		T125	5		T126	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T192	1		T190	1		T193	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T89	1		T167	1		T191	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T89	6		T125	1		T167	3
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T89	5		T125	5		T126	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T167	1		T194	1		T188	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T89	1		T125	1		T191	1