Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	50980	0	0
entropy_period_rd_A	2147483647	953	0	0
intr_enable_rd_A	2147483647	1529	0	0
prefix_0_rd_A	2147483647	1025	0	0
prefix_10_rd_A	2147483647	1026	0	0
prefix_1_rd_A	2147483647	1025	0	0
prefix_2_rd_A	2147483647	957	0	0
prefix_3_rd_A	2147483647	902	0	0
prefix_4_rd_A	2147483647	1004	0	0
prefix_5_rd_A	2147483647	987	0	0
prefix_6_rd_A	2147483647	968	0	0
prefix_7_rd_A	2147483647	1046	0	0
prefix_8_rd_A	2147483647	1007	0	0
prefix_9_rd_A	2147483647	1089	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50980	0	0
T26	598177	48275	0	0
T89	0	2	0	0
T106	0	157	0	0
T124	0	202	0	0
T126	0	1	0	0
T128	0	16	0	0
T140	0	7	0	0
T141	0	70	0	0
T142	0	2	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T152	0	4	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	953	0	0
T26	598177	57	0	0
T88	0	2	0	0
T91	0	69	0	0
T96	0	10	0	0
T126	0	84	0	0
T140	0	15	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T164	0	35	0	0
T165	0	2	0	0
T166	0	6	0	0
T167	0	125	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1529	0	0
T26	598177	42	0	0
T91	0	95	0	0
T96	0	18	0	0
T126	0	125	0	0
T140	0	18	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T164	0	40	0	0
T165	0	13	0	0
T166	0	1	0	0
T167	0	132	0	0
T168	0	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1025	0	0
T26	598177	36	0	0
T88	0	2	0	0
T91	0	53	0	0
T96	0	7	0	0
T126	0	42	0	0
T140	0	29	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T164	0	22	0	0
T165	0	3	0	0
T166	0	1	0	0
T167	0	79	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1026	0	0
T26	598177	58	0	0
T88	0	7	0	0
T91	0	40	0	0
T96	0	5	0	0
T126	0	49	0	0
T140	0	11	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T164	0	27	0	0
T165	0	2	0	0
T166	0	7	0	0
T167	0	71	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1025	0	0
T26	598177	64	0	0
T88	0	1	0	0
T91	0	51	0	0
T106	0	8	0	0
T126	0	36	0	0
T140	0	22	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T164	0	12	0	0
T165	0	11	0	0
T166	0	2	0	0
T167	0	81	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	957	0	0
T26	598177	38	0	0
T88	0	4	0	0
T91	0	64	0	0
T96	0	16	0	0
T126	0	40	0	0
T140	0	18	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T164	0	2	0	0
T165	0	5	0	0
T166	0	9	0	0
T167	0	94	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	902	0	0
T26	598177	47	0	0
T88	0	5	0	0
T91	0	55	0	0
T96	0	8	0	0
T126	0	35	0	0
T140	0	20	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T164	0	37	0	0
T165	0	7	0	0
T167	0	78	0	0
T168	0	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1004	0	0
T26	598177	34	0	0
T88	0	2	0	0
T91	0	50	0	0
T96	0	11	0	0
T126	0	34	0	0
T140	0	18	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T164	0	37	0	0
T165	0	8	0	0
T166	0	7	0	0
T167	0	79	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	987	0	0
T26	598177	98	0	0
T88	0	3	0	0
T91	0	41	0	0
T96	0	15	0	0
T126	0	50	0	0
T140	0	5	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T165	0	3	0	0
T166	0	4	0	0
T167	0	81	0	0
T168	0	11	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	968	0	0
T26	598177	74	0	0
T88	0	6	0	0
T91	0	38	0	0
T96	0	14	0	0
T126	0	22	0	0
T140	0	21	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T165	0	7	0	0
T166	0	5	0	0
T167	0	67	0	0
T169	0	31	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1046	0	0
T26	598177	50	0	0
T88	0	4	0	0
T91	0	70	0	0
T106	0	6	0	0
T126	0	27	0	0
T140	0	22	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T164	0	15	0	0
T165	0	3	0	0
T166	0	9	0	0
T167	0	72	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1007	0	0
T26	598177	29	0	0
T88	0	7	0	0
T91	0	52	0	0
T96	0	12	0	0
T126	0	55	0	0
T140	0	25	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T164	0	9	0	0
T166	0	5	0	0
T167	0	81	0	0
T169	0	39	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1089	0	0
T26	598177	89	0	0
T88	0	6	0	0
T91	0	56	0	0
T96	0	18	0	0
T126	0	32	0	0
T140	0	13	0	0
T143	153177	0	0	0
T144	46996	0	0	0
T145	579693	0	0	0
T146	191558	0	0	0
T147	137898	0	0	0
T148	271866	0	0	0
T149	1618	0	0	0
T150	112597	0	0	0
T151	146604	0	0	0
T165	0	5	0	0
T166	0	3	0	0
T167	0	112	0	0
T168	0	10	0	0