Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	259724805	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

186565632

1

T1

9381

T2

345092

T3

477435

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	230535760	1			T1	10246		T2	454319		T3	631645
values[0x0]	103751881	1			T1	2445		T2	217634		T3	265876
values[0x1]	112002796	1			T1	2585		T2	236926		T3	287792

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202039767	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

244250670

1

T1

10683

T2

469311

T3

634866

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3574208	1			T1	58		T2	3643		T3	4651
valid_sources[0x01]	1280112	1			T1	62		T2	3297		T3	4664
valid_sources[0x02]	1249096	1			T1	36		T2	3547		T3	4592
valid_sources[0x03]	1495146	1			T1	48		T2	3553		T3	4625
valid_sources[0x04]	1288756	1			T1	33		T2	3475		T3	4560
valid_sources[0x05]	1899050	1			T1	41		T2	3459		T3	4621
valid_sources[0x06]	2287403	1			T1	49		T2	3445		T3	4645
valid_sources[0x07]	1253657	1			T1	48		T2	3590		T3	4564
valid_sources[0x08]	1252523	1			T1	43		T2	3648		T3	4705
valid_sources[0x09]	1253757	1			T1	73		T2	3724		T3	4628
valid_sources[0x0a]	1276460	1			T1	81		T2	3431		T3	4600
valid_sources[0x0b]	2124199	1			T1	76		T2	3429		T3	4655
valid_sources[0x0c]	2185405	1			T1	53		T2	3263		T3	4502
valid_sources[0x0d]	3602393	1			T1	56		T2	3573		T3	4498
valid_sources[0x0e]	1255648	1			T1	51		T2	3354		T3	4759
valid_sources[0x0f]	3633189	1			T1	66		T2	3651		T3	4650
valid_sources[0x10]	3581629	1			T1	56		T2	3667		T3	4603
valid_sources[0x11]	1275441	1			T1	72		T2	3776		T3	4536
valid_sources[0x12]	1258419	1			T1	48		T2	3444		T3	4603
valid_sources[0x13]	1911794	1			T1	48		T2	3558		T3	4627
valid_sources[0x14]	3579006	1			T1	77		T2	3681		T3	4530
valid_sources[0x15]	1258730	1			T1	64		T2	3750		T3	4639
valid_sources[0x16]	1249879	1			T1	47		T2	3422		T3	4631
valid_sources[0x17]	1263275	1			T1	61		T2	3425		T3	4679
valid_sources[0x18]	1402961	1			T1	65		T2	3693		T3	4644
valid_sources[0x19]	2117826	1			T1	44		T2	3536		T3	4607
valid_sources[0x1a]	1248381	1			T1	88		T2	3548		T3	4560
valid_sources[0x1b]	3862214	1			T1	60		T2	3599		T3	4631
valid_sources[0x1c]	1256251	1			T1	46		T2	3824		T3	4661
valid_sources[0x1d]	1249601	1			T1	62		T2	3595		T3	4619
valid_sources[0x1e]	1258625	1			T1	45		T2	3428		T3	4744
valid_sources[0x1f]	1252082	1			T1	42		T2	3545		T3	4670
valid_sources[0x20]	2856913	1			T1	39		T2	3731		T3	4607
valid_sources[0x21]	1251022	1			T1	60		T2	3595		T3	4645
valid_sources[0x22]	2187936	1			T1	64		T2	3742		T3	4610
valid_sources[0x23]	1260181	1			T1	49		T2	3319		T3	4679
valid_sources[0x24]	3592403	1			T1	62		T2	3371		T3	4515
valid_sources[0x25]	1257861	1			T1	76		T2	3617		T3	4621
valid_sources[0x26]	1405614	1			T1	71		T2	3516		T3	4625
valid_sources[0x27]	1249147	1			T1	66		T2	3484		T3	4650
valid_sources[0x28]	1252049	1			T1	49		T2	3677		T3	4540
valid_sources[0x29]	1250603	1			T1	66		T2	3478		T3	4727
valid_sources[0x2a]	1258104	1			T1	60		T2	3678		T3	4594
valid_sources[0x2b]	1254050	1			T1	82		T2	3158		T3	4567
valid_sources[0x2c]	1244487	1			T1	67		T2	3496		T3	4676
valid_sources[0x2d]	1251620	1			T1	61		T2	3596		T3	4601
valid_sources[0x2e]	1448875	1			T1	43		T2	3653		T3	4696
valid_sources[0x2f]	1252861	1			T1	39		T2	3464		T3	4605
valid_sources[0x30]	3602267	1			T1	57		T2	3539		T3	4649
valid_sources[0x31]	1257813	1			T1	39		T2	3608		T3	4600
valid_sources[0x32]	1258294	1			T1	60		T2	3355		T3	4501
valid_sources[0x33]	1254801	1			T1	64		T2	3566		T3	4689
valid_sources[0x34]	1254424	1			T1	82		T2	3792		T3	4553
valid_sources[0x35]	1263820	1			T1	61		T2	3565		T3	4730
valid_sources[0x36]	1460062	1			T1	85		T2	3382		T3	4646
valid_sources[0x37]	2459355	1			T1	67		T2	3589		T3	4682
valid_sources[0x38]	1256673	1			T1	44		T2	3530		T3	4678
valid_sources[0x39]	1255909	1			T1	46		T2	3489		T3	4631
valid_sources[0x3a]	1364831	1			T1	69		T2	3374		T3	4518
valid_sources[0x3b]	1258241	1			T1	61		T2	3444		T3	4459
valid_sources[0x3c]	1330742	1			T1	59		T2	3456		T3	4558
valid_sources[0x3d]	3241608	1			T1	47		T2	3875		T3	4736
valid_sources[0x3e]	3590736	1			T1	37		T2	3969		T3	4714
valid_sources[0x3f]	1248201	1			T1	51		T2	3463		T3	4688
valid_sources[0x40]	3596214	1			T1	74		T2	3524		T3	4681
valid_sources[0x41]	1384983	1			T1	86		T2	3589		T3	4640
valid_sources[0x42]	1365882	1			T1	77		T2	3604		T3	4599
valid_sources[0x43]	1254287	1			T1	53		T2	3355		T3	4598
valid_sources[0x44]	1251849	1			T1	52		T2	3464		T3	4643
valid_sources[0x45]	2106948	1			T1	66		T2	3407		T3	4690
valid_sources[0x46]	3295586	1			T1	71		T2	3491		T3	4499
valid_sources[0x47]	1248359	1			T1	46		T2	3530		T3	4531
valid_sources[0x48]	1253265	1			T1	42		T2	3648		T3	4624
valid_sources[0x49]	1692148	1			T1	44		T2	3432		T3	4645
valid_sources[0x4a]	1253441	1			T1	44		T2	3746		T3	4597
valid_sources[0x4b]	1247731	1			T1	66		T2	3358		T3	4687
valid_sources[0x4c]	1252455	1			T1	58		T2	3629		T3	4695
valid_sources[0x4d]	1256452	1			T1	88		T2	3603		T3	4496
valid_sources[0x4e]	1911389	1			T1	74		T2	3734		T3	4791
valid_sources[0x4f]	1400281	1			T1	67		T2	3647		T3	4756
valid_sources[0x50]	1317592	1			T1	71		T2	3434		T3	4656
valid_sources[0x51]	1251607	1			T1	55		T2	3681		T3	4728
valid_sources[0x52]	1252197	1			T1	82		T2	3358		T3	4628
valid_sources[0x53]	1253506	1			T1	40		T2	3705		T3	4601
valid_sources[0x54]	1248868	1			T1	44		T2	3729		T3	4633
valid_sources[0x55]	4506768	1			T1	59		T2	3419		T3	4585
valid_sources[0x56]	1249799	1			T1	70		T2	3420		T3	4581
valid_sources[0x57]	3206045	1			T1	88		T2	3550		T3	4599
valid_sources[0x58]	1248296	1			T1	72		T2	3523		T3	4549
valid_sources[0x59]	1255572	1			T1	54		T2	3468		T3	4574
valid_sources[0x5a]	1250534	1			T1	66		T2	3802		T3	4717
valid_sources[0x5b]	3633316	1			T1	59		T2	3476		T3	4611
valid_sources[0x5c]	1254453	1			T1	53		T2	3529		T3	4639
valid_sources[0x5d]	1254803	1			T1	42		T2	3561		T3	4658
valid_sources[0x5e]	1252290	1			T1	53		T2	3620		T3	4607
valid_sources[0x5f]	1253450	1			T1	70		T2	3434		T3	4732
valid_sources[0x60]	1252144	1			T1	65		T2	3580		T3	4610
valid_sources[0x61]	3748999	1			T1	71		T2	3557		T3	4661
valid_sources[0x62]	3186835	1			T1	52		T2	3324		T3	4636
valid_sources[0x63]	1261839	1			T1	42		T2	3718		T3	4547
valid_sources[0x64]	2122502	1			T1	44		T2	3705		T3	4681
valid_sources[0x65]	1253967	1			T1	82		T2	3524		T3	4600
valid_sources[0x66]	3577812	1			T1	51		T2	3573		T3	4611
valid_sources[0x67]	1391077	1			T1	69		T2	3736		T3	4543
valid_sources[0x68]	3213762	1			T1	55		T2	3791		T3	4649
valid_sources[0x69]	2115262	1			T1	43		T2	3830		T3	4609
valid_sources[0x6a]	5466669	1			T1	58		T2	3760		T3	4589
valid_sources[0x6b]	1252905	1			T1	54		T2	3447		T3	4682
valid_sources[0x6c]	1254888	1			T1	31		T2	3730		T3	4586
valid_sources[0x6d]	1255399	1			T1	66		T2	3526		T3	4464
valid_sources[0x6e]	2125050	1			T1	54		T2	3561		T3	4721
valid_sources[0x6f]	2533222	1			T1	82		T2	3662		T3	4673
valid_sources[0x70]	2153069	1			T1	77		T2	3375		T3	4812
valid_sources[0x71]	1256908	1			T1	67		T2	3692		T3	4663
valid_sources[0x72]	1254469	1			T1	46		T2	3559		T3	4535
valid_sources[0x73]	1679664	1			T1	59		T2	3483		T3	4754
valid_sources[0x74]	1708847	1			T1	67		T2	3499		T3	4666
valid_sources[0x75]	1254790	1			T1	44		T2	3606		T3	4582
valid_sources[0x76]	1297402	1			T1	77		T2	3584		T3	4679
valid_sources[0x77]	3225271	1			T1	54		T2	3691		T3	4706
valid_sources[0x78]	1267983	1			T1	57		T2	3733		T3	4578
valid_sources[0x79]	1246575	1			T1	62		T2	3426		T3	4436
valid_sources[0x7a]	1718138	1			T1	55		T2	3493		T3	4534
valid_sources[0x7b]	1424596	1			T1	83		T2	3412		T3	4697
valid_sources[0x7c]	3346342	1			T1	70		T2	3384		T3	4798
valid_sources[0x7d]	1428947	1			T1	54		T2	3505		T3	4603
valid_sources[0x7e]	1254865	1			T1	73		T2	3497		T3	4562
valid_sources[0x7f]	1257435	1			T1	56		T2	3529		T3	4599
valid_sources[0x80]	2149255	1			T1	43		T2	3689		T3	4548

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72184669

1

T1

6354

T2

118276

T3

191569

values[0x0]

all_enables

biggest_size

61448550

1

T1

1595

T2

122455

T3

153835

values[0x1]

all_enables

biggest_size

52932413

1

T1

1432

T2

104361

T3

132031