Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

260586533

1

T1

5895

T2

563787

T3

707878

full_word

186619597

1

T1

9381

T2

345092

T3

477435

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	447205810	1			T1	15276		T2	908879		T3	118531
auto[TlIntgErrCmd]	114	1			T127	8		T141	3		T142	5
auto[TlIntgErrData]	114	1			T141	4		T188	10		T189	4
auto[TlIntgErrBoth]	92	1			T127	2		T141	3		T142	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230700517

1

T1

10246

T2

454319

T3

631645

auto[1]

216505613

1

T1

5030

T2

454560

T3

553668

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158502402	1			T1	3892		T2	336043		T3	440076
auto[TlIntgErrNone]	partial	auto[1]	102083837	1			T1	2003		T2	227744		T3	267802
auto[TlIntgErrNone]	full_word	auto[0]	72197961	1			T1	6354		T2	118276		T3	191569
auto[TlIntgErrNone]	full_word	auto[1]	114421610	1			T1	3027		T2	226816		T3	285866
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T127	3		T141	1		T142	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T127	4		T141	1		T142	4
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T127	1		T141	1		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T191	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T141	2		T188	4		T189	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T141	2		T188	5		T189	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T188	1		T185	1		T186	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T189	1		T185	1		T191	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T127	1		T141	1		T142	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T127	1		T141	2		T142	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T185	1		T187	2		T191	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T142	1		T192	1		T193	1