Module Definition
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Module : prim_dom_and_2share
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom 100.00 100.00 100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom 100.00 100.00 100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom 100.00 100.00 100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom 100.00 100.00 100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom 100.00 100.00 100.00


Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.37 100.00 98.75 98.73 100.00 u_keccak_p


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_inner_domain_regs.u_prim_flop_tab01 100.00 100.00 100.00
u_prim_flop_t01 100.00 100.00 100.00
u_prim_xor_q01 100.00 100.00
u_prim_xor_t01 100.00 100.00


Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.37 100.00 98.75 98.73 100.00 u_keccak_p


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_inner_domain_regs.u_prim_flop_tab01 100.00 100.00 100.00
u_prim_flop_t01 100.00 100.00 100.00
u_prim_xor_q01 100.00 100.00
u_prim_xor_t01 100.00 100.00


Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.37 100.00 98.75 98.73 100.00 u_keccak_p


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_inner_domain_regs.u_prim_flop_tab01 100.00 100.00 100.00
u_prim_flop_t01 100.00 100.00 100.00
u_prim_xor_q01 100.00 100.00
u_prim_xor_t01 100.00 100.00


Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.37 100.00 98.75 98.73 100.00 u_keccak_p


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_inner_domain_regs.u_prim_flop_tab01 100.00 100.00 100.00
u_prim_flop_t01 100.00 100.00 100.00
u_prim_xor_q01 100.00 100.00
u_prim_xor_t01 100.00 100.00


Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.37 100.00 98.75 98.73 100.00 u_keccak_p


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_inner_domain_regs.u_prim_flop_tab01 100.00 100.00 100.00
u_prim_flop_t01 100.00 100.00 100.00
u_prim_xor_q01 100.00 100.00
u_prim_xor_t01 100.00 100.00

Line Coverage for Module : prim_dom_and_2share
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1

Assert Coverage for Module : prim_dom_and_2share
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 775116845 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 775116845 0 0
T1 912805 37680 0 0
T2 4885620 1330080 0 0
T3 1235150 1768320 0 0
T4 513715 9360 0 0
T7 848995 67440 0 0
T33 1557095 2116320 0 0
T34 3167310 1326240 0 0
T35 3050520 1326240 0 0
T36 736550 1310880 0 0
T37 854830 1174560 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 155023369 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155023369 0 0
T1 182561 7536 0 0
T2 977124 266016 0 0
T3 247030 353664 0 0
T4 102743 1872 0 0
T7 169799 13488 0 0
T33 311419 423264 0 0
T34 633462 265248 0 0
T35 610104 265248 0 0
T36 147310 262176 0 0
T37 170966 234912 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 155023369 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155023369 0 0
T1 182561 7536 0 0
T2 977124 266016 0 0
T3 247030 353664 0 0
T4 102743 1872 0 0
T7 169799 13488 0 0
T33 311419 423264 0 0
T34 633462 265248 0 0
T35 610104 265248 0 0
T36 147310 262176 0 0
T37 170966 234912 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 155023369 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155023369 0 0
T1 182561 7536 0 0
T2 977124 266016 0 0
T3 247030 353664 0 0
T4 102743 1872 0 0
T7 169799 13488 0 0
T33 311419 423264 0 0
T34 633462 265248 0 0
T35 610104 265248 0 0
T36 147310 262176 0 0
T37 170966 234912 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 155023369 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155023369 0 0
T1 182561 7536 0 0
T2 977124 266016 0 0
T3 247030 353664 0 0
T4 102743 1872 0 0
T7 169799 13488 0 0
T33 311419 423264 0 0
T34 633462 265248 0 0
T35 610104 265248 0 0
T36 147310 262176 0 0
T37 170966 234912 0 0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN14211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
60 1 1
61 1 1
110 1 1
111 1 1
142 1 1

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
UnmaskedAndMatched_A 2147483647 155023369 0 0


UnmaskedAndMatched_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155023369 0 0
T1 182561 7536 0 0
T2 977124 266016 0 0
T3 247030 353664 0 0
T4 102743 1872 0 0
T7 169799 13488 0 0
T33 311419 423264 0 0
T34 633462 265248 0 0
T35 610104 265248 0 0
T36 147310 262176 0 0
T37 170966 234912 0 0

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