Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	201893	0	0
entropy_period_rd_A	2147483647	2043	0	0
intr_enable_rd_A	2147483647	3081	0	0
prefix_0_rd_A	2147483647	2450	0	0
prefix_10_rd_A	2147483647	2588	0	0
prefix_1_rd_A	2147483647	2559	0	0
prefix_2_rd_A	2147483647	2532	0	0
prefix_3_rd_A	2147483647	2391	0	0
prefix_4_rd_A	2147483647	2455	0	0
prefix_5_rd_A	2147483647	2394	0	0
prefix_6_rd_A	2147483647	2438	0	0
prefix_7_rd_A	2147483647	2492	0	0
prefix_8_rd_A	2147483647	2494	0	0
prefix_9_rd_A	2147483647	2518	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	201893	0	0
T13	2842	0	0	0
T44	257502	33981	0	0
T45	0	164764	0	0
T113	998790	0	0	0
T126	1289	0	0	0
T127	0	1	0	0
T140	0	58	0	0
T141	0	1	0	0
T143	0	225	0	0
T147	0	189	0	0
T148	0	113	0	0
T149	0	101	0	0
T150	0	5	0	0
T151	426403	0	0	0
T152	150425	0	0	0
T153	129018	0	0	0
T154	480856	0	0	0
T155	18809	0	0	0
T156	399608	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2043	0	0
T99	6892	21	0	0
T108	5399	30	0	0
T142	10643	53	0	0
T150	8869	24	0	0
T157	4724	14	0	0
T169	143071	252	0	0
T170	4817	19	0	0
T171	11814	55	0	0
T172	48170	434	0	0
T173	5968	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3081	0	0
T99	6892	16	0	0
T144	876	13	0	0
T145	1213	24	0	0
T150	8869	33	0	0
T169	143071	440	0	0
T170	4817	7	0	0
T174	1159	10	0	0
T175	1391	19	0	0
T176	1383	6	0	0
T177	1807	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2450	0	0
T99	6892	8	0	0
T108	5399	20	0	0
T140	5671	4	0	0
T142	10643	25	0	0
T150	8869	21	0	0
T157	4724	3	0	0
T169	143071	412	0	0
T171	11814	61	0	0
T172	48170	391	0	0
T177	1807	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2588	0	0
T99	6892	4	0	0
T108	5399	24	0	0
T142	10643	30	0	0
T147	10621	1	0	0
T150	8869	19	0	0
T157	4724	5	0	0
T169	143071	434	0	0
T170	4817	19	0	0
T171	11814	63	0	0
T177	1807	1	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2559	0	0
T99	6892	26	0	0
T108	5399	10	0	0
T142	10643	28	0	0
T150	8869	18	0	0
T157	4724	2	0	0
T169	143071	452	0	0
T170	4817	17	0	0
T171	11814	54	0	0
T172	48170	442	0	0
T177	1807	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2532	0	0
T99	6892	22	0	0
T108	5399	19	0	0
T142	10643	35	0	0
T150	8869	20	0	0
T157	4724	5	0	0
T169	143071	401	0	0
T170	4817	24	0	0
T171	11814	52	0	0
T172	48170	383	0	0
T177	1807	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2391	0	0
T99	6892	15	0	0
T108	5399	21	0	0
T142	10643	30	0	0
T150	8869	27	0	0
T169	143071	424	0	0
T170	4817	20	0	0
T171	11814	23	0	0
T172	48170	445	0	0
T173	5968	13	0	0
T177	1807	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2455	0	0
T99	6892	20	0	0
T140	5671	9	0	0
T142	10643	9	0	0
T147	10621	10	0	0
T150	8869	5	0	0
T157	4724	2	0	0
T169	143071	431	0	0
T170	4817	28	0	0
T171	11814	101	0	0
T177	1807	1	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2394	0	0
T99	6892	9	0	0
T108	5399	25	0	0
T142	10643	23	0	0
T147	10621	9	0	0
T150	8869	9	0	0
T157	4724	1	0	0
T169	143071	488	0	0
T170	4817	21	0	0
T171	11814	22	0	0
T177	1807	9	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2438	0	0
T99	6892	21	0	0
T108	5399	30	0	0
T142	10643	1	0	0
T149	7800	4	0	0
T150	8869	16	0	0
T157	4724	8	0	0
T169	143071	432	0	0
T171	11814	52	0	0
T172	48170	437	0	0
T177	1807	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2492	0	0
T99	6892	25	0	0
T108	5399	25	0	0
T142	10643	14	0	0
T150	8869	4	0	0
T157	4724	5	0	0
T169	143071	393	0	0
T170	4817	7	0	0
T171	11814	38	0	0
T172	48170	473	0	0
T173	5968	15	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2494	0	0
T99	6892	16	0	0
T108	5399	28	0	0
T142	10643	8	0	0
T150	8869	16	0	0
T169	143071	431	0	0
T170	4817	15	0	0
T171	11814	51	0	0
T172	48170	474	0	0
T173	5968	4	0	0
T177	1807	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2518	0	0
T99	6892	13	0	0
T108	5399	20	0	0
T142	10643	17	0	0
T150	8869	27	0	0
T157	4724	1	0	0
T169	143071	477	0	0
T170	4817	21	0	0
T171	11814	39	0	0
T172	48170	422	0	0
T177	1807	5	0	0