Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99561705	1			T1	3		T3	7013		T15	270069
all_values[1]	99561705	1			T1	3		T3	7013		T15	270069
all_values[2]	99561705	1			T1	3		T3	7013		T15	270069

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

542289

1

T1

3

T3

30

T15

10624

auto[1]

298142826

1

T1

6

T3

21009

T15

799583

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297165819

1

T1

9

T3

20751

T15

809418

auto[1]

1519296

1

T3

288

T15

789

T18

1410

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	183889	1			T1	3		T3	1		T15	3245
all_values[0]	auto[0]	auto[1]	2060	1			T15	2		T34	2		T41	4
all_values[0]	auto[1]	auto[0]	98871384	1			T3	6916		T15	266561		T18	159386
all_values[0]	auto[1]	auto[1]	504372	1			T3	96		T15	261		T18	470
all_values[1]	auto[0]	auto[0]	179822	1			T3	28		T15	7370		T18	9
all_values[1]	auto[0]	auto[1]	1568	1			T3	1		T15	7		T18	6
all_values[1]	auto[1]	auto[0]	98875451	1			T1	3		T3	6889		T15	262436
all_values[1]	auto[1]	auto[1]	504864	1			T3	95		T15	256		T18	464
all_values[2]	auto[0]	auto[0]	173452	1			T18	2		T33	2		T34	1
all_values[2]	auto[0]	auto[1]	1498	1			T18	1		T33	1		T34	2
all_values[2]	auto[1]	auto[0]	98881821	1			T1	3		T3	6917		T15	269806
all_values[2]	auto[1]	auto[1]	504934	1			T3	96		T15	263		T18	469