Total Groups Coverage Summary 

COVERED	EXPECTED	SCORE	COVERED	EXPECTED	INST SCORE	WEIGHT
690	706	97.73	690	706	97.73	1

Total groups in report: 32

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NAME	COVERED	EXPECTED	SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING	COMMENT
tl_agent_pkg::pending_req_on_rst_cg	1	2	50.00	50.00	1	100	1	1	64	64
kmac_env_pkg::kmac_env_cov::error_cg	26	29	89.66		1	100	1	0	64	64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}	25	27	92.59		1	100	1	0	64	64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg	13	14	92.86	92.86	1	100	1	1	64	64
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg	14	15	93.33	93.33	1	100	1	1	64	64
kmac_env_pkg::app_cg_wrap::app_cg	17	18	94.44	90.74	1	100	1	1	64	64
kmac_env_pkg::config_masked_cg	31	32	96.88		1	100	1	0	64	64
alert_esc_agent_pkg::alert_handshake_complete_cg	3	3	100.00	100.00	1	100	1	1	64	64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}	19	19	100.00		1	100	1	0	64	64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}	19	19	100.00		1	100	1	0	64	64
cip_base_pkg::resets_cg	4	4	100.00	100.00	1	100	1	1	64	64
cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg	24	24	100.00	100.00	1	100	1	1	64	64
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg	2	2	100.00	98.31	1	100	1	1	64	64
dv_base_reg_pkg::dv_base_shadowed_field_cov::shadow_field_errs_cg	2	2	100.00	100.00	1	100	1	1	64	64
dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg	6	6	100.00	100.00	1	100	1	1	64	64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg	4	4	100.00	100.00	1	100	1	1	64	64
tb.dut.kmac_cov_if::cmd_process_cg	7	7	100.00		1	100	1	0	64	64
kmac_env_pkg::app_cg_wrap::app_cfg_reg_cg	3	3	100.00	100.00	1	100	1	1	64	64
kmac_env_pkg::kmac_env_cov::entropy_timer_cg	26	26	100.00		1	100	1	0	64	64
kmac_env_pkg::kmac_env_cov::msg_len_cg	15	15	100.00		1	100	1	0	64	64
kmac_env_pkg::kmac_env_cov::msgfifo_level_cg	20	20	100.00		1	100	1	0	64	64
kmac_env_pkg::kmac_env_cov::msgfifo_write_mask_cg	4	4	100.00		1	100	1	0	64	64
kmac_env_pkg::kmac_env_cov::output_digest_len_cg	14	14	100.00		1	100	1	0	64	64
kmac_env_pkg::kmac_env_cov::prefix_range_cg	3	3	100.00		1	100	1	0	64	64
kmac_env_pkg::kmac_env_cov::sha3_status_cg	6	6	100.00		1	100	1	0	64	64
kmac_env_pkg::kmac_env_cov::sideload_cg	10	10	100.00		1	100	1	0	64	64
kmac_env_pkg::kmac_env_cov::state_read_mask_cg	14	14	100.00		1	100	1	0	64	64
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg	2	2	100.00	100.00	1	100	1	1	64	64
push_pull_agent_pkg::req_ack_cg	3	3	100.00	100.00	1	100	1	1	64	64
push_pull_agent_pkg::valid_ready_cg	4	4	100.00	100.00	1	100	1	1	64	64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1}	1	1	100.00	100.00	1	100	1	1	64	64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}	137	137	100.00	100.00	1	100	1	1	64	64