Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
309716 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
188 |
auto[1] |
378370 |
1 |
|
|
T33 |
778 |
|
T41 |
490 |
|
T31 |
248 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172470 |
1 |
|
|
T1 |
1 |
|
T3 |
66 |
|
T15 |
77 |
lower_val |
169968 |
1 |
|
|
T3 |
42 |
|
T15 |
96 |
|
T18 |
129 |
zero_val |
1780 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
249378 |
1 |
|
|
T1 |
2 |
|
T3 |
94 |
|
T15 |
158 |
lower_val |
249574 |
1 |
|
|
T3 |
94 |
|
T15 |
198 |
|
T18 |
302 |
zero_val |
189134 |
1 |
|
|
T2 |
2 |
|
T33 |
418 |
|
T41 |
228 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
38409 |
1 |
|
|
T1 |
1 |
|
T3 |
33 |
|
T15 |
27 |
higher_val |
higher_val |
auto[1] |
23925 |
1 |
|
|
T33 |
51 |
|
T41 |
38 |
|
T31 |
11 |
higher_val |
lower_val |
auto[0] |
38961 |
1 |
|
|
T3 |
33 |
|
T15 |
50 |
|
T18 |
92 |
higher_val |
lower_val |
auto[1] |
23726 |
1 |
|
|
T33 |
39 |
|
T41 |
26 |
|
T31 |
18 |
higher_val |
zero_val |
auto[0] |
61 |
1 |
|
|
T7 |
1 |
|
T194 |
1 |
|
T195 |
1 |
higher_val |
zero_val |
auto[1] |
47388 |
1 |
|
|
T33 |
105 |
|
T41 |
64 |
|
T31 |
40 |
lower_val |
higher_val |
auto[0] |
38064 |
1 |
|
|
T3 |
21 |
|
T15 |
48 |
|
T18 |
68 |
lower_val |
higher_val |
auto[1] |
23606 |
1 |
|
|
T33 |
50 |
|
T41 |
35 |
|
T31 |
14 |
lower_val |
lower_val |
auto[0] |
37964 |
1 |
|
|
T3 |
21 |
|
T15 |
48 |
|
T18 |
61 |
lower_val |
lower_val |
auto[1] |
23723 |
1 |
|
|
T33 |
50 |
|
T41 |
30 |
|
T31 |
17 |
lower_val |
zero_val |
auto[0] |
78 |
1 |
|
|
T30 |
1 |
|
T94 |
1 |
|
T152 |
1 |
lower_val |
zero_val |
auto[1] |
46533 |
1 |
|
|
T33 |
100 |
|
T41 |
61 |
|
T31 |
39 |
zero_val |
higher_val |
auto[0] |
542 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
3 |
zero_val |
higher_val |
auto[1] |
128 |
1 |
|
|
T92 |
2 |
|
T196 |
1 |
|
T197 |
1 |
zero_val |
lower_val |
auto[0] |
552 |
1 |
|
|
T3 |
1 |
|
T33 |
1 |
|
T41 |
1 |
zero_val |
lower_val |
auto[1] |
139 |
1 |
|
|
T92 |
1 |
|
T196 |
2 |
|
T13 |
1 |
zero_val |
zero_val |
auto[0] |
229 |
1 |
|
|
T2 |
1 |
|
T30 |
1 |
|
T58 |
1 |
zero_val |
zero_val |
auto[1] |
190 |
1 |
|
|
T92 |
1 |
|
T196 |
1 |
|
T197 |
1 |