Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99561705	1			T1	3		T3	7013		T15	270069
all_pins[1]	99561705	1			T1	3		T3	7013		T15	270069
all_pins[2]	99561705	1			T1	3		T3	7013		T15	270069

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297894275	1			T1	9		T3	13979		T15	809946
values[0x1]	790840	1			T3	7060		T15	261		T18	470
transitions[0x0=>0x1]	788877	1			T3	6985		T15	261		T18	470
transitions[0x1=>0x0]	788905	1			T3	6986		T15	261		T18	470

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99057333	1			T1	3		T3	6917		T15	269808
all_pins[0]	values[0x1]	504372	1			T3	96		T15	261		T18	470
all_pins[0]	transitions[0x0=>0x1]	504358	1			T3	96		T15	261		T18	470
all_pins[0]	transitions[0x1=>0x0]	5711	1			T3	13		T32	27		T31	55
all_pins[1]	values[0x0]	99555980	1			T1	3		T3	7000		T15	270069
all_pins[1]	values[0x1]	5725	1			T3	13		T32	27		T31	55
all_pins[1]	transitions[0x0=>0x1]	5467	1			T32	27		T31	55		T60	1
all_pins[1]	transitions[0x1=>0x0]	280485	1			T3	6938		T8	11		T13	3997
all_pins[2]	values[0x0]	99280962	1			T1	3		T3	62		T15	270069
all_pins[2]	values[0x1]	280743	1			T3	6951		T8	11		T13	4009
all_pins[2]	transitions[0x0=>0x1]	279052	1			T3	6889		T8	11		T13	3979
all_pins[2]	transitions[0x1=>0x0]	502709	1			T3	35		T15	261		T18	470