Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	605	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5153	1			T3	5		T15	24		T32	12
len_601_800	12101	1			T3	25		T15	80		T32	17
len_401_600	8047	1			T3	21		T15	33		T32	11
len_201_400	16256	1			T3	4		T15	12		T32	7
len_65_200	73530	1			T3	3		T15	13		T32	1
len_min_for_xof_require_squeeze	1011	1			T31	1		T80	10		T88	1
len_keccak_block_sizes[72]	748	1			T80	5		T58	1		T88	1
len_keccak_block_sizes[104]	753	1			T80	5		T87	1		T116	5
len_keccak_block_sizes[136]	755	1			T80	5		T58	1		T87	1
len_keccak_block_sizes[144]	278	1			T80	5		T116	5		T196	5
len_keccak_block_sizes[168]	283	1			T80	5		T116	5		T152	1
len_datapath_width	13716	1			T35	3		T41	246		T31	2
len_2_63	212975	1			T3	35		T15	10		T18	310
len_1	47	1			T15	1		T198	1		T194	3