Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 284 1 T135 4 T136 4 T174 4
all_values[1] 284 1 T135 4 T136 4 T174 4
all_values[2] 284 1 T135 4 T136 4 T174 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 457 1 T135 12 T136 6 T174 7
auto[1] 395 1 T136 6 T174 5 T175 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 380 1 T135 6 T136 3 T174 9
auto[1] 472 1 T135 6 T136 9 T174 3


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 504 1 T135 8 T136 7 T174 9
auto[1] 348 1 T135 4 T136 5 T174 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 57 1 T135 2 T174 1 T176 2
all_values[0] auto[0] auto[0] auto[1] 31 1 T135 1 T136 2 T177 1
all_values[0] auto[0] auto[1] auto[0] 47 1 T174 1 T175 1 T176 1
all_values[0] auto[0] auto[1] auto[1] 32 1 T175 2 T176 1 T177 1
all_values[0] auto[1] auto[0] auto[1] 71 1 T135 1 T136 2 T174 2
all_values[0] auto[1] auto[1] auto[1] 46 1 T175 1 T177 2 T178 2
all_values[1] auto[0] auto[0] auto[0] 89 1 T135 3 T136 1 T175 1
all_values[1] auto[0] auto[1] auto[0] 95 1 T136 2 T174 4 T175 2
all_values[1] auto[1] auto[0] auto[1] 57 1 T135 1 T176 1 T178 2
all_values[1] auto[1] auto[1] auto[1] 43 1 T136 1 T175 1 T176 1
all_values[2] auto[0] auto[0] auto[0] 48 1 T135 1 T174 3 T177 2
all_values[2] auto[0] auto[0] auto[1] 33 1 T135 1 T176 1 T178 2
all_values[2] auto[0] auto[1] auto[0] 44 1 T175 3 T176 2 T177 1
all_values[2] auto[0] auto[1] auto[1] 28 1 T136 2 T177 1 T178 1
all_values[2] auto[1] auto[0] auto[1] 71 1 T135 2 T136 1 T174 1
all_values[2] auto[1] auto[1] auto[1] 60 1 T136 1 T175 1 T176 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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