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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.38 97.89 92.58 99.89 78.17 95.53 98.89 97.73


Total test records in report: 1225
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T1051 /workspace/coverage/default/8.kmac_test_vectors_sha3_224.3334888695 Jul 01 12:09:03 PM PDT 24 Jul 01 12:50:52 PM PDT 24 107774413185 ps
T1052 /workspace/coverage/default/30.kmac_key_error.2288578714 Jul 01 12:19:02 PM PDT 24 Jul 01 12:19:14 PM PDT 24 3455847983 ps
T1053 /workspace/coverage/default/2.kmac_app.4236364007 Jul 01 12:06:35 PM PDT 24 Jul 01 12:10:29 PM PDT 24 32421188628 ps
T1054 /workspace/coverage/default/23.kmac_smoke.84280311 Jul 01 12:15:42 PM PDT 24 Jul 01 12:16:25 PM PDT 24 1758581723 ps
T1055 /workspace/coverage/default/26.kmac_burst_write.2505858426 Jul 01 12:16:53 PM PDT 24 Jul 01 12:22:32 PM PDT 24 9807069519 ps
T1056 /workspace/coverage/default/27.kmac_key_error.2580634869 Jul 01 12:17:38 PM PDT 24 Jul 01 12:17:41 PM PDT 24 165339486 ps
T1057 /workspace/coverage/default/1.kmac_entropy_refresh.3094910578 Jul 01 12:06:05 PM PDT 24 Jul 01 12:07:12 PM PDT 24 9078169275 ps
T1058 /workspace/coverage/default/20.kmac_lc_escalation.1425650857 Jul 01 12:14:44 PM PDT 24 Jul 01 12:14:46 PM PDT 24 39632093 ps
T1059 /workspace/coverage/default/48.kmac_test_vectors_sha3_256.149891632 Jul 01 12:27:01 PM PDT 24 Jul 01 01:02:16 PM PDT 24 80705499316 ps
T1060 /workspace/coverage/default/13.kmac_edn_timeout_error.2683392603 Jul 01 12:11:21 PM PDT 24 Jul 01 12:11:22 PM PDT 24 12423856 ps
T1061 /workspace/coverage/default/15.kmac_alert_test.529424473 Jul 01 12:12:18 PM PDT 24 Jul 01 12:12:19 PM PDT 24 11687419 ps
T1062 /workspace/coverage/default/32.kmac_burst_write.4161479166 Jul 01 12:19:37 PM PDT 24 Jul 01 12:22:25 PM PDT 24 6673063687 ps
T1063 /workspace/coverage/default/39.kmac_app.2990344155 Jul 01 12:22:59 PM PDT 24 Jul 01 12:30:39 PM PDT 24 92817832047 ps
T1064 /workspace/coverage/default/38.kmac_sideload.3345277598 Jul 01 12:22:19 PM PDT 24 Jul 01 12:22:28 PM PDT 24 1356344955 ps
T1065 /workspace/coverage/default/16.kmac_edn_timeout_error.1229677819 Jul 01 12:12:38 PM PDT 24 Jul 01 12:12:40 PM PDT 24 106001049 ps
T1066 /workspace/coverage/default/13.kmac_test_vectors_shake_128.2347432067 Jul 01 12:11:11 PM PDT 24 Jul 01 01:54:47 PM PDT 24 258791848251 ps
T1067 /workspace/coverage/default/33.kmac_long_msg_and_output.532015459 Jul 01 12:20:04 PM PDT 24 Jul 01 01:01:09 PM PDT 24 42386984391 ps
T96 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1246918804 Jul 01 10:45:47 AM PDT 24 Jul 01 10:45:51 AM PDT 24 34702760 ps
T134 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2374211657 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:47 AM PDT 24 71557765 ps
T139 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2818332166 Jul 01 10:46:22 AM PDT 24 Jul 01 10:46:24 AM PDT 24 23993907 ps
T97 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1554281002 Jul 01 10:45:50 AM PDT 24 Jul 01 10:45:53 AM PDT 24 64347524 ps
T140 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.58485170 Jul 01 10:45:26 AM PDT 24 Jul 01 10:45:28 AM PDT 24 63997049 ps
T141 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.1416393699 Jul 01 10:45:44 AM PDT 24 Jul 01 10:45:50 AM PDT 24 716718828 ps
T98 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.455193057 Jul 01 10:45:36 AM PDT 24 Jul 01 10:45:39 AM PDT 24 372819943 ps
T142 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2846086525 Jul 01 10:45:52 AM PDT 24 Jul 01 10:45:54 AM PDT 24 25229066 ps
T143 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.310396378 Jul 01 10:46:02 AM PDT 24 Jul 01 10:46:05 AM PDT 24 1157524748 ps
T108 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3421215983 Jul 01 10:45:56 AM PDT 24 Jul 01 10:45:59 AM PDT 24 145395676 ps
T151 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3525887006 Jul 01 10:45:50 AM PDT 24 Jul 01 10:45:53 AM PDT 24 50847372 ps
T102 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2130099684 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:49 AM PDT 24 199924360 ps
T166 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3301892941 Jul 01 10:45:35 AM PDT 24 Jul 01 10:45:37 AM PDT 24 149003426 ps
T167 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3767276574 Jul 01 10:46:28 AM PDT 24 Jul 01 10:46:35 AM PDT 24 114470734 ps
T1068 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1499667059 Jul 01 10:45:44 AM PDT 24 Jul 01 10:45:50 AM PDT 24 143780387 ps
T1069 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3416075878 Jul 01 10:45:49 AM PDT 24 Jul 01 10:45:52 AM PDT 24 31928585 ps
T130 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.679425343 Jul 01 10:45:26 AM PDT 24 Jul 01 10:45:31 AM PDT 24 761398393 ps
T1070 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.588546828 Jul 01 10:45:40 AM PDT 24 Jul 01 10:45:42 AM PDT 24 14912155 ps
T135 /workspace/coverage/cover_reg_top/8.kmac_intr_test.3629764894 Jul 01 10:46:30 AM PDT 24 Jul 01 10:46:32 AM PDT 24 47434705 ps
T131 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.722576321 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:47 AM PDT 24 241493249 ps
T136 /workspace/coverage/cover_reg_top/33.kmac_intr_test.1296394305 Jul 01 10:45:59 AM PDT 24 Jul 01 10:46:00 AM PDT 24 44051554 ps
T174 /workspace/coverage/cover_reg_top/22.kmac_intr_test.1401411810 Jul 01 10:46:03 AM PDT 24 Jul 01 10:46:04 AM PDT 24 12577931 ps
T168 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2061563071 Jul 01 10:45:45 AM PDT 24 Jul 01 10:45:50 AM PDT 24 33465382 ps
T175 /workspace/coverage/cover_reg_top/14.kmac_intr_test.3060587880 Jul 01 10:45:51 AM PDT 24 Jul 01 10:45:52 AM PDT 24 65898377 ps
T132 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3933897709 Jul 01 10:45:45 AM PDT 24 Jul 01 10:45:52 AM PDT 24 895461292 ps
T1071 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.2572978489 Jul 01 10:45:36 AM PDT 24 Jul 01 10:45:38 AM PDT 24 158816687 ps
T179 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1130224486 Jul 01 10:45:56 AM PDT 24 Jul 01 10:46:02 AM PDT 24 1271734204 ps
T1072 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.553724177 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:52 AM PDT 24 61202227 ps
T1073 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2501137209 Jul 01 10:46:13 AM PDT 24 Jul 01 10:46:16 AM PDT 24 154772622 ps
T153 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.640012672 Jul 01 10:45:44 AM PDT 24 Jul 01 10:45:50 AM PDT 24 150462722 ps
T176 /workspace/coverage/cover_reg_top/35.kmac_intr_test.923621986 Jul 01 10:45:59 AM PDT 24 Jul 01 10:46:00 AM PDT 24 22244189 ps
T177 /workspace/coverage/cover_reg_top/12.kmac_intr_test.2256411642 Jul 01 10:45:49 AM PDT 24 Jul 01 10:45:52 AM PDT 24 22743963 ps
T1074 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.4056459387 Jul 01 10:45:39 AM PDT 24 Jul 01 10:45:42 AM PDT 24 255303563 ps
T169 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3356514868 Jul 01 10:45:34 AM PDT 24 Jul 01 10:45:37 AM PDT 24 455112306 ps
T178 /workspace/coverage/cover_reg_top/9.kmac_intr_test.809981372 Jul 01 10:45:51 AM PDT 24 Jul 01 10:45:52 AM PDT 24 24527208 ps
T1075 /workspace/coverage/cover_reg_top/34.kmac_intr_test.2425233615 Jul 01 10:46:29 AM PDT 24 Jul 01 10:46:31 AM PDT 24 15574892 ps
T170 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3227390323 Jul 01 10:45:29 AM PDT 24 Jul 01 10:45:32 AM PDT 24 263340610 ps
T1076 /workspace/coverage/cover_reg_top/24.kmac_intr_test.2326380556 Jul 01 10:45:53 AM PDT 24 Jul 01 10:45:54 AM PDT 24 45126278 ps
T104 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2180531113 Jul 01 10:45:40 AM PDT 24 Jul 01 10:45:42 AM PDT 24 82659041 ps
T1077 /workspace/coverage/cover_reg_top/3.kmac_intr_test.3416029311 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:46 AM PDT 24 16426631 ps
T193 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1477555888 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:50 AM PDT 24 2323124297 ps
T1078 /workspace/coverage/cover_reg_top/36.kmac_intr_test.1993171314 Jul 01 10:45:57 AM PDT 24 Jul 01 10:45:58 AM PDT 24 46292366 ps
T1079 /workspace/coverage/cover_reg_top/11.kmac_intr_test.696287011 Jul 01 10:46:06 AM PDT 24 Jul 01 10:46:07 AM PDT 24 15859375 ps
T1080 /workspace/coverage/cover_reg_top/25.kmac_intr_test.1034387556 Jul 01 10:46:19 AM PDT 24 Jul 01 10:46:20 AM PDT 24 64195813 ps
T1081 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.3481270908 Jul 01 10:46:04 AM PDT 24 Jul 01 10:46:05 AM PDT 24 129282464 ps
T1082 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1676208655 Jul 01 10:46:16 AM PDT 24 Jul 01 10:46:18 AM PDT 24 26675542 ps
T1083 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1999919359 Jul 01 10:45:46 AM PDT 24 Jul 01 10:45:51 AM PDT 24 185819712 ps
T99 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.708009860 Jul 01 10:46:02 AM PDT 24 Jul 01 10:46:04 AM PDT 24 216273056 ps
T154 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2312747498 Jul 01 10:45:32 AM PDT 24 Jul 01 10:45:34 AM PDT 24 148195901 ps
T1084 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.542073558 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:49 AM PDT 24 32628888 ps
T180 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2964147087 Jul 01 10:46:09 AM PDT 24 Jul 01 10:46:16 AM PDT 24 344665007 ps
T1085 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1263172516 Jul 01 10:45:46 AM PDT 24 Jul 01 10:45:51 AM PDT 24 269464519 ps
T1086 /workspace/coverage/cover_reg_top/17.kmac_intr_test.466110448 Jul 01 10:46:15 AM PDT 24 Jul 01 10:46:16 AM PDT 24 18858447 ps
T101 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2058009281 Jul 01 10:46:03 AM PDT 24 Jul 01 10:46:04 AM PDT 24 17716974 ps
T1087 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.176389517 Jul 01 10:45:56 AM PDT 24 Jul 01 10:45:59 AM PDT 24 109582631 ps
T1088 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.2245270041 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:47 AM PDT 24 17558657 ps
T1089 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3157405653 Jul 01 10:45:46 AM PDT 24 Jul 01 10:45:50 AM PDT 24 29229018 ps
T1090 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.4026487655 Jul 01 10:45:43 AM PDT 24 Jul 01 10:46:02 AM PDT 24 1130958184 ps
T1091 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1651418821 Jul 01 10:45:51 AM PDT 24 Jul 01 10:45:54 AM PDT 24 107738093 ps
T181 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3863082499 Jul 01 10:45:55 AM PDT 24 Jul 01 10:45:58 AM PDT 24 100373836 ps
T100 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.359481664 Jul 01 10:45:52 AM PDT 24 Jul 01 10:45:55 AM PDT 24 82730909 ps
T1092 /workspace/coverage/cover_reg_top/42.kmac_intr_test.1360177828 Jul 01 10:46:33 AM PDT 24 Jul 01 10:46:37 AM PDT 24 10846108 ps
T1093 /workspace/coverage/cover_reg_top/32.kmac_intr_test.3908369137 Jul 01 10:46:09 AM PDT 24 Jul 01 10:46:10 AM PDT 24 32332956 ps
T1094 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.104961818 Jul 01 10:45:50 AM PDT 24 Jul 01 10:45:53 AM PDT 24 52147298 ps
T1095 /workspace/coverage/cover_reg_top/43.kmac_intr_test.3415336607 Jul 01 10:46:35 AM PDT 24 Jul 01 10:46:41 AM PDT 24 23539904 ps
T1096 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3948215968 Jul 01 10:45:49 AM PDT 24 Jul 01 10:45:53 AM PDT 24 75363200 ps
T1097 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1432324772 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:46 AM PDT 24 436695152 ps
T1098 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1911751499 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:47 AM PDT 24 66089827 ps
T103 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.500621944 Jul 01 10:45:55 AM PDT 24 Jul 01 10:45:56 AM PDT 24 29785757 ps
T1099 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.347346177 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:48 AM PDT 24 22329931 ps
T1100 /workspace/coverage/cover_reg_top/15.kmac_intr_test.3120304017 Jul 01 10:46:14 AM PDT 24 Jul 01 10:46:16 AM PDT 24 39518884 ps
T1101 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3660374324 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:48 AM PDT 24 57851433 ps
T182 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1045539316 Jul 01 10:45:55 AM PDT 24 Jul 01 10:45:58 AM PDT 24 631160810 ps
T1102 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3889910534 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:47 AM PDT 24 189659348 ps
T1103 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3957724027 Jul 01 10:45:56 AM PDT 24 Jul 01 10:45:59 AM PDT 24 180111250 ps
T1104 /workspace/coverage/cover_reg_top/38.kmac_intr_test.3694947273 Jul 01 10:46:15 AM PDT 24 Jul 01 10:46:16 AM PDT 24 79293804 ps
T1105 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2091705646 Jul 01 10:46:02 AM PDT 24 Jul 01 10:46:03 AM PDT 24 42066115 ps
T1106 /workspace/coverage/cover_reg_top/0.kmac_intr_test.2249706044 Jul 01 10:45:44 AM PDT 24 Jul 01 10:45:50 AM PDT 24 68799471 ps
T1107 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.4154441002 Jul 01 10:45:59 AM PDT 24 Jul 01 10:46:01 AM PDT 24 16627623 ps
T1108 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.884474229 Jul 01 10:45:32 AM PDT 24 Jul 01 10:45:34 AM PDT 24 160218712 ps
T1109 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3629449887 Jul 01 10:45:39 AM PDT 24 Jul 01 10:45:41 AM PDT 24 74030746 ps
T1110 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1654423733 Jul 01 10:45:54 AM PDT 24 Jul 01 10:45:55 AM PDT 24 413036527 ps
T1111 /workspace/coverage/cover_reg_top/45.kmac_intr_test.1903417395 Jul 01 10:46:00 AM PDT 24 Jul 01 10:46:02 AM PDT 24 13312571 ps
T1112 /workspace/coverage/cover_reg_top/6.kmac_intr_test.758856346 Jul 01 10:45:38 AM PDT 24 Jul 01 10:45:39 AM PDT 24 30888683 ps
T1113 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2746334634 Jul 01 10:46:14 AM PDT 24 Jul 01 10:46:18 AM PDT 24 149116241 ps
T1114 /workspace/coverage/cover_reg_top/39.kmac_intr_test.3120942885 Jul 01 10:46:26 AM PDT 24 Jul 01 10:46:27 AM PDT 24 28553063 ps
T1115 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.8230144 Jul 01 10:45:39 AM PDT 24 Jul 01 10:45:43 AM PDT 24 282664152 ps
T1116 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.260590814 Jul 01 10:45:51 AM PDT 24 Jul 01 10:45:54 AM PDT 24 80494126 ps
T1117 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2144967617 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:53 AM PDT 24 1159215228 ps
T1118 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1395228121 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:49 AM PDT 24 90561175 ps
T1119 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.17126869 Jul 01 10:45:30 AM PDT 24 Jul 01 10:45:32 AM PDT 24 59555772 ps
T1120 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.3236291040 Jul 01 10:46:03 AM PDT 24 Jul 01 10:46:05 AM PDT 24 99531737 ps
T192 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2835393302 Jul 01 10:46:16 AM PDT 24 Jul 01 10:46:20 AM PDT 24 144567637 ps
T1121 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1507160518 Jul 01 10:46:07 AM PDT 24 Jul 01 10:46:08 AM PDT 24 14463471 ps
T1122 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1650203558 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:55 AM PDT 24 148779630 ps
T1123 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.759931072 Jul 01 10:45:42 AM PDT 24 Jul 01 10:45:47 AM PDT 24 38948611 ps
T1124 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2616706613 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:48 AM PDT 24 130478446 ps
T190 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1785848672 Jul 01 10:45:53 AM PDT 24 Jul 01 10:45:58 AM PDT 24 1094617435 ps
T107 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1742220054 Jul 01 10:45:38 AM PDT 24 Jul 01 10:45:40 AM PDT 24 30658956 ps
T1125 /workspace/coverage/cover_reg_top/19.kmac_intr_test.4132752552 Jul 01 10:46:22 AM PDT 24 Jul 01 10:46:23 AM PDT 24 39024551 ps
T188 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2550037004 Jul 01 10:45:47 AM PDT 24 Jul 01 10:45:54 AM PDT 24 367297115 ps
T1126 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.967722212 Jul 01 10:46:15 AM PDT 24 Jul 01 10:46:18 AM PDT 24 396649282 ps
T1127 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1489920405 Jul 01 10:46:16 AM PDT 24 Jul 01 10:46:18 AM PDT 24 47871293 ps
T1128 /workspace/coverage/cover_reg_top/31.kmac_intr_test.3014091933 Jul 01 10:45:56 AM PDT 24 Jul 01 10:45:58 AM PDT 24 37922349 ps
T1129 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.2614573411 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:57 AM PDT 24 770696766 ps
T1130 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.3738840407 Jul 01 10:46:09 AM PDT 24 Jul 01 10:46:11 AM PDT 24 21040483 ps
T1131 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.4079165326 Jul 01 10:46:22 AM PDT 24 Jul 01 10:46:23 AM PDT 24 15766812 ps
T1132 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2011120355 Jul 01 10:45:53 AM PDT 24 Jul 01 10:45:55 AM PDT 24 97006782 ps
T1133 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1095736640 Jul 01 10:46:10 AM PDT 24 Jul 01 10:46:13 AM PDT 24 325625436 ps
T1134 /workspace/coverage/cover_reg_top/49.kmac_intr_test.3835432586 Jul 01 10:46:33 AM PDT 24 Jul 01 10:46:36 AM PDT 24 30597797 ps
T105 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.372298902 Jul 01 10:45:24 AM PDT 24 Jul 01 10:45:27 AM PDT 24 182402881 ps
T1135 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.119169078 Jul 01 10:45:31 AM PDT 24 Jul 01 10:45:33 AM PDT 24 41200821 ps
T1136 /workspace/coverage/cover_reg_top/5.kmac_intr_test.4149249433 Jul 01 10:46:05 AM PDT 24 Jul 01 10:46:06 AM PDT 24 27703882 ps
T1137 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.1818289826 Jul 01 10:46:02 AM PDT 24 Jul 01 10:46:06 AM PDT 24 295484258 ps
T1138 /workspace/coverage/cover_reg_top/20.kmac_intr_test.831049989 Jul 01 10:45:57 AM PDT 24 Jul 01 10:45:59 AM PDT 24 18010334 ps
T1139 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.830575479 Jul 01 10:45:41 AM PDT 24 Jul 01 10:46:00 AM PDT 24 1166755402 ps
T1140 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.8773386 Jul 01 10:45:49 AM PDT 24 Jul 01 10:45:54 AM PDT 24 392755315 ps
T1141 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.82917786 Jul 01 10:45:55 AM PDT 24 Jul 01 10:45:56 AM PDT 24 31945244 ps
T1142 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3334455815 Jul 01 10:45:47 AM PDT 24 Jul 01 10:45:52 AM PDT 24 125687463 ps
T1143 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3775130654 Jul 01 10:45:31 AM PDT 24 Jul 01 10:45:33 AM PDT 24 10767732 ps
T1144 /workspace/coverage/cover_reg_top/16.kmac_intr_test.3746244765 Jul 01 10:46:08 AM PDT 24 Jul 01 10:46:09 AM PDT 24 12484314 ps
T1145 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2558585311 Jul 01 10:46:11 AM PDT 24 Jul 01 10:46:15 AM PDT 24 92737124 ps
T1146 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2598980476 Jul 01 10:45:49 AM PDT 24 Jul 01 10:45:52 AM PDT 24 79525542 ps
T1147 /workspace/coverage/cover_reg_top/26.kmac_intr_test.934123388 Jul 01 10:46:11 AM PDT 24 Jul 01 10:46:13 AM PDT 24 21644747 ps
T1148 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2998535839 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:52 AM PDT 24 427283521 ps
T1149 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2897803251 Jul 01 10:45:44 AM PDT 24 Jul 01 10:45:50 AM PDT 24 59778911 ps
T1150 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2619196091 Jul 01 10:45:46 AM PDT 24 Jul 01 10:45:51 AM PDT 24 38246511 ps
T1151 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2363230272 Jul 01 10:45:58 AM PDT 24 Jul 01 10:45:59 AM PDT 24 26504187 ps
T1152 /workspace/coverage/cover_reg_top/21.kmac_intr_test.4270696953 Jul 01 10:45:55 AM PDT 24 Jul 01 10:45:56 AM PDT 24 14514004 ps
T106 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.923589794 Jul 01 10:45:26 AM PDT 24 Jul 01 10:45:28 AM PDT 24 70641589 ps
T1153 /workspace/coverage/cover_reg_top/27.kmac_intr_test.423747021 Jul 01 10:46:07 AM PDT 24 Jul 01 10:46:14 AM PDT 24 48280900 ps
T1154 /workspace/coverage/cover_reg_top/44.kmac_intr_test.1813629001 Jul 01 10:46:01 AM PDT 24 Jul 01 10:46:03 AM PDT 24 59220363 ps
T1155 /workspace/coverage/cover_reg_top/23.kmac_intr_test.170795188 Jul 01 10:46:31 AM PDT 24 Jul 01 10:46:32 AM PDT 24 14006216 ps
T1156 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2841684824 Jul 01 10:45:29 AM PDT 24 Jul 01 10:45:49 AM PDT 24 1946580409 ps
T1157 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3456222203 Jul 01 10:45:38 AM PDT 24 Jul 01 10:45:40 AM PDT 24 87626068 ps
T1158 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.658492006 Jul 01 10:45:49 AM PDT 24 Jul 01 10:45:54 AM PDT 24 49908220 ps
T189 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1707113839 Jul 01 10:45:37 AM PDT 24 Jul 01 10:45:41 AM PDT 24 450230721 ps
T1159 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3396557372 Jul 01 10:45:48 AM PDT 24 Jul 01 10:45:52 AM PDT 24 48516247 ps
T1160 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1004896491 Jul 01 10:45:51 AM PDT 24 Jul 01 10:45:53 AM PDT 24 161229988 ps
T155 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.498741528 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:46 AM PDT 24 130121517 ps
T156 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2222105969 Jul 01 10:45:34 AM PDT 24 Jul 01 10:45:35 AM PDT 24 73128440 ps
T1161 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2047178750 Jul 01 10:46:32 AM PDT 24 Jul 01 10:46:35 AM PDT 24 68243062 ps
T1162 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.4149416529 Jul 01 10:46:07 AM PDT 24 Jul 01 10:46:09 AM PDT 24 51141906 ps
T1163 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2019993383 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:45 AM PDT 24 60121339 ps
T1164 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2687420068 Jul 01 10:46:07 AM PDT 24 Jul 01 10:46:09 AM PDT 24 287351162 ps
T1165 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3909331872 Jul 01 10:46:09 AM PDT 24 Jul 01 10:46:10 AM PDT 24 16092003 ps
T1166 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.280248347 Jul 01 10:45:52 AM PDT 24 Jul 01 10:45:55 AM PDT 24 301975715 ps
T157 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3615366888 Jul 01 10:45:26 AM PDT 24 Jul 01 10:45:28 AM PDT 24 17992238 ps
T1167 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3215538449 Jul 01 10:46:00 AM PDT 24 Jul 01 10:46:04 AM PDT 24 44335396 ps
T1168 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.439772157 Jul 01 10:45:54 AM PDT 24 Jul 01 10:45:56 AM PDT 24 30928753 ps
T1169 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1380428673 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:47 AM PDT 24 121129769 ps
T1170 /workspace/coverage/cover_reg_top/18.kmac_intr_test.1393592283 Jul 01 10:46:21 AM PDT 24 Jul 01 10:46:22 AM PDT 24 15960203 ps
T1171 /workspace/coverage/cover_reg_top/41.kmac_intr_test.2346689780 Jul 01 10:46:29 AM PDT 24 Jul 01 10:46:30 AM PDT 24 52681101 ps
T1172 /workspace/coverage/cover_reg_top/37.kmac_intr_test.2100278759 Jul 01 10:46:20 AM PDT 24 Jul 01 10:46:21 AM PDT 24 73870163 ps
T1173 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.641770414 Jul 01 10:45:59 AM PDT 24 Jul 01 10:46:01 AM PDT 24 54158879 ps
T1174 /workspace/coverage/cover_reg_top/10.kmac_intr_test.946546078 Jul 01 10:46:09 AM PDT 24 Jul 01 10:46:10 AM PDT 24 38294276 ps
T1175 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3422987770 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:46 AM PDT 24 44312126 ps
T1176 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1582668316 Jul 01 10:45:51 AM PDT 24 Jul 01 10:45:52 AM PDT 24 26504736 ps
T1177 /workspace/coverage/cover_reg_top/13.kmac_intr_test.2408496964 Jul 01 10:45:49 AM PDT 24 Jul 01 10:45:51 AM PDT 24 42163649 ps
T1178 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.2719691685 Jul 01 10:45:45 AM PDT 24 Jul 01 10:45:50 AM PDT 24 34912259 ps
T1179 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.644158560 Jul 01 10:45:38 AM PDT 24 Jul 01 10:45:42 AM PDT 24 85655033 ps
T1180 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.269852050 Jul 01 10:45:38 AM PDT 24 Jul 01 10:45:39 AM PDT 24 110621397 ps
T1181 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2341684160 Jul 01 10:45:47 AM PDT 24 Jul 01 10:45:54 AM PDT 24 93412950 ps
T191 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3001956705 Jul 01 10:45:48 AM PDT 24 Jul 01 10:45:56 AM PDT 24 3398580684 ps
T1182 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2498878220 Jul 01 10:45:39 AM PDT 24 Jul 01 10:45:42 AM PDT 24 366074824 ps
T1183 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3592813006 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:48 AM PDT 24 13406301 ps
T1184 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.2787146241 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:46 AM PDT 24 83817082 ps
T1185 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2564149832 Jul 01 10:45:29 AM PDT 24 Jul 01 10:45:32 AM PDT 24 448085812 ps
T1186 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2187606596 Jul 01 10:46:04 AM PDT 24 Jul 01 10:46:07 AM PDT 24 36248160 ps
T1187 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3456822378 Jul 01 10:45:35 AM PDT 24 Jul 01 10:45:44 AM PDT 24 791210105 ps
T1188 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2221576272 Jul 01 10:46:28 AM PDT 24 Jul 01 10:46:33 AM PDT 24 1016165241 ps
T1189 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2435640710 Jul 01 10:46:00 AM PDT 24 Jul 01 10:46:03 AM PDT 24 785642921 ps
T1190 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.4107683897 Jul 01 10:45:45 AM PDT 24 Jul 01 10:45:50 AM PDT 24 105664840 ps
T1191 /workspace/coverage/cover_reg_top/48.kmac_intr_test.159119357 Jul 01 10:46:34 AM PDT 24 Jul 01 10:46:39 AM PDT 24 42329827 ps
T1192 /workspace/coverage/cover_reg_top/40.kmac_intr_test.2917840473 Jul 01 10:46:04 AM PDT 24 Jul 01 10:46:06 AM PDT 24 13956402 ps
T1193 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.591396934 Jul 01 10:45:37 AM PDT 24 Jul 01 10:45:47 AM PDT 24 2002921656 ps
T1194 /workspace/coverage/cover_reg_top/7.kmac_intr_test.1489406038 Jul 01 10:45:41 AM PDT 24 Jul 01 10:45:45 AM PDT 24 104362070 ps
T1195 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.827068640 Jul 01 10:45:44 AM PDT 24 Jul 01 10:46:04 AM PDT 24 292952900 ps
T1196 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2035905373 Jul 01 10:46:04 AM PDT 24 Jul 01 10:46:07 AM PDT 24 155374179 ps
T1197 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1360697355 Jul 01 10:45:49 AM PDT 24 Jul 01 10:45:52 AM PDT 24 77744694 ps
T1198 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.623950432 Jul 01 10:46:25 AM PDT 24 Jul 01 10:46:27 AM PDT 24 130226311 ps
T1199 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2284091803 Jul 01 10:46:13 AM PDT 24 Jul 01 10:46:16 AM PDT 24 74031220 ps
T1200 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1931944741 Jul 01 10:45:43 AM PDT 24 Jul 01 10:45:48 AM PDT 24 13933871 ps
T1201 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.721227805 Jul 01 10:45:50 AM PDT 24 Jul 01 10:45:53 AM PDT 24 79165063 ps
T1202 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2933978180 Jul 01 10:45:44 AM PDT 24 Jul 01 10:45:50 AM PDT 24 51366572 ps
T1203 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1956609146 Jul 01 10:46:25 AM PDT 24 Jul 01 10:46:28 AM PDT 24 236994047 ps
T1204 /workspace/coverage/cover_reg_top/2.kmac_intr_test.2696705868 Jul 01 10:45:38 AM PDT 24 Jul 01 10:45:40 AM PDT 24 34391343 ps
T1205 /workspace/coverage/cover_reg_top/29.kmac_intr_test.878926718 Jul 01 10:46:08 AM PDT 24 Jul 01 10:46:09 AM PDT 24 64044616 ps
T1206 /workspace/coverage/cover_reg_top/46.kmac_intr_test.2964552097 Jul 01 10:46:03 AM PDT 24 Jul 01 10:46:05 AM PDT 24 18002173 ps
T1207 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3475802618 Jul 01 10:45:40 AM PDT 24 Jul 01 10:45:44 AM PDT 24 36108721 ps
T1208 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3898133796 Jul 01 10:45:50 AM PDT 24 Jul 01 10:45:53 AM PDT 24 72591342 ps
T1209 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2286760086 Jul 01 10:46:15 AM PDT 24 Jul 01 10:46:17 AM PDT 24 58218406 ps
T1210 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3021337094 Jul 01 10:45:47 AM PDT 24 Jul 01 10:45:51 AM PDT 24 29218257 ps
T1211 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3748974369 Jul 01 10:45:49 AM PDT 24 Jul 01 10:45:52 AM PDT 24 56295178 ps
T1212 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3528571580 Jul 01 10:46:12 AM PDT 24 Jul 01 10:46:15 AM PDT 24 105858066 ps
T1213 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3433548894 Jul 01 10:46:14 AM PDT 24 Jul 01 10:46:17 AM PDT 24 70746979 ps
T1214 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.86211106 Jul 01 10:46:25 AM PDT 24 Jul 01 10:46:28 AM PDT 24 75862949 ps
T1215 /workspace/coverage/cover_reg_top/30.kmac_intr_test.1359724455 Jul 01 10:46:30 AM PDT 24 Jul 01 10:46:31 AM PDT 24 12928428 ps
T1216 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2483226661 Jul 01 10:45:30 AM PDT 24 Jul 01 10:45:46 AM PDT 24 397495839 ps
T1217 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2902281952 Jul 01 10:46:15 AM PDT 24 Jul 01 10:46:19 AM PDT 24 427423526 ps
T1218 /workspace/coverage/cover_reg_top/28.kmac_intr_test.1264515714 Jul 01 10:46:03 AM PDT 24 Jul 01 10:46:04 AM PDT 24 13726680 ps
T1219 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2559206368 Jul 01 10:45:25 AM PDT 24 Jul 01 10:45:26 AM PDT 24 77381653 ps
T1220 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2672037820 Jul 01 10:46:09 AM PDT 24 Jul 01 10:46:12 AM PDT 24 401800720 ps
T1221 /workspace/coverage/cover_reg_top/4.kmac_intr_test.607061266 Jul 01 10:45:32 AM PDT 24 Jul 01 10:45:34 AM PDT 24 20981293 ps
T1222 /workspace/coverage/cover_reg_top/47.kmac_intr_test.4275518485 Jul 01 10:46:19 AM PDT 24 Jul 01 10:46:20 AM PDT 24 81478481 ps
T1223 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.1050693901 Jul 01 10:45:34 AM PDT 24 Jul 01 10:45:37 AM PDT 24 254159730 ps
T1224 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.634944473 Jul 01 10:45:55 AM PDT 24 Jul 01 10:45:57 AM PDT 24 85877538 ps
T1225 /workspace/coverage/cover_reg_top/1.kmac_intr_test.168603993 Jul 01 10:45:37 AM PDT 24 Jul 01 10:45:38 AM PDT 24 36653726 ps

Test location /workspace/coverage/default/7.kmac_mubi.2328718258
Short name T3
Test name
Test status
Simulation time 5822425390 ps
CPU time 139.22 seconds
Started Jul 01 12:08:56 PM PDT 24
Finished Jul 01 12:11:16 PM PDT 24
Peak memory 238720 kb
Host smart-e5ab7967-f10a-43ac-b8c5-4fb65a72dab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328718258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2328718258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1554281002
Short name T97
Test name
Test status
Simulation time 64347524 ps
CPU time 1.73 seconds
Started Jul 01 10:45:50 AM PDT 24
Finished Jul 01 10:45:53 AM PDT 24
Peak memory 218216 kb
Host smart-718a1c81-1cf9-4268-9e3b-d3926c6c2992
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554281002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.1554281002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.1719149811
Short name T2
Test name
Test status
Simulation time 70738521 ps
CPU time 1.3 seconds
Started Jul 01 12:05:43 PM PDT 24
Finished Jul 01 12:05:46 PM PDT 24
Peak memory 218200 kb
Host smart-307cce1b-fa9b-45cd-9672-4232ed026136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719149811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1719149811 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_stress_all_with_rand_reset.1357190916
Short name T69
Test name
Test status
Simulation time 21949505893 ps
CPU time 512.45 seconds
Started Jul 01 12:08:41 PM PDT 24
Finished Jul 01 12:17:14 PM PDT 24
Peak memory 272288 kb
Host smart-cef14e71-7ec3-4f01-873d-f54cb76c3ca9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357190916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.1357190916 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.kmac_key_error.3776775226
Short name T37
Test name
Test status
Simulation time 1840749168 ps
CPU time 13.54 seconds
Started Jul 01 12:15:09 PM PDT 24
Finished Jul 01 12:15:23 PM PDT 24
Peak memory 218124 kb
Host smart-2b3a0084-52ee-42a9-9450-9a0638012b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776775226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3776775226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.3687845629
Short name T27
Test name
Test status
Simulation time 14612660439 ps
CPU time 51.23 seconds
Started Jul 01 12:07:16 PM PDT 24
Finished Jul 01 12:08:08 PM PDT 24
Peak memory 260764 kb
Host smart-1e0b5797-97f1-4903-8ea1-92eefff82281
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687845629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3687845629 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.982674080
Short name T7
Test name
Test status
Simulation time 13032419414 ps
CPU time 369.13 seconds
Started Jul 01 12:07:30 PM PDT 24
Finished Jul 01 12:13:40 PM PDT 24
Peak memory 248040 kb
Host smart-d51110f3-b761-4f4b-b4f3-4af79547c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982674080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.982674080 +enable_masking=1 +sw_
key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.734957141
Short name T30
Test name
Test status
Simulation time 75776255 ps
CPU time 1.5 seconds
Started Jul 01 12:11:03 PM PDT 24
Finished Jul 01 12:11:06 PM PDT 24
Peak memory 219112 kb
Host smart-1e3dac29-177d-46a8-a018-5136b8b80bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734957141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.734957141 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_error.1955724357
Short name T20
Test name
Test status
Simulation time 34622682902 ps
CPU time 441.72 seconds
Started Jul 01 12:05:39 PM PDT 24
Finished Jul 01 12:13:02 PM PDT 24
Peak memory 264580 kb
Host smart-17a15ffc-5a87-43b3-8dea-93fdf1e4aa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955724357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1955724357 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_sideload.507037267
Short name T31
Test name
Test status
Simulation time 3708596033 ps
CPU time 273.92 seconds
Started Jul 01 12:20:54 PM PDT 24
Finished Jul 01 12:25:29 PM PDT 24
Peak memory 246232 kb
Host smart-d8a3b395-1468-449e-b7da-722bf7858c9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507037267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.507037267 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.2260918962
Short name T772
Test name
Test status
Simulation time 13340602883 ps
CPU time 70.84 seconds
Started Jul 01 12:07:11 PM PDT 24
Finished Jul 01 12:08:22 PM PDT 24
Peak memory 219884 kb
Host smart-c8fd5dab-c4a0-4474-903a-2a736ba32008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260918962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2260918962 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.1956659537
Short name T53
Test name
Test status
Simulation time 74229967 ps
CPU time 1.07 seconds
Started Jul 01 12:11:05 PM PDT 24
Finished Jul 01 12:11:06 PM PDT 24
Peak memory 218056 kb
Host smart-f4f4bc76-2355-4e98-90db-6393637b58dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1956659537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1956659537 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.679425343
Short name T130
Test name
Test status
Simulation time 761398393 ps
CPU time 4.52 seconds
Started Jul 01 10:45:26 AM PDT 24
Finished Jul 01 10:45:31 AM PDT 24
Peak memory 215816 kb
Host smart-4f2ee3f0-ed33-494b-b9f0-23d34d69b3a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679425343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.679425
343 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.2256411642
Short name T177
Test name
Test status
Simulation time 22743963 ps
CPU time 0.87 seconds
Started Jul 01 10:45:49 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 215744 kb
Host smart-a62ddd8c-dc47-4761-96fa-35c73846b846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256411642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2256411642 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.4145168002
Short name T43
Test name
Test status
Simulation time 57127571 ps
CPU time 1.44 seconds
Started Jul 01 12:23:42 PM PDT 24
Finished Jul 01 12:23:44 PM PDT 24
Peak memory 223848 kb
Host smart-bed8362a-cde3-4214-849e-9cfe90c864e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145168002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.4145168002 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.3742501557
Short name T72
Test name
Test status
Simulation time 2863078624 ps
CPU time 13.34 seconds
Started Jul 01 12:16:43 PM PDT 24
Finished Jul 01 12:16:57 PM PDT 24
Peak memory 230120 kb
Host smart-50ca9341-411a-4a6c-b3ef-0531800a3520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742501557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.3742501557 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.2875853053
Short name T80
Test name
Test status
Simulation time 651912913952 ps
CPU time 4627.86 seconds
Started Jul 01 12:10:08 PM PDT 24
Finished Jul 01 01:27:17 PM PDT 24
Peak memory 564576 kb
Host smart-603a16ff-b9cc-4828-bbf4-dbad98d272ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2875853053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.2875853053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.2232653222
Short name T433
Test name
Test status
Simulation time 175431209 ps
CPU time 1.43 seconds
Started Jul 01 12:05:41 PM PDT 24
Finished Jul 01 12:05:43 PM PDT 24
Peak memory 218024 kb
Host smart-294a9d48-df38-4f2b-ac7d-c50b41563c92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2232653222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.2232653222 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.2961342968
Short name T49
Test name
Test status
Simulation time 37988227 ps
CPU time 1.36 seconds
Started Jul 01 12:12:48 PM PDT 24
Finished Jul 01 12:12:51 PM PDT 24
Peak memory 218228 kb
Host smart-d65d9e17-b0bd-4d56-9429-0764e7ccd23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961342968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2961342968 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.1934441517
Short name T66
Test name
Test status
Simulation time 87754963 ps
CPU time 1.28 seconds
Started Jul 01 12:07:17 PM PDT 24
Finished Jul 01 12:07:19 PM PDT 24
Peak memory 218184 kb
Host smart-d03e688e-28c8-4d40-85cc-0dcbab721311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934441517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1934441517 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.708009860
Short name T99
Test name
Test status
Simulation time 216273056 ps
CPU time 1.57 seconds
Started Jul 01 10:46:02 AM PDT 24
Finished Jul 01 10:46:04 AM PDT 24
Peak memory 217176 kb
Host smart-80a9fa5b-72cd-4c9e-be32-d0636bf86f13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708009860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e
rrors.708009860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2222105969
Short name T156
Test name
Test status
Simulation time 73128440 ps
CPU time 1.24 seconds
Started Jul 01 10:45:34 AM PDT 24
Finished Jul 01 10:45:35 AM PDT 24
Peak memory 215828 kb
Host smart-cf6a6d22-2261-4ceb-b11f-68832bce314f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222105969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.2222105969 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/18.kmac_alert_test.1435345674
Short name T226
Test name
Test status
Simulation time 17037133 ps
CPU time 0.83 seconds
Started Jul 01 12:13:50 PM PDT 24
Finished Jul 01 12:13:51 PM PDT 24
Peak memory 217828 kb
Host smart-913044ad-2d0b-4d49-90fa-a27d56f86ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435345674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1435345674 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.821619952
Short name T92
Test name
Test status
Simulation time 21821501895 ps
CPU time 1844.93 seconds
Started Jul 01 12:22:27 PM PDT 24
Finished Jul 01 12:53:12 PM PDT 24
Peak memory 389660 kb
Host smart-22f677ed-8cb7-415d-acc4-b0fed0096265
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=821619952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.821619952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.2365602373
Short name T76
Test name
Test status
Simulation time 42295887 ps
CPU time 1.4 seconds
Started Jul 01 12:06:14 PM PDT 24
Finished Jul 01 12:06:16 PM PDT 24
Peak memory 218248 kb
Host smart-7068c525-221b-488b-b25b-e7ef4feb56de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365602373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2365602373 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.2816124644
Short name T45
Test name
Test status
Simulation time 33641073 ps
CPU time 1.43 seconds
Started Jul 01 12:06:40 PM PDT 24
Finished Jul 01 12:06:42 PM PDT 24
Peak memory 218224 kb
Host smart-feb2149d-33cf-4940-8356-75ddb1b0328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816124644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2816124644 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2550037004
Short name T188
Test name
Test status
Simulation time 367297115 ps
CPU time 4.01 seconds
Started Jul 01 10:45:47 AM PDT 24
Finished Jul 01 10:45:54 AM PDT 24
Peak memory 215384 kb
Host smart-93b1fe6d-16b4-4446-a22d-46302f2777ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550037004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2550
037004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.696287011
Short name T1079
Test name
Test status
Simulation time 15859375 ps
CPU time 0.83 seconds
Started Jul 01 10:46:06 AM PDT 24
Finished Jul 01 10:46:07 AM PDT 24
Peak memory 215684 kb
Host smart-5f539012-5dee-4523-894a-777641dab671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696287011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.696287011 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2180531113
Short name T104
Test name
Test status
Simulation time 82659041 ps
CPU time 1.33 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:42 AM PDT 24
Peak memory 216284 kb
Host smart-ad7dc1c7-8387-4535-a8a1-bf170869c5b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180531113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.2180531113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.4158249931
Short name T29
Test name
Test status
Simulation time 16440233026 ps
CPU time 56.42 seconds
Started Jul 01 12:06:20 PM PDT 24
Finished Jul 01 12:07:17 PM PDT 24
Peak memory 267560 kb
Host smart-fa985f47-8d90-4246-90c9-549f2424725d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158249931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.4158249931 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.1931771774
Short name T50
Test name
Test status
Simulation time 11993803704 ps
CPU time 275.85 seconds
Started Jul 01 12:15:33 PM PDT 24
Finished Jul 01 12:20:09 PM PDT 24
Peak memory 245128 kb
Host smart-43f64c47-7951-421d-846b-e543491631c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931771774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1931771774 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.2778205260
Short name T375
Test name
Test status
Simulation time 81227429931 ps
CPU time 380.99 seconds
Started Jul 01 12:26:46 PM PDT 24
Finished Jul 01 12:33:08 PM PDT 24
Peak memory 258888 kb
Host smart-6057a16a-8002-4959-b361-ce7b9a5943df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778205260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2778205260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_burst_write.2480822124
Short name T165
Test name
Test status
Simulation time 24145068116 ps
CPU time 1633.73 seconds
Started Jul 01 12:07:20 PM PDT 24
Finished Jul 01 12:34:35 PM PDT 24
Peak memory 237864 kb
Host smart-deb351dd-0b1c-4adb-9eee-f9fe30940431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480822124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.2480822124 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_smoke.2628596255
Short name T216
Test name
Test status
Simulation time 2993352450 ps
CPU time 73.69 seconds
Started Jul 01 12:10:25 PM PDT 24
Finished Jul 01 12:11:39 PM PDT 24
Peak memory 226312 kb
Host smart-c8f17695-1a5b-47ac-b55b-54a3200513d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628596255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2628596255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.3515191140
Short name T61
Test name
Test status
Simulation time 7720801309 ps
CPU time 233.82 seconds
Started Jul 01 12:11:42 PM PDT 24
Finished Jul 01 12:15:36 PM PDT 24
Peak memory 244484 kb
Host smart-cef2de25-980c-4115-b7d4-ae29992f0fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515191140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3515191140 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3227390323
Short name T170
Test name
Test status
Simulation time 263340610 ps
CPU time 2.02 seconds
Started Jul 01 10:45:29 AM PDT 24
Finished Jul 01 10:45:32 AM PDT 24
Peak memory 219524 kb
Host smart-5faa3b9a-8989-4fb9-b5a9-bce715b2dae6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227390323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.3227390323 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.4093185062
Short name T326
Test name
Test status
Simulation time 7236457622 ps
CPU time 237.45 seconds
Started Jul 01 12:16:53 PM PDT 24
Finished Jul 01 12:20:51 PM PDT 24
Peak memory 241628 kb
Host smart-fd06c018-2ac2-4e31-9d96-045cc38d8c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093185062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.4093185062 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.386554789
Short name T1000
Test name
Test status
Simulation time 35401851073 ps
CPU time 516.62 seconds
Started Jul 01 12:20:45 PM PDT 24
Finished Jul 01 12:29:22 PM PDT 24
Peak memory 267392 kb
Host smart-bb9490f8-7c16-478d-8e17-59111f282728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386554789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.386554789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1650203558
Short name T1122
Test name
Test status
Simulation time 148779630 ps
CPU time 8.22 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:55 AM PDT 24
Peak memory 215764 kb
Host smart-62be964b-9718-4bd5-b19e-2f179742474b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650203558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1650203
558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2841684824
Short name T1156
Test name
Test status
Simulation time 1946580409 ps
CPU time 19.47 seconds
Started Jul 01 10:45:29 AM PDT 24
Finished Jul 01 10:45:49 AM PDT 24
Peak memory 215788 kb
Host smart-447c7a6b-8458-439c-ab4f-685a7c47b1d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841684824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2841684
824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2019993383
Short name T1163
Test name
Test status
Simulation time 60121339 ps
CPU time 1.09 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:45 AM PDT 24
Peak memory 215884 kb
Host smart-fb0dbeac-25b0-4e95-8fc0-baca0011b5b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019993383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2019993
383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.17126869
Short name T1119
Test name
Test status
Simulation time 59555772 ps
CPU time 1.6 seconds
Started Jul 01 10:45:30 AM PDT 24
Finished Jul 01 10:45:32 AM PDT 24
Peak memory 216892 kb
Host smart-0267efaf-f804-4dd2-8303-f0a9de01bd44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17126869 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.17126869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2559206368
Short name T1219
Test name
Test status
Simulation time 77381653 ps
CPU time 0.95 seconds
Started Jul 01 10:45:25 AM PDT 24
Finished Jul 01 10:45:26 AM PDT 24
Peak memory 215676 kb
Host smart-7cb2cdd6-2393-444e-a4bd-3749df0cd2fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559206368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2559206368 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2249706044
Short name T1106
Test name
Test status
Simulation time 68799471 ps
CPU time 0.81 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 215712 kb
Host smart-c2564f81-f1c6-4e94-860e-8e23da4d2540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249706044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2249706044 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3615366888
Short name T157
Test name
Test status
Simulation time 17992238 ps
CPU time 1.2 seconds
Started Jul 01 10:45:26 AM PDT 24
Finished Jul 01 10:45:28 AM PDT 24
Peak memory 215804 kb
Host smart-66457847-a6ac-4f34-8f60-13d0a4200b09
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615366888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.3615366888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1931944741
Short name T1200
Test name
Test status
Simulation time 13933871 ps
CPU time 0.78 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 215792 kb
Host smart-32110a91-9e29-45e0-9edb-6c52fc34b5b2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931944741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1931944741
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2564149832
Short name T1185
Test name
Test status
Simulation time 448085812 ps
CPU time 2.26 seconds
Started Jul 01 10:45:29 AM PDT 24
Finished Jul 01 10:45:32 AM PDT 24
Peak memory 215828 kb
Host smart-3e6b618b-00ef-4f2a-a680-b3b0e40aa1e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564149832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.2564149832 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.372298902
Short name T105
Test name
Test status
Simulation time 182402881 ps
CPU time 2.62 seconds
Started Jul 01 10:45:24 AM PDT 24
Finished Jul 01 10:45:27 AM PDT 24
Peak memory 218972 kb
Host smart-f96b4a8f-ed8a-4bbd-99c1-784312d6a2b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372298902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_
shadow_reg_errors_with_csr_rw.372298902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.58485170
Short name T140
Test name
Test status
Simulation time 63997049 ps
CPU time 1.28 seconds
Started Jul 01 10:45:26 AM PDT 24
Finished Jul 01 10:45:28 AM PDT 24
Peak memory 215968 kb
Host smart-342044fb-c691-4ccf-a0c6-d1cda3c250dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58485170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.58485170 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2144967617
Short name T1117
Test name
Test status
Simulation time 1159215228 ps
CPU time 9.13 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:53 AM PDT 24
Peak memory 215736 kb
Host smart-d9604323-3a7e-4d00-95db-415f59489f0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144967617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2144967
617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2483226661
Short name T1216
Test name
Test status
Simulation time 397495839 ps
CPU time 15.21 seconds
Started Jul 01 10:45:30 AM PDT 24
Finished Jul 01 10:45:46 AM PDT 24
Peak memory 215884 kb
Host smart-5f7d9152-b200-49b3-9f0d-fafc595ea522
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483226661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2483226
661 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2374211657
Short name T134
Test name
Test status
Simulation time 71557765 ps
CPU time 1.02 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 215732 kb
Host smart-7d070b57-d3a7-4594-a2aa-bfe655e67da8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374211657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2374211
657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3475802618
Short name T1207
Test name
Test status
Simulation time 36108721 ps
CPU time 2.34 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:44 AM PDT 24
Peak memory 220924 kb
Host smart-8b33629c-253d-4533-a5ed-e68e3614e23e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475802618 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.3475802618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.4079165326
Short name T1131
Test name
Test status
Simulation time 15766812 ps
CPU time 1.09 seconds
Started Jul 01 10:46:22 AM PDT 24
Finished Jul 01 10:46:23 AM PDT 24
Peak memory 215772 kb
Host smart-9766d97b-6c3a-4ec7-85c1-e7286659e529
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079165326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.4079165326 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.168603993
Short name T1225
Test name
Test status
Simulation time 36653726 ps
CPU time 0.87 seconds
Started Jul 01 10:45:37 AM PDT 24
Finished Jul 01 10:45:38 AM PDT 24
Peak memory 215752 kb
Host smart-eb01d62f-eb82-4fa1-9100-f44fba89b258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168603993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.168603993 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.640012672
Short name T153
Test name
Test status
Simulation time 150462722 ps
CPU time 1.41 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 215800 kb
Host smart-16b7cc8f-a9cd-4f6d-8b87-b7ac7fe01c93
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640012672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial
_access.640012672 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3592813006
Short name T1183
Test name
Test status
Simulation time 13406301 ps
CPU time 0.72 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 215764 kb
Host smart-d59f1c1b-e374-4e90-b1d2-e3b617a61663
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592813006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3592813006
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3356514868
Short name T169
Test name
Test status
Simulation time 455112306 ps
CPU time 2.74 seconds
Started Jul 01 10:45:34 AM PDT 24
Finished Jul 01 10:45:37 AM PDT 24
Peak memory 215852 kb
Host smart-01547689-8e5e-48ef-9903-e06ef0c458ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356514868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.3356514868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.884474229
Short name T1108
Test name
Test status
Simulation time 160218712 ps
CPU time 1.3 seconds
Started Jul 01 10:45:32 AM PDT 24
Finished Jul 01 10:45:34 AM PDT 24
Peak memory 216400 kb
Host smart-a3e0284a-eb01-4bd8-a3ca-9694aa4150ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884474229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e
rrors.884474229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1499667059
Short name T1068
Test name
Test status
Simulation time 143780387 ps
CPU time 1.82 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 215896 kb
Host smart-8bdafed3-11ba-46be-94ee-04c2dd1d1f99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499667059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.1499667059 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2616706613
Short name T1124
Test name
Test status
Simulation time 130478446 ps
CPU time 2.98 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 215808 kb
Host smart-86bc4932-f57a-4ed6-a787-1c5a0b502594
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616706613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.26167
06613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1395228121
Short name T1118
Test name
Test status
Simulation time 90561175 ps
CPU time 1.76 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:49 AM PDT 24
Peak memory 217144 kb
Host smart-f3e79d3c-e2d0-44ce-a935-f017847324f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395228121 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.1395228121 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2061563071
Short name T168
Test name
Test status
Simulation time 33465382 ps
CPU time 1.13 seconds
Started Jul 01 10:45:45 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 215792 kb
Host smart-68d47c21-7279-4056-8bc4-bd7ea56344f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061563071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2061563071 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.946546078
Short name T1174
Test name
Test status
Simulation time 38294276 ps
CPU time 0.8 seconds
Started Jul 01 10:46:09 AM PDT 24
Finished Jul 01 10:46:10 AM PDT 24
Peak memory 215736 kb
Host smart-2af65cfe-2551-4274-92b9-32f49b792210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946546078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.946546078 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3433548894
Short name T1213
Test name
Test status
Simulation time 70746979 ps
CPU time 1.81 seconds
Started Jul 01 10:46:14 AM PDT 24
Finished Jul 01 10:46:17 AM PDT 24
Peak memory 215772 kb
Host smart-51c4490d-6ad8-45a5-93de-b7bc3910f3d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433548894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.3433548894 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2598980476
Short name T1146
Test name
Test status
Simulation time 79525542 ps
CPU time 1.48 seconds
Started Jul 01 10:45:49 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 217396 kb
Host smart-fc201018-fbd8-4033-b48d-aba14777f048
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598980476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.2598980476 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.8773386
Short name T1140
Test name
Test status
Simulation time 392755315 ps
CPU time 3.12 seconds
Started Jul 01 10:45:49 AM PDT 24
Finished Jul 01 10:45:54 AM PDT 24
Peak memory 218816 kb
Host smart-3ab812e2-0744-4bd8-8c91-0cf212dbc27b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8773386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_s
hadow_reg_errors_with_csr_rw.8773386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2619196091
Short name T1150
Test name
Test status
Simulation time 38246511 ps
CPU time 2.06 seconds
Started Jul 01 10:45:46 AM PDT 24
Finished Jul 01 10:45:51 AM PDT 24
Peak memory 215964 kb
Host smart-4846fd7e-292a-45ce-a28c-827d36045cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619196091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2619196091 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3001956705
Short name T191
Test name
Test status
Simulation time 3398580684 ps
CPU time 5.62 seconds
Started Jul 01 10:45:48 AM PDT 24
Finished Jul 01 10:45:56 AM PDT 24
Peak memory 215876 kb
Host smart-6ee35cdc-4828-446a-b016-6f85bee010cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001956705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3001
956705 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1360697355
Short name T1197
Test name
Test status
Simulation time 77744694 ps
CPU time 1.71 seconds
Started Jul 01 10:45:49 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 219900 kb
Host smart-976c8d31-a7e5-4d49-9e7e-e3bd25d0a625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360697355 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1360697355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2687420068
Short name T1164
Test name
Test status
Simulation time 287351162 ps
CPU time 0.97 seconds
Started Jul 01 10:46:07 AM PDT 24
Finished Jul 01 10:46:09 AM PDT 24
Peak memory 215720 kb
Host smart-ea5d3097-a964-43c9-83db-8e2fa4a1c166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687420068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2687420068 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3898133796
Short name T1208
Test name
Test status
Simulation time 72591342 ps
CPU time 1.71 seconds
Started Jul 01 10:45:50 AM PDT 24
Finished Jul 01 10:45:53 AM PDT 24
Peak memory 215804 kb
Host smart-c13d029a-c05c-4cbf-8e2e-347bce294bca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898133796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.3898133796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2058009281
Short name T101
Test name
Test status
Simulation time 17716974 ps
CPU time 0.84 seconds
Started Jul 01 10:46:03 AM PDT 24
Finished Jul 01 10:46:04 AM PDT 24
Peak memory 215736 kb
Host smart-2a286ba0-ed4a-47c6-9091-27cf4d45aeaa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058009281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.2058009281 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1999919359
Short name T1083
Test name
Test status
Simulation time 185819712 ps
CPU time 1.92 seconds
Started Jul 01 10:45:46 AM PDT 24
Finished Jul 01 10:45:51 AM PDT 24
Peak memory 218572 kb
Host smart-b519431b-abbd-4049-8393-0f33dc995334
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999919359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.1999919359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2672037820
Short name T1220
Test name
Test status
Simulation time 401800720 ps
CPU time 2.67 seconds
Started Jul 01 10:46:09 AM PDT 24
Finished Jul 01 10:46:12 AM PDT 24
Peak memory 215964 kb
Host smart-a5c70fea-dc49-4f53-a8d3-621bce78d8fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672037820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2672037820 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2964147087
Short name T180
Test name
Test status
Simulation time 344665007 ps
CPU time 5.84 seconds
Started Jul 01 10:46:09 AM PDT 24
Finished Jul 01 10:46:16 AM PDT 24
Peak memory 215796 kb
Host smart-b983d94f-cfdf-42b7-b8ae-5c2005222c84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964147087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2964
147087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2284091803
Short name T1199
Test name
Test status
Simulation time 74031220 ps
CPU time 2.43 seconds
Started Jul 01 10:46:13 AM PDT 24
Finished Jul 01 10:46:16 AM PDT 24
Peak memory 221016 kb
Host smart-24717b31-7145-427d-975c-ca8878cb9d6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284091803 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2284091803 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3416075878
Short name T1069
Test name
Test status
Simulation time 31928585 ps
CPU time 1.1 seconds
Started Jul 01 10:45:49 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 215796 kb
Host smart-94475f8f-f28e-4a8d-a3b1-303417ad15e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416075878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3416075878 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3748974369
Short name T1211
Test name
Test status
Simulation time 56295178 ps
CPU time 1.77 seconds
Started Jul 01 10:45:49 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 215864 kb
Host smart-10c5f9cc-f557-410a-841d-e7f8faec196c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748974369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.3748974369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1246918804
Short name T96
Test name
Test status
Simulation time 34702760 ps
CPU time 1.4 seconds
Started Jul 01 10:45:47 AM PDT 24
Finished Jul 01 10:45:51 AM PDT 24
Peak memory 216356 kb
Host smart-05958025-8b77-46cc-abb3-64366439613f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246918804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.1246918804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.658492006
Short name T1158
Test name
Test status
Simulation time 49908220 ps
CPU time 2.86 seconds
Started Jul 01 10:45:49 AM PDT 24
Finished Jul 01 10:45:54 AM PDT 24
Peak memory 215952 kb
Host smart-72052376-c4c0-4517-b6d6-5b3e9a396080
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658492006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.658492006 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3525887006
Short name T151
Test name
Test status
Simulation time 50847372 ps
CPU time 1.63 seconds
Started Jul 01 10:45:50 AM PDT 24
Finished Jul 01 10:45:53 AM PDT 24
Peak memory 217120 kb
Host smart-12dc030e-ab33-4513-bacc-175e84181292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525887006 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3525887006 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.3481270908
Short name T1081
Test name
Test status
Simulation time 129282464 ps
CPU time 0.92 seconds
Started Jul 01 10:46:04 AM PDT 24
Finished Jul 01 10:46:05 AM PDT 24
Peak memory 215660 kb
Host smart-88f7d9ff-88c4-462c-a837-5cef7ea7eaef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481270908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3481270908 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.2408496964
Short name T1177
Test name
Test status
Simulation time 42163649 ps
CPU time 0.8 seconds
Started Jul 01 10:45:49 AM PDT 24
Finished Jul 01 10:45:51 AM PDT 24
Peak memory 215748 kb
Host smart-41cb018c-d907-48a5-972f-8f3b4a347e44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408496964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2408496964 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3334455815
Short name T1142
Test name
Test status
Simulation time 125687463 ps
CPU time 2.07 seconds
Started Jul 01 10:45:47 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 215312 kb
Host smart-a2eb2f9e-865f-43a0-b93b-2afd5d8a1803
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334455815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3334455815 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2091705646
Short name T1105
Test name
Test status
Simulation time 42066115 ps
CPU time 0.99 seconds
Started Jul 01 10:46:02 AM PDT 24
Finished Jul 01 10:46:03 AM PDT 24
Peak memory 216060 kb
Host smart-acc73f8b-2ba8-4831-a2a7-ca1892ce7a95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091705646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.2091705646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.721227805
Short name T1201
Test name
Test status
Simulation time 79165063 ps
CPU time 2.04 seconds
Started Jul 01 10:45:50 AM PDT 24
Finished Jul 01 10:45:53 AM PDT 24
Peak memory 215948 kb
Host smart-94be200b-6714-481f-bd12-82404367157e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721227805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.721227805 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2835393302
Short name T192
Test name
Test status
Simulation time 144567637 ps
CPU time 4.12 seconds
Started Jul 01 10:46:16 AM PDT 24
Finished Jul 01 10:46:20 AM PDT 24
Peak memory 215860 kb
Host smart-a170eb0f-dd07-4a20-a38f-0fda606a0c86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835393302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2835
393302 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.310396378
Short name T143
Test name
Test status
Simulation time 1157524748 ps
CPU time 2.57 seconds
Started Jul 01 10:46:02 AM PDT 24
Finished Jul 01 10:46:05 AM PDT 24
Peak memory 220696 kb
Host smart-d6764611-8b0f-4262-800a-1973c78aacf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310396378 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.310396378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.3236291040
Short name T1120
Test name
Test status
Simulation time 99531737 ps
CPU time 1.19 seconds
Started Jul 01 10:46:03 AM PDT 24
Finished Jul 01 10:46:05 AM PDT 24
Peak memory 215872 kb
Host smart-7ed7ab0a-d025-4aeb-aa65-4d260fe13cab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236291040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.3236291040 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.3060587880
Short name T175
Test name
Test status
Simulation time 65898377 ps
CPU time 0.83 seconds
Started Jul 01 10:45:51 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 215740 kb
Host smart-3879bc05-5b93-4881-8cab-d3e8d475ac6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060587880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3060587880 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1651418821
Short name T1091
Test name
Test status
Simulation time 107738093 ps
CPU time 1.83 seconds
Started Jul 01 10:45:51 AM PDT 24
Finished Jul 01 10:45:54 AM PDT 24
Peak memory 215796 kb
Host smart-fe5a7c0f-21ba-4082-acf8-fe5beaf9c07e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651418821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.1651418821 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2011120355
Short name T1132
Test name
Test status
Simulation time 97006782 ps
CPU time 1.07 seconds
Started Jul 01 10:45:53 AM PDT 24
Finished Jul 01 10:45:55 AM PDT 24
Peak memory 216056 kb
Host smart-378a4a2d-fceb-4c09-910f-f6b0ac13c758
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011120355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.2011120355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.359481664
Short name T100
Test name
Test status
Simulation time 82730909 ps
CPU time 1.98 seconds
Started Jul 01 10:45:52 AM PDT 24
Finished Jul 01 10:45:55 AM PDT 24
Peak memory 218168 kb
Host smart-4a42b8b2-35d2-4496-b12b-501b9775e6e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359481664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac
_shadow_reg_errors_with_csr_rw.359481664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2187606596
Short name T1186
Test name
Test status
Simulation time 36248160 ps
CPU time 2.31 seconds
Started Jul 01 10:46:04 AM PDT 24
Finished Jul 01 10:46:07 AM PDT 24
Peak memory 215816 kb
Host smart-528ba7ee-1766-49fc-a864-b4522a19e869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187606596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2187606596 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3863082499
Short name T181
Test name
Test status
Simulation time 100373836 ps
CPU time 2.82 seconds
Started Jul 01 10:45:55 AM PDT 24
Finished Jul 01 10:45:58 AM PDT 24
Peak memory 215776 kb
Host smart-b2aa9e42-763d-4481-a7f3-9ccb7af74156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863082499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3863
082499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1095736640
Short name T1133
Test name
Test status
Simulation time 325625436 ps
CPU time 1.96 seconds
Started Jul 01 10:46:10 AM PDT 24
Finished Jul 01 10:46:13 AM PDT 24
Peak memory 220740 kb
Host smart-ab35016b-585f-41ed-8710-2a1fedd82df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095736640 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1095736640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3909331872
Short name T1165
Test name
Test status
Simulation time 16092003 ps
CPU time 0.92 seconds
Started Jul 01 10:46:09 AM PDT 24
Finished Jul 01 10:46:10 AM PDT 24
Peak memory 215716 kb
Host smart-72b3ef19-fd6e-4c59-9d14-32d6d02e5f1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909331872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3909331872 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.3120304017
Short name T1100
Test name
Test status
Simulation time 39518884 ps
CPU time 0.75 seconds
Started Jul 01 10:46:14 AM PDT 24
Finished Jul 01 10:46:16 AM PDT 24
Peak memory 215708 kb
Host smart-3fd2c0e0-8f7a-4699-a926-7d44f0774c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120304017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3120304017 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.176389517
Short name T1087
Test name
Test status
Simulation time 109582631 ps
CPU time 2.51 seconds
Started Jul 01 10:45:56 AM PDT 24
Finished Jul 01 10:45:59 AM PDT 24
Peak memory 215700 kb
Host smart-3196237a-66a6-4601-9abf-7bbceda8b2ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176389517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr
_outstanding.176389517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1004896491
Short name T1160
Test name
Test status
Simulation time 161229988 ps
CPU time 1.5 seconds
Started Jul 01 10:45:51 AM PDT 24
Finished Jul 01 10:45:53 AM PDT 24
Peak memory 216340 kb
Host smart-c6e8ab99-4d17-46ec-831e-7b86fd24871c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004896491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.1004896491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3421215983
Short name T108
Test name
Test status
Simulation time 145395676 ps
CPU time 2.34 seconds
Started Jul 01 10:45:56 AM PDT 24
Finished Jul 01 10:45:59 AM PDT 24
Peak memory 219688 kb
Host smart-81e79b7a-7d7a-4c4b-9889-759b233f8dbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421215983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.3421215983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.967722212
Short name T1126
Test name
Test status
Simulation time 396649282 ps
CPU time 2.5 seconds
Started Jul 01 10:46:15 AM PDT 24
Finished Jul 01 10:46:18 AM PDT 24
Peak memory 215896 kb
Host smart-54b17f99-cea6-4653-829e-fed7efbac00d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967722212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.967722212 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1785848672
Short name T190
Test name
Test status
Simulation time 1094617435 ps
CPU time 4.9 seconds
Started Jul 01 10:45:53 AM PDT 24
Finished Jul 01 10:45:58 AM PDT 24
Peak memory 215792 kb
Host smart-c1a5fa02-b50e-4a97-808a-f747ef6336d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785848672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1785
848672 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2846086525
Short name T142
Test name
Test status
Simulation time 25229066 ps
CPU time 1.71 seconds
Started Jul 01 10:45:52 AM PDT 24
Finished Jul 01 10:45:54 AM PDT 24
Peak memory 221556 kb
Host smart-e502f260-605f-4d38-87d5-b04bfde1494e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846086525 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2846086525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1582668316
Short name T1176
Test name
Test status
Simulation time 26504736 ps
CPU time 0.98 seconds
Started Jul 01 10:45:51 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 215768 kb
Host smart-992ec290-61fe-4f04-b197-731e38f20878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582668316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1582668316 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.3746244765
Short name T1144
Test name
Test status
Simulation time 12484314 ps
CPU time 0.78 seconds
Started Jul 01 10:46:08 AM PDT 24
Finished Jul 01 10:46:09 AM PDT 24
Peak memory 215712 kb
Host smart-447fc0d2-6b8f-4fa3-8e4d-45acae225d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746244765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3746244765 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.104961818
Short name T1094
Test name
Test status
Simulation time 52147298 ps
CPU time 1.78 seconds
Started Jul 01 10:45:50 AM PDT 24
Finished Jul 01 10:45:53 AM PDT 24
Peak memory 215804 kb
Host smart-ff2ec37d-0df2-4bc8-82d0-0b21984f3c48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104961818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr
_outstanding.104961818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.500621944
Short name T103
Test name
Test status
Simulation time 29785757 ps
CPU time 1.11 seconds
Started Jul 01 10:45:55 AM PDT 24
Finished Jul 01 10:45:56 AM PDT 24
Peak memory 216132 kb
Host smart-a0a17ba9-9d70-460e-baca-dbf70427d7ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500621944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_
errors.500621944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2047178750
Short name T1161
Test name
Test status
Simulation time 68243062 ps
CPU time 1.86 seconds
Started Jul 01 10:46:32 AM PDT 24
Finished Jul 01 10:46:35 AM PDT 24
Peak memory 219604 kb
Host smart-0b267bba-12e3-4048-bc6b-e399a57bff1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047178750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.2047178750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3215538449
Short name T1167
Test name
Test status
Simulation time 44335396 ps
CPU time 2.88 seconds
Started Jul 01 10:46:00 AM PDT 24
Finished Jul 01 10:46:04 AM PDT 24
Peak memory 215908 kb
Host smart-0639ab23-813e-49b0-9151-7020a573db04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215538449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3215538449 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2035905373
Short name T1196
Test name
Test status
Simulation time 155374179 ps
CPU time 2.5 seconds
Started Jul 01 10:46:04 AM PDT 24
Finished Jul 01 10:46:07 AM PDT 24
Peak memory 215804 kb
Host smart-e51df707-2c98-4d13-b11b-51261cc52dc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035905373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2035
905373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.280248347
Short name T1166
Test name
Test status
Simulation time 301975715 ps
CPU time 2.45 seconds
Started Jul 01 10:45:52 AM PDT 24
Finished Jul 01 10:45:55 AM PDT 24
Peak memory 221840 kb
Host smart-02d6ed88-079f-4726-bc1d-d225bfd5ee53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280248347 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.280248347 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.439772157
Short name T1168
Test name
Test status
Simulation time 30928753 ps
CPU time 1.18 seconds
Started Jul 01 10:45:54 AM PDT 24
Finished Jul 01 10:45:56 AM PDT 24
Peak memory 215780 kb
Host smart-6b8797c4-240b-4c50-862d-c0bf45445d18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439772157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.439772157 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.466110448
Short name T1086
Test name
Test status
Simulation time 18858447 ps
CPU time 0.73 seconds
Started Jul 01 10:46:15 AM PDT 24
Finished Jul 01 10:46:16 AM PDT 24
Peak memory 215736 kb
Host smart-69615cbe-9895-4cb2-9096-7f2fcabbca24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466110448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.466110448 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1676208655
Short name T1082
Test name
Test status
Simulation time 26675542 ps
CPU time 1.51 seconds
Started Jul 01 10:46:16 AM PDT 24
Finished Jul 01 10:46:18 AM PDT 24
Peak memory 215864 kb
Host smart-b01bd411-c1dc-4b1e-b128-1021671a73d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676208655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.1676208655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1654423733
Short name T1110
Test name
Test status
Simulation time 413036527 ps
CPU time 1.23 seconds
Started Jul 01 10:45:54 AM PDT 24
Finished Jul 01 10:45:55 AM PDT 24
Peak memory 216116 kb
Host smart-710dbb97-e46a-443b-b3c2-95b980c260b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654423733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.1654423733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.86211106
Short name T1214
Test name
Test status
Simulation time 75862949 ps
CPU time 2.03 seconds
Started Jul 01 10:46:25 AM PDT 24
Finished Jul 01 10:46:28 AM PDT 24
Peak memory 218312 kb
Host smart-2f185a00-5060-4b54-9a33-45fbc54675f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86211106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_
shadow_reg_errors_with_csr_rw.86211106 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.1818289826
Short name T1137
Test name
Test status
Simulation time 295484258 ps
CPU time 3.75 seconds
Started Jul 01 10:46:02 AM PDT 24
Finished Jul 01 10:46:06 AM PDT 24
Peak memory 215936 kb
Host smart-be8b5e50-6378-452c-b42c-252662f96b93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818289826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1818289826 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2902281952
Short name T1217
Test name
Test status
Simulation time 427423526 ps
CPU time 2.72 seconds
Started Jul 01 10:46:15 AM PDT 24
Finished Jul 01 10:46:19 AM PDT 24
Peak memory 215888 kb
Host smart-501567ca-fdfa-4ed7-819c-bd77376e54ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902281952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2902
281952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3957724027
Short name T1103
Test name
Test status
Simulation time 180111250 ps
CPU time 1.77 seconds
Started Jul 01 10:45:56 AM PDT 24
Finished Jul 01 10:45:59 AM PDT 24
Peak memory 217612 kb
Host smart-b71e2687-0815-4257-986c-0ec823347d5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957724027 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.3957724027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2286760086
Short name T1209
Test name
Test status
Simulation time 58218406 ps
CPU time 1.03 seconds
Started Jul 01 10:46:15 AM PDT 24
Finished Jul 01 10:46:17 AM PDT 24
Peak memory 215604 kb
Host smart-f81de70d-ea74-4713-92c5-11763075805b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286760086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2286760086 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.1393592283
Short name T1170
Test name
Test status
Simulation time 15960203 ps
CPU time 0.77 seconds
Started Jul 01 10:46:21 AM PDT 24
Finished Jul 01 10:46:22 AM PDT 24
Peak memory 215724 kb
Host smart-2b46b6ea-dc26-4c5d-bdd9-bc6e2efe5880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393592283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1393592283 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.623950432
Short name T1198
Test name
Test status
Simulation time 130226311 ps
CPU time 2 seconds
Started Jul 01 10:46:25 AM PDT 24
Finished Jul 01 10:46:27 AM PDT 24
Peak memory 215808 kb
Host smart-e6c8a43d-9c3d-4c09-8325-7b5fa170e831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623950432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr
_outstanding.623950432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.82917786
Short name T1141
Test name
Test status
Simulation time 31945244 ps
CPU time 1.1 seconds
Started Jul 01 10:45:55 AM PDT 24
Finished Jul 01 10:45:56 AM PDT 24
Peak memory 216132 kb
Host smart-6d2c5ffa-31fb-4cdc-a9db-4525786cb204
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82917786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_e
rrors.82917786 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2558585311
Short name T1145
Test name
Test status
Simulation time 92737124 ps
CPU time 2.49 seconds
Started Jul 01 10:46:11 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 218716 kb
Host smart-b7036f4a-1461-4c20-8c2d-b0f81d1ec27f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558585311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.2558585311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2501137209
Short name T1073
Test name
Test status
Simulation time 154772622 ps
CPU time 1.63 seconds
Started Jul 01 10:46:13 AM PDT 24
Finished Jul 01 10:46:16 AM PDT 24
Peak memory 215856 kb
Host smart-dca6c110-21b4-4243-a7b4-a045b41528ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501137209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2501137209 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2221576272
Short name T1188
Test name
Test status
Simulation time 1016165241 ps
CPU time 4.92 seconds
Started Jul 01 10:46:28 AM PDT 24
Finished Jul 01 10:46:33 AM PDT 24
Peak memory 215772 kb
Host smart-b73fd88a-741b-4b10-8915-2cb2470228df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221576272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2221
576272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2435640710
Short name T1189
Test name
Test status
Simulation time 785642921 ps
CPU time 2.67 seconds
Started Jul 01 10:46:00 AM PDT 24
Finished Jul 01 10:46:03 AM PDT 24
Peak memory 221152 kb
Host smart-96e3c6fb-8f6a-4774-9fb0-64e85297d0d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435640710 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2435640710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.4154441002
Short name T1107
Test name
Test status
Simulation time 16627623 ps
CPU time 0.99 seconds
Started Jul 01 10:45:59 AM PDT 24
Finished Jul 01 10:46:01 AM PDT 24
Peak memory 215672 kb
Host smart-f4e0d42f-2b43-4a43-86f0-36d46a20cbaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154441002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.4154441002 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.4132752552
Short name T1125
Test name
Test status
Simulation time 39024551 ps
CPU time 0.81 seconds
Started Jul 01 10:46:22 AM PDT 24
Finished Jul 01 10:46:23 AM PDT 24
Peak memory 215752 kb
Host smart-aa1ba6e7-6d13-403f-b9cc-2df0884c5848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132752552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.4132752552 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2363230272
Short name T1151
Test name
Test status
Simulation time 26504187 ps
CPU time 1.44 seconds
Started Jul 01 10:45:58 AM PDT 24
Finished Jul 01 10:45:59 AM PDT 24
Peak memory 215804 kb
Host smart-be6a95bc-7418-4b8e-ba33-3962025d1a06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363230272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.2363230272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.641770414
Short name T1173
Test name
Test status
Simulation time 54158879 ps
CPU time 1.82 seconds
Started Jul 01 10:45:59 AM PDT 24
Finished Jul 01 10:46:01 AM PDT 24
Peak memory 215904 kb
Host smart-a00a8329-9c91-410b-93c7-a0fc8965dc4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641770414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.641770414 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1045539316
Short name T182
Test name
Test status
Simulation time 631160810 ps
CPU time 2.93 seconds
Started Jul 01 10:45:55 AM PDT 24
Finished Jul 01 10:45:58 AM PDT 24
Peak memory 215776 kb
Host smart-10444497-6d8d-492d-909f-5075c475339d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045539316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1045
539316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.591396934
Short name T1193
Test name
Test status
Simulation time 2002921656 ps
CPU time 9.85 seconds
Started Jul 01 10:45:37 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 215824 kb
Host smart-cfe6faf0-5c47-4b60-964d-3febaa4dab25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591396934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.59139693
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.4026487655
Short name T1090
Test name
Test status
Simulation time 1130958184 ps
CPU time 14.94 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:46:02 AM PDT 24
Peak memory 215776 kb
Host smart-d467aef3-21b5-46c5-a49f-a5d0f982239f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026487655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.4026487
655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.2245270041
Short name T1088
Test name
Test status
Simulation time 17558657 ps
CPU time 0.95 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 215732 kb
Host smart-5a497586-6b0d-44dc-9bb2-f1a2070da951
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245270041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.2245270
041 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1432324772
Short name T1097
Test name
Test status
Simulation time 436695152 ps
CPU time 2.91 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:46 AM PDT 24
Peak memory 222052 kb
Host smart-c3dab6ce-e6ae-4f4b-9a43-dd2d80fd78ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432324772 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.1432324772 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.588546828
Short name T1070
Test name
Test status
Simulation time 14912155 ps
CPU time 0.92 seconds
Started Jul 01 10:45:40 AM PDT 24
Finished Jul 01 10:45:42 AM PDT 24
Peak memory 215736 kb
Host smart-cf809676-e499-4455-8420-1557ef177ece
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588546828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.588546828 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.2696705868
Short name T1204
Test name
Test status
Simulation time 34391343 ps
CPU time 0.77 seconds
Started Jul 01 10:45:38 AM PDT 24
Finished Jul 01 10:45:40 AM PDT 24
Peak memory 215764 kb
Host smart-c690b91e-527f-4540-8c74-79600abcca1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696705868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2696705868 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.2719691685
Short name T1178
Test name
Test status
Simulation time 34912259 ps
CPU time 0.77 seconds
Started Jul 01 10:45:45 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 215712 kb
Host smart-4b2113a3-0c41-419a-be88-2a6ab3b306d7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719691685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2719691685
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1911751499
Short name T1098
Test name
Test status
Simulation time 66089827 ps
CPU time 2.06 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 215784 kb
Host smart-03afc0e5-dc6f-4c69-8c9a-ea11dac6572c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911751499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.1911751499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.923589794
Short name T106
Test name
Test status
Simulation time 70641589 ps
CPU time 1.49 seconds
Started Jul 01 10:45:26 AM PDT 24
Finished Jul 01 10:45:28 AM PDT 24
Peak memory 217032 kb
Host smart-5b49efdf-4744-4d7a-bba6-b87ab545ff03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923589794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_e
rrors.923589794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1380428673
Short name T1169
Test name
Test status
Simulation time 121129769 ps
CPU time 1.88 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 217252 kb
Host smart-f0051020-2b28-4300-a768-7acc64b2849c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380428673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.1380428673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.1050693901
Short name T1223
Test name
Test status
Simulation time 254159730 ps
CPU time 2.06 seconds
Started Jul 01 10:45:34 AM PDT 24
Finished Jul 01 10:45:37 AM PDT 24
Peak memory 215984 kb
Host smart-f140c22e-a0fc-453e-9b90-f83f8e8e2780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050693901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1050693901 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1477555888
Short name T193
Test name
Test status
Simulation time 2323124297 ps
CPU time 4.48 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 215932 kb
Host smart-8ceb68d2-a8c0-401e-8fdc-637d4f136b59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477555888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.14775
55888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.831049989
Short name T1138
Test name
Test status
Simulation time 18010334 ps
CPU time 0.86 seconds
Started Jul 01 10:45:57 AM PDT 24
Finished Jul 01 10:45:59 AM PDT 24
Peak memory 215760 kb
Host smart-5d1402aa-8983-4704-a381-0d3ca0c47c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831049989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.831049989 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.4270696953
Short name T1152
Test name
Test status
Simulation time 14514004 ps
CPU time 0.86 seconds
Started Jul 01 10:45:55 AM PDT 24
Finished Jul 01 10:45:56 AM PDT 24
Peak memory 215740 kb
Host smart-58d7e356-dc4c-4db6-888e-6c2f1ff26a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270696953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.4270696953 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.1401411810
Short name T174
Test name
Test status
Simulation time 12577931 ps
CPU time 0.8 seconds
Started Jul 01 10:46:03 AM PDT 24
Finished Jul 01 10:46:04 AM PDT 24
Peak memory 215740 kb
Host smart-44db7284-f181-4a4e-a342-8c06f2ad0186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401411810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1401411810 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.170795188
Short name T1155
Test name
Test status
Simulation time 14006216 ps
CPU time 0.77 seconds
Started Jul 01 10:46:31 AM PDT 24
Finished Jul 01 10:46:32 AM PDT 24
Peak memory 215688 kb
Host smart-1155821a-88e8-447d-ba37-b53c62a5a315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170795188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.170795188 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.2326380556
Short name T1076
Test name
Test status
Simulation time 45126278 ps
CPU time 0.77 seconds
Started Jul 01 10:45:53 AM PDT 24
Finished Jul 01 10:45:54 AM PDT 24
Peak memory 215712 kb
Host smart-a68cb995-49e0-40dd-8dfb-7b90fe7c5788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326380556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2326380556 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.1034387556
Short name T1080
Test name
Test status
Simulation time 64195813 ps
CPU time 0.92 seconds
Started Jul 01 10:46:19 AM PDT 24
Finished Jul 01 10:46:20 AM PDT 24
Peak memory 215764 kb
Host smart-f0217783-5a7e-4321-a8f9-24d76e9ca104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034387556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1034387556 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.934123388
Short name T1147
Test name
Test status
Simulation time 21644747 ps
CPU time 0.78 seconds
Started Jul 01 10:46:11 AM PDT 24
Finished Jul 01 10:46:13 AM PDT 24
Peak memory 215756 kb
Host smart-c6a06f80-eaab-41aa-b041-239828ae91f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934123388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.934123388 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.423747021
Short name T1153
Test name
Test status
Simulation time 48280900 ps
CPU time 0.81 seconds
Started Jul 01 10:46:07 AM PDT 24
Finished Jul 01 10:46:14 AM PDT 24
Peak memory 215680 kb
Host smart-a46f508a-96a8-449e-865f-d10cfba503c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423747021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.423747021 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.1264515714
Short name T1218
Test name
Test status
Simulation time 13726680 ps
CPU time 0.79 seconds
Started Jul 01 10:46:03 AM PDT 24
Finished Jul 01 10:46:04 AM PDT 24
Peak memory 215744 kb
Host smart-fc1952a0-9fce-44c2-b3b4-f0e5fb69d9d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264515714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1264515714 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.878926718
Short name T1205
Test name
Test status
Simulation time 64044616 ps
CPU time 0.74 seconds
Started Jul 01 10:46:08 AM PDT 24
Finished Jul 01 10:46:09 AM PDT 24
Peak memory 215636 kb
Host smart-c9e898e6-065f-4a1e-9a24-0de6a938f38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878926718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.878926718 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.2614573411
Short name T1129
Test name
Test status
Simulation time 770696766 ps
CPU time 9.47 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:57 AM PDT 24
Peak memory 215796 kb
Host smart-a05ebfcf-ebfe-4f5c-8a0c-542ce83c1916
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614573411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2614573
411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.827068640
Short name T1195
Test name
Test status
Simulation time 292952900 ps
CPU time 15.2 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:46:04 AM PDT 24
Peak memory 215804 kb
Host smart-0a3fe361-978c-40e9-ba65-9566d7c593cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827068640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.82706864
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.347346177
Short name T1099
Test name
Test status
Simulation time 22329931 ps
CPU time 0.99 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 215692 kb
Host smart-549ff4ad-579b-4644-8481-44624631d9d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347346177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.34734617
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2933978180
Short name T1202
Test name
Test status
Simulation time 51366572 ps
CPU time 1.59 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 219564 kb
Host smart-c05e8b65-dbdc-4065-b78b-a93521b84b83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933978180 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.2933978180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3422987770
Short name T1175
Test name
Test status
Simulation time 44312126 ps
CPU time 1.06 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:46 AM PDT 24
Peak memory 215812 kb
Host smart-83ab5794-d0ad-4052-81b3-6d0c90c49f88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422987770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3422987770 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.3416029311
Short name T1077
Test name
Test status
Simulation time 16426631 ps
CPU time 0.81 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:46 AM PDT 24
Peak memory 215760 kb
Host smart-9facdc02-1072-474c-bfda-bf5a0c19b7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416029311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3416029311 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.498741528
Short name T155
Test name
Test status
Simulation time 130121517 ps
CPU time 1.46 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:46 AM PDT 24
Peak memory 215832 kb
Host smart-7dd39419-0005-4116-9a50-d08dc37256fd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498741528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial
_access.498741528 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1507160518
Short name T1121
Test name
Test status
Simulation time 14463471 ps
CPU time 0.75 seconds
Started Jul 01 10:46:07 AM PDT 24
Finished Jul 01 10:46:08 AM PDT 24
Peak memory 215772 kb
Host smart-07e0b63c-2570-458b-bb30-114de421819c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507160518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1507160518
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3301892941
Short name T166
Test name
Test status
Simulation time 149003426 ps
CPU time 1.6 seconds
Started Jul 01 10:45:35 AM PDT 24
Finished Jul 01 10:45:37 AM PDT 24
Peak memory 215696 kb
Host smart-940db3f3-e656-4eb4-b9d2-2fc328e5bdc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301892941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.3301892941 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3660374324
Short name T1101
Test name
Test status
Simulation time 57851433 ps
CPU time 1.66 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 219436 kb
Host smart-31762784-b237-4456-80e5-555ceba5d839
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660374324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.3660374324 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.1416393699
Short name T141
Test name
Test status
Simulation time 716718828 ps
CPU time 1.64 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 215872 kb
Host smart-0d871808-08fe-49aa-956f-fc21e7eb84e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416393699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1416393699 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.722576321
Short name T131
Test name
Test status
Simulation time 241493249 ps
CPU time 2.81 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 215808 kb
Host smart-f3411cb9-d18e-427c-82f5-770be03d993b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722576321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.722576
321 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.1359724455
Short name T1215
Test name
Test status
Simulation time 12928428 ps
CPU time 0.78 seconds
Started Jul 01 10:46:30 AM PDT 24
Finished Jul 01 10:46:31 AM PDT 24
Peak memory 215740 kb
Host smart-798481bb-9f48-4764-bf7b-4f5bad7d241e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359724455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1359724455 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.3014091933
Short name T1128
Test name
Test status
Simulation time 37922349 ps
CPU time 0.84 seconds
Started Jul 01 10:45:56 AM PDT 24
Finished Jul 01 10:45:58 AM PDT 24
Peak memory 215760 kb
Host smart-de22d9c6-ece1-455b-bae3-a6ff665025bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014091933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3014091933 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.3908369137
Short name T1093
Test name
Test status
Simulation time 32332956 ps
CPU time 0.79 seconds
Started Jul 01 10:46:09 AM PDT 24
Finished Jul 01 10:46:10 AM PDT 24
Peak memory 215656 kb
Host smart-eef1b691-6bd4-4e92-9501-10d7c87d23d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908369137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.3908369137 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.1296394305
Short name T136
Test name
Test status
Simulation time 44051554 ps
CPU time 0.8 seconds
Started Jul 01 10:45:59 AM PDT 24
Finished Jul 01 10:46:00 AM PDT 24
Peak memory 215684 kb
Host smart-dc135ff3-f118-40bb-b8f4-6ad6abf96af3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296394305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1296394305 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.2425233615
Short name T1075
Test name
Test status
Simulation time 15574892 ps
CPU time 0.82 seconds
Started Jul 01 10:46:29 AM PDT 24
Finished Jul 01 10:46:31 AM PDT 24
Peak memory 215768 kb
Host smart-9a5ea828-b757-4748-acc4-757b48434545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425233615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2425233615 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.923621986
Short name T176
Test name
Test status
Simulation time 22244189 ps
CPU time 0.83 seconds
Started Jul 01 10:45:59 AM PDT 24
Finished Jul 01 10:46:00 AM PDT 24
Peak memory 215668 kb
Host smart-b8504a10-8b79-4e4f-b6e1-3f95db87b62f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923621986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.923621986 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.1993171314
Short name T1078
Test name
Test status
Simulation time 46292366 ps
CPU time 0.82 seconds
Started Jul 01 10:45:57 AM PDT 24
Finished Jul 01 10:45:58 AM PDT 24
Peak memory 215816 kb
Host smart-1d6a6c04-18c8-48fa-a83b-56535d4406d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993171314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1993171314 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.2100278759
Short name T1172
Test name
Test status
Simulation time 73870163 ps
CPU time 0.8 seconds
Started Jul 01 10:46:20 AM PDT 24
Finished Jul 01 10:46:21 AM PDT 24
Peak memory 215680 kb
Host smart-254d20d5-ba8f-4f3b-959f-3d7b7473aa60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100278759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2100278759 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.3694947273
Short name T1104
Test name
Test status
Simulation time 79293804 ps
CPU time 0.79 seconds
Started Jul 01 10:46:15 AM PDT 24
Finished Jul 01 10:46:16 AM PDT 24
Peak memory 215736 kb
Host smart-055e48b3-b225-4842-9c9f-0909fbf7a79f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694947273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3694947273 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.3120942885
Short name T1114
Test name
Test status
Simulation time 28553063 ps
CPU time 0.79 seconds
Started Jul 01 10:46:26 AM PDT 24
Finished Jul 01 10:46:27 AM PDT 24
Peak memory 215640 kb
Host smart-94ff5d28-6329-4959-9a47-b736df928f9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120942885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3120942885 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3456822378
Short name T1187
Test name
Test status
Simulation time 791210105 ps
CPU time 9 seconds
Started Jul 01 10:45:35 AM PDT 24
Finished Jul 01 10:45:44 AM PDT 24
Peak memory 215800 kb
Host smart-eecfa2b6-8642-4a05-857c-76fb60c1f04a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456822378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3456822
378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.830575479
Short name T1139
Test name
Test status
Simulation time 1166755402 ps
CPU time 15.25 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:46:00 AM PDT 24
Peak memory 215824 kb
Host smart-3e711edb-bc4a-4ba5-b07a-cd43688429f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830575479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.83057547
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.553724177
Short name T1072
Test name
Test status
Simulation time 61202227 ps
CPU time 1.1 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 215816 kb
Host smart-95567342-344e-463d-8069-aa5fc9151585
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553724177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.55372417
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2818332166
Short name T139
Test name
Test status
Simulation time 23993907 ps
CPU time 1.74 seconds
Started Jul 01 10:46:22 AM PDT 24
Finished Jul 01 10:46:24 AM PDT 24
Peak memory 219400 kb
Host smart-10a6b159-ef01-404a-83c7-e1bb65eaeda2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818332166 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2818332166 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.4149416529
Short name T1162
Test name
Test status
Simulation time 51141906 ps
CPU time 1.15 seconds
Started Jul 01 10:46:07 AM PDT 24
Finished Jul 01 10:46:09 AM PDT 24
Peak memory 215864 kb
Host smart-56d00111-eed6-45d1-910c-3c2aeb652f73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149416529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.4149416529 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.607061266
Short name T1221
Test name
Test status
Simulation time 20981293 ps
CPU time 0.86 seconds
Started Jul 01 10:45:32 AM PDT 24
Finished Jul 01 10:45:34 AM PDT 24
Peak memory 215736 kb
Host smart-b1e49e93-4e93-4793-a3c2-31ed36a0772d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607061266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.607061266 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2312747498
Short name T154
Test name
Test status
Simulation time 148195901 ps
CPU time 1.52 seconds
Started Jul 01 10:45:32 AM PDT 24
Finished Jul 01 10:45:34 AM PDT 24
Peak memory 215856 kb
Host smart-9d749032-4915-4ccd-bc29-a19c81220bd6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312747498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.2312747498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3775130654
Short name T1143
Test name
Test status
Simulation time 10767732 ps
CPU time 0.8 seconds
Started Jul 01 10:45:31 AM PDT 24
Finished Jul 01 10:45:33 AM PDT 24
Peak memory 215704 kb
Host smart-d16eb7ff-15e3-45e5-be64-8ffeacda062f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775130654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3775130654
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.119169078
Short name T1135
Test name
Test status
Simulation time 41200821 ps
CPU time 1.35 seconds
Started Jul 01 10:45:31 AM PDT 24
Finished Jul 01 10:45:33 AM PDT 24
Peak memory 215696 kb
Host smart-dbe05ed8-1719-49de-ad87-bc2351ce6242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119169078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_
outstanding.119169078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.634944473
Short name T1224
Test name
Test status
Simulation time 85877538 ps
CPU time 1.3 seconds
Started Jul 01 10:45:55 AM PDT 24
Finished Jul 01 10:45:57 AM PDT 24
Peak memory 216448 kb
Host smart-9f4b1f03-8134-4c42-b7bb-e818a8f1382b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634944473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_e
rrors.634944473 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2130099684
Short name T102
Test name
Test status
Simulation time 199924360 ps
CPU time 1.94 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:49 AM PDT 24
Peak memory 219624 kb
Host smart-625ca467-b0cc-4247-aa58-3cf9b94b6128
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130099684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.2130099684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.2572978489
Short name T1071
Test name
Test status
Simulation time 158816687 ps
CPU time 1.69 seconds
Started Jul 01 10:45:36 AM PDT 24
Finished Jul 01 10:45:38 AM PDT 24
Peak memory 215976 kb
Host smart-92d7a8f4-f881-410c-b7ea-cf1f592db61e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572978489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.2572978489 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2998535839
Short name T1148
Test name
Test status
Simulation time 427283521 ps
CPU time 4.82 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 215840 kb
Host smart-0e31e793-7e89-418f-8b65-43b433f19cde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998535839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.29985
35839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.2917840473
Short name T1192
Test name
Test status
Simulation time 13956402 ps
CPU time 0.82 seconds
Started Jul 01 10:46:04 AM PDT 24
Finished Jul 01 10:46:06 AM PDT 24
Peak memory 215744 kb
Host smart-14b4d4a4-9e73-458b-868f-591a86e1a43e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917840473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2917840473 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.2346689780
Short name T1171
Test name
Test status
Simulation time 52681101 ps
CPU time 0.78 seconds
Started Jul 01 10:46:29 AM PDT 24
Finished Jul 01 10:46:30 AM PDT 24
Peak memory 215640 kb
Host smart-ac134634-09c5-4751-a12e-611561404644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346689780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2346689780 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.1360177828
Short name T1092
Test name
Test status
Simulation time 10846108 ps
CPU time 0.81 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:37 AM PDT 24
Peak memory 215860 kb
Host smart-a6e45c3f-5fcb-4a66-9761-2590170f106c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360177828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1360177828 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.3415336607
Short name T1095
Test name
Test status
Simulation time 23539904 ps
CPU time 0.79 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 215748 kb
Host smart-5b3416d8-53f9-4b45-ba55-9b8bba1d5132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415336607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3415336607 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.1813629001
Short name T1154
Test name
Test status
Simulation time 59220363 ps
CPU time 0.8 seconds
Started Jul 01 10:46:01 AM PDT 24
Finished Jul 01 10:46:03 AM PDT 24
Peak memory 215724 kb
Host smart-b4d201f9-80f4-422f-b7b2-c152cbec0b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813629001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1813629001 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.1903417395
Short name T1111
Test name
Test status
Simulation time 13312571 ps
CPU time 0.84 seconds
Started Jul 01 10:46:00 AM PDT 24
Finished Jul 01 10:46:02 AM PDT 24
Peak memory 215684 kb
Host smart-3ed26217-d291-4db5-a402-60d43d8323bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903417395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1903417395 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.2964552097
Short name T1206
Test name
Test status
Simulation time 18002173 ps
CPU time 0.87 seconds
Started Jul 01 10:46:03 AM PDT 24
Finished Jul 01 10:46:05 AM PDT 24
Peak memory 215660 kb
Host smart-955e0448-9e64-4808-b47d-3f02fde38aae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964552097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2964552097 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.4275518485
Short name T1222
Test name
Test status
Simulation time 81478481 ps
CPU time 0.86 seconds
Started Jul 01 10:46:19 AM PDT 24
Finished Jul 01 10:46:20 AM PDT 24
Peak memory 215704 kb
Host smart-44623fca-5970-4c53-8645-a13f14eafff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275518485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.4275518485 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.159119357
Short name T1191
Test name
Test status
Simulation time 42329827 ps
CPU time 0.74 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:39 AM PDT 24
Peak memory 215744 kb
Host smart-e2ba20d6-8ff0-406f-a936-c8ab3cdc3704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159119357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.159119357 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.3835432586
Short name T1134
Test name
Test status
Simulation time 30597797 ps
CPU time 0.77 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:36 AM PDT 24
Peak memory 215704 kb
Host smart-b1dc0769-901e-4602-b78e-d2a8cc196e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835432586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3835432586 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1489920405
Short name T1127
Test name
Test status
Simulation time 47871293 ps
CPU time 1.61 seconds
Started Jul 01 10:46:16 AM PDT 24
Finished Jul 01 10:46:18 AM PDT 24
Peak memory 219652 kb
Host smart-715928fe-1b91-4282-bd13-c08ae3722302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489920405 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.1489920405 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.759931072
Short name T1123
Test name
Test status
Simulation time 38948611 ps
CPU time 0.99 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 215644 kb
Host smart-b45928bf-e8a6-4124-a177-314bfe7a37d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759931072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.759931072 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.4149249433
Short name T1136
Test name
Test status
Simulation time 27703882 ps
CPU time 0.81 seconds
Started Jul 01 10:46:05 AM PDT 24
Finished Jul 01 10:46:06 AM PDT 24
Peak memory 215672 kb
Host smart-4de18747-d9f3-4ee8-aa66-3a48a1df5d2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149249433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.4149249433 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1263172516
Short name T1085
Test name
Test status
Simulation time 269464519 ps
CPU time 1.82 seconds
Started Jul 01 10:45:46 AM PDT 24
Finished Jul 01 10:45:51 AM PDT 24
Peak memory 216104 kb
Host smart-ac19b0fc-aa51-46e0-8e1e-c411b4cbc8b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263172516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.1263172516 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.455193057
Short name T98
Test name
Test status
Simulation time 372819943 ps
CPU time 2.57 seconds
Started Jul 01 10:45:36 AM PDT 24
Finished Jul 01 10:45:39 AM PDT 24
Peak memory 218312 kb
Host smart-457c79e2-f45f-4571-8194-5b564317ac37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455193057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_
shadow_reg_errors_with_csr_rw.455193057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.644158560
Short name T1179
Test name
Test status
Simulation time 85655033 ps
CPU time 2.76 seconds
Started Jul 01 10:45:38 AM PDT 24
Finished Jul 01 10:45:42 AM PDT 24
Peak memory 215956 kb
Host smart-2c4dffb2-68ac-42a0-869d-d35e71640298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644158560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.644158560 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1707113839
Short name T189
Test name
Test status
Simulation time 450230721 ps
CPU time 4.06 seconds
Started Jul 01 10:45:37 AM PDT 24
Finished Jul 01 10:45:41 AM PDT 24
Peak memory 215832 kb
Host smart-28837ce3-02db-4b60-ada9-a9969f40d810
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707113839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.17071
13839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3456222203
Short name T1157
Test name
Test status
Simulation time 87626068 ps
CPU time 1.61 seconds
Started Jul 01 10:45:38 AM PDT 24
Finished Jul 01 10:45:40 AM PDT 24
Peak memory 218760 kb
Host smart-43a8adf6-e2aa-4614-9363-16007a36522a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456222203 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3456222203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3021337094
Short name T1210
Test name
Test status
Simulation time 29218257 ps
CPU time 1.16 seconds
Started Jul 01 10:45:47 AM PDT 24
Finished Jul 01 10:45:51 AM PDT 24
Peak memory 215804 kb
Host smart-f7fb8041-dabe-4012-bd3a-f23526785090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021337094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3021337094 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.758856346
Short name T1112
Test name
Test status
Simulation time 30888683 ps
CPU time 0.79 seconds
Started Jul 01 10:45:38 AM PDT 24
Finished Jul 01 10:45:39 AM PDT 24
Peak memory 215740 kb
Host smart-d9b316a6-f116-4be9-ba81-b47f6111d8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758856346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.758856346 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3889910534
Short name T1102
Test name
Test status
Simulation time 189659348 ps
CPU time 1.67 seconds
Started Jul 01 10:45:42 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 215804 kb
Host smart-29f15eb4-819b-4dde-bad5-9dc270a969cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889910534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.3889910534 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1742220054
Short name T107
Test name
Test status
Simulation time 30658956 ps
CPU time 1.12 seconds
Started Jul 01 10:45:38 AM PDT 24
Finished Jul 01 10:45:40 AM PDT 24
Peak memory 216120 kb
Host smart-dfab18a7-26bd-4a7d-8b29-b7e9061d1a6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742220054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.1742220054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3629449887
Short name T1109
Test name
Test status
Simulation time 74030746 ps
CPU time 2.32 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:41 AM PDT 24
Peak memory 215908 kb
Host smart-62bbaeac-9310-4dee-8db2-70536996056d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629449887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3629449887 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.2787146241
Short name T1184
Test name
Test status
Simulation time 83817082 ps
CPU time 2.59 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:46 AM PDT 24
Peak memory 215752 kb
Host smart-463af358-dab2-4216-b19b-a99307a5a2a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787146241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.27871
46241 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.260590814
Short name T1116
Test name
Test status
Simulation time 80494126 ps
CPU time 2.47 seconds
Started Jul 01 10:45:51 AM PDT 24
Finished Jul 01 10:45:54 AM PDT 24
Peak memory 216936 kb
Host smart-7e6c70a6-7038-4a24-84db-801d32ed9b1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260590814 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.260590814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.269852050
Short name T1180
Test name
Test status
Simulation time 110621397 ps
CPU time 1.2 seconds
Started Jul 01 10:45:38 AM PDT 24
Finished Jul 01 10:45:39 AM PDT 24
Peak memory 215832 kb
Host smart-56c5fb5b-1d77-4a0e-a7d2-934dbf39c5c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269852050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.269852050 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.1489406038
Short name T1194
Test name
Test status
Simulation time 104362070 ps
CPU time 0.87 seconds
Started Jul 01 10:45:41 AM PDT 24
Finished Jul 01 10:45:45 AM PDT 24
Peak memory 215676 kb
Host smart-423d1ca7-4c5c-4eda-8c0b-0faf95a29b50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489406038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1489406038 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3767276574
Short name T167
Test name
Test status
Simulation time 114470734 ps
CPU time 1.62 seconds
Started Jul 01 10:46:28 AM PDT 24
Finished Jul 01 10:46:35 AM PDT 24
Peak memory 215764 kb
Host smart-dcad8429-7eca-47dd-b4c1-183ac0ded811
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767276574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.3767276574 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2498878220
Short name T1182
Test name
Test status
Simulation time 366074824 ps
CPU time 1.19 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:42 AM PDT 24
Peak memory 216092 kb
Host smart-0bad0bec-a006-498f-b05a-2fd14568ab26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498878220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.2498878220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.8230144
Short name T1115
Test name
Test status
Simulation time 282664152 ps
CPU time 1.8 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:43 AM PDT 24
Peak memory 218576 kb
Host smart-fd0af1af-8f69-45f1-9e93-78c38ae0a1dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8230144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_sh
adow_reg_errors_with_csr_rw.8230144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.4056459387
Short name T1074
Test name
Test status
Simulation time 255303563 ps
CPU time 1.62 seconds
Started Jul 01 10:45:39 AM PDT 24
Finished Jul 01 10:45:42 AM PDT 24
Peak memory 215864 kb
Host smart-e9a26d41-2668-4757-ac3d-13592fd36713
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056459387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.4056459387 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1130224486
Short name T179
Test name
Test status
Simulation time 1271734204 ps
CPU time 4.98 seconds
Started Jul 01 10:45:56 AM PDT 24
Finished Jul 01 10:46:02 AM PDT 24
Peak memory 215888 kb
Host smart-79eac06b-751c-4c3c-b9e5-8ea0e119fd63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130224486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.11302
24486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3948215968
Short name T1096
Test name
Test status
Simulation time 75363200 ps
CPU time 2.34 seconds
Started Jul 01 10:45:49 AM PDT 24
Finished Jul 01 10:45:53 AM PDT 24
Peak memory 221616 kb
Host smart-b15ade1a-fd73-4969-b3af-fc72ce983aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948215968 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3948215968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.4107683897
Short name T1190
Test name
Test status
Simulation time 105664840 ps
CPU time 1.2 seconds
Started Jul 01 10:45:45 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 215860 kb
Host smart-15c0667e-8f80-4c9f-b392-28f023f3637f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107683897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.4107683897 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.3629764894
Short name T135
Test name
Test status
Simulation time 47434705 ps
CPU time 0.79 seconds
Started Jul 01 10:46:30 AM PDT 24
Finished Jul 01 10:46:32 AM PDT 24
Peak memory 215756 kb
Host smart-4a481dec-e987-43d5-80c1-9abe4f3c2448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629764894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3629764894 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.542073558
Short name T1084
Test name
Test status
Simulation time 32628888 ps
CPU time 2.02 seconds
Started Jul 01 10:45:43 AM PDT 24
Finished Jul 01 10:45:49 AM PDT 24
Peak memory 215728 kb
Host smart-e1d4b51e-9d74-49fa-ae03-24db045dda5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542073558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_
outstanding.542073558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3157405653
Short name T1089
Test name
Test status
Simulation time 29229018 ps
CPU time 0.98 seconds
Started Jul 01 10:45:46 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 216036 kb
Host smart-5a171e3a-1e14-47cc-a489-768e7e3b69df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157405653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.3157405653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3528571580
Short name T1212
Test name
Test status
Simulation time 105858066 ps
CPU time 1.89 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 219676 kb
Host smart-d3d41618-e803-481b-b731-7b99d5f8c2cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528571580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.3528571580 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1956609146
Short name T1203
Test name
Test status
Simulation time 236994047 ps
CPU time 2.01 seconds
Started Jul 01 10:46:25 AM PDT 24
Finished Jul 01 10:46:28 AM PDT 24
Peak memory 215916 kb
Host smart-a3fce11f-b184-44b2-be56-6c484ff600ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956609146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1956609146 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2341684160
Short name T1181
Test name
Test status
Simulation time 93412950 ps
CPU time 4.1 seconds
Started Jul 01 10:45:47 AM PDT 24
Finished Jul 01 10:45:54 AM PDT 24
Peak memory 215832 kb
Host smart-f818792f-846d-48a6-9db4-bd7acc574162
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341684160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.23416
84160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3396557372
Short name T1159
Test name
Test status
Simulation time 48516247 ps
CPU time 1.79 seconds
Started Jul 01 10:45:48 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 220928 kb
Host smart-b301f029-ca84-4d13-b5f2-ee6530972c93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396557372 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3396557372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.3738840407
Short name T1130
Test name
Test status
Simulation time 21040483 ps
CPU time 1.08 seconds
Started Jul 01 10:46:09 AM PDT 24
Finished Jul 01 10:46:11 AM PDT 24
Peak memory 215772 kb
Host smart-bf70c0b6-4762-49ff-ab7f-b7c7d82f4b2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738840407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3738840407 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.809981372
Short name T178
Test name
Test status
Simulation time 24527208 ps
CPU time 0.82 seconds
Started Jul 01 10:45:51 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 215668 kb
Host smart-e74f6441-b844-4aa1-9563-b615c00af4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809981372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.809981372 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2897803251
Short name T1149
Test name
Test status
Simulation time 59778911 ps
CPU time 1.66 seconds
Started Jul 01 10:45:44 AM PDT 24
Finished Jul 01 10:45:50 AM PDT 24
Peak memory 215828 kb
Host smart-3477a543-5287-45f6-8a62-03240fb9031e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897803251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.2897803251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2746334634
Short name T1113
Test name
Test status
Simulation time 149116241 ps
CPU time 3.37 seconds
Started Jul 01 10:46:14 AM PDT 24
Finished Jul 01 10:46:18 AM PDT 24
Peak memory 215896 kb
Host smart-4e453cc7-8659-4ba8-9184-e1c2b4804f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746334634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2746334634 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3933897709
Short name T132
Test name
Test status
Simulation time 895461292 ps
CPU time 3.09 seconds
Started Jul 01 10:45:45 AM PDT 24
Finished Jul 01 10:45:52 AM PDT 24
Peak memory 215824 kb
Host smart-5211e6a7-c744-4bf6-a517-504955ced648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933897709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.39338
97709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.288716840
Short name T565
Test name
Test status
Simulation time 20235465 ps
CPU time 0.89 seconds
Started Jul 01 12:05:54 PM PDT 24
Finished Jul 01 12:05:56 PM PDT 24
Peak memory 217928 kb
Host smart-5f1213c3-a6aa-489d-ad44-2c78aa70aa46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288716840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.288716840 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.3394455780
Short name T360
Test name
Test status
Simulation time 37458451709 ps
CPU time 230.84 seconds
Started Jul 01 12:05:41 PM PDT 24
Finished Jul 01 12:09:33 PM PDT 24
Peak memory 242676 kb
Host smart-0535fff7-0272-4d6e-9a42-11c9b6c9c2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394455780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3394455780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.3501560658
Short name T185
Test name
Test status
Simulation time 41101622976 ps
CPU time 298.25 seconds
Started Jul 01 12:05:48 PM PDT 24
Finished Jul 01 12:10:47 PM PDT 24
Peak memory 248236 kb
Host smart-f7a4b332-bbfd-4c56-a32d-0f9af48a4bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501560658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.3501560658 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.1212415414
Short name T441
Test name
Test status
Simulation time 13062835650 ps
CPU time 619.34 seconds
Started Jul 01 12:05:22 PM PDT 24
Finished Jul 01 12:15:42 PM PDT 24
Peak memory 232920 kb
Host smart-8e309268-13ca-448d-ac1f-51a2fbefade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212415414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1212415414 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.3366717133
Short name T976
Test name
Test status
Simulation time 2846708448 ps
CPU time 46.53 seconds
Started Jul 01 12:05:47 PM PDT 24
Finished Jul 01 12:06:34 PM PDT 24
Peak memory 226932 kb
Host smart-c49f7465-e343-4d38-b787-0ca210d53419
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3366717133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3366717133 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.2267307547
Short name T579
Test name
Test status
Simulation time 2210068114 ps
CPU time 20.82 seconds
Started Jul 01 12:05:44 PM PDT 24
Finished Jul 01 12:06:06 PM PDT 24
Peak memory 218224 kb
Host smart-bc100980-2cbc-43ba-9341-ed15512bd42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267307547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2267307547 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.3773330441
Short name T273
Test name
Test status
Simulation time 463823863 ps
CPU time 4.16 seconds
Started Jul 01 12:05:46 PM PDT 24
Finished Jul 01 12:05:52 PM PDT 24
Peak memory 218036 kb
Host smart-e6a4cb55-d0e8-426b-9a71-2ead0bba062e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773330441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3773330441 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3629576630
Short name T513
Test name
Test status
Simulation time 49388283072 ps
CPU time 2755.9 seconds
Started Jul 01 12:05:18 PM PDT 24
Finished Jul 01 12:51:15 PM PDT 24
Peak memory 458680 kb
Host smart-1897c282-266e-4db9-b7b0-8dbd768098c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629576630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3629576630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.1179760135
Short name T85
Test name
Test status
Simulation time 3318625261 ps
CPU time 69.99 seconds
Started Jul 01 12:05:47 PM PDT 24
Finished Jul 01 12:06:58 PM PDT 24
Peak memory 231592 kb
Host smart-9dfb9d09-37c9-49c4-85e3-fb0884f35f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179760135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1179760135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.3934526922
Short name T121
Test name
Test status
Simulation time 29130839953 ps
CPU time 51.47 seconds
Started Jul 01 12:05:54 PM PDT 24
Finished Jul 01 12:06:46 PM PDT 24
Peak memory 256112 kb
Host smart-7cba8cdc-7d7d-4a6b-8069-1fa76d624036
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934526922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3934526922 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.254839034
Short name T1034
Test name
Test status
Simulation time 8762820555 ps
CPU time 275.2 seconds
Started Jul 01 12:05:17 PM PDT 24
Finished Jul 01 12:09:52 PM PDT 24
Peak memory 246472 kb
Host smart-9504a382-29b6-417f-ac69-a53c9072dd2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254839034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.254839034 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.104615602
Short name T582
Test name
Test status
Simulation time 21524678441 ps
CPU time 92.92 seconds
Started Jul 01 12:05:22 PM PDT 24
Finished Jul 01 12:06:55 PM PDT 24
Peak memory 218260 kb
Host smart-122052a3-85b7-491c-b2c4-4ab94c6dce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104615602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.104615602 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.694635494
Short name T86
Test name
Test status
Simulation time 169306862386 ps
CPU time 1637.12 seconds
Started Jul 01 12:05:44 PM PDT 24
Finished Jul 01 12:33:02 PM PDT 24
Peak memory 357780 kb
Host smart-5f746815-59af-4a09-a75d-8aa17b49569e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=694635494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.694635494 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_stress_all_with_rand_reset.1618628775
Short name T138
Test name
Test status
Simulation time 61498131162 ps
CPU time 1128.21 seconds
Started Jul 01 12:05:44 PM PDT 24
Finished Jul 01 12:24:33 PM PDT 24
Peak memory 287612 kb
Host smart-667559f6-6191-4128-adae-fe4a40b3c6d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618628775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.1618628775 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.1548967284
Short name T258
Test name
Test status
Simulation time 277407263 ps
CPU time 6.74 seconds
Started Jul 01 12:05:44 PM PDT 24
Finished Jul 01 12:05:52 PM PDT 24
Peak memory 218984 kb
Host smart-8347eae9-62ac-4ae6-bd16-324f8de8c951
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548967284 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.1548967284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.713271837
Short name T892
Test name
Test status
Simulation time 450026772 ps
CPU time 5.86 seconds
Started Jul 01 12:05:33 PM PDT 24
Finished Jul 01 12:05:39 PM PDT 24
Peak memory 218120 kb
Host smart-779cfcab-c8f8-49f4-852f-a0c4b461dc77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713271837 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.kmac_test_vectors_kmac_xof.713271837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.3418425848
Short name T674
Test name
Test status
Simulation time 81252907453 ps
CPU time 1948.59 seconds
Started Jul 01 12:05:18 PM PDT 24
Finished Jul 01 12:37:47 PM PDT 24
Peak memory 396236 kb
Host smart-0c79bd9e-40ee-4731-b393-9413f87b9acc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3418425848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.3418425848 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.3898994534
Short name T202
Test name
Test status
Simulation time 1117117921181 ps
CPU time 2079.91 seconds
Started Jul 01 12:05:23 PM PDT 24
Finished Jul 01 12:40:04 PM PDT 24
Peak memory 377444 kb
Host smart-7fd8c341-9908-4c7d-81c7-3a8f034fd1c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3898994534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3898994534 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.643121287
Short name T434
Test name
Test status
Simulation time 29746423010 ps
CPU time 1569.65 seconds
Started Jul 01 12:05:23 PM PDT 24
Finished Jul 01 12:31:33 PM PDT 24
Peak memory 346796 kb
Host smart-1b436d7f-5e0f-4b7e-a383-2b9819e643e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=643121287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.643121287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.1913269175
Short name T266
Test name
Test status
Simulation time 40437031873 ps
CPU time 1176.32 seconds
Started Jul 01 12:05:23 PM PDT 24
Finished Jul 01 12:25:00 PM PDT 24
Peak memory 299028 kb
Host smart-70c3741d-2916-4162-a55c-885842622dd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1913269175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1913269175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.1380890425
Short name T314
Test name
Test status
Simulation time 887071678974 ps
CPU time 5411.41 seconds
Started Jul 01 12:05:28 PM PDT 24
Finished Jul 01 01:35:40 PM PDT 24
Peak memory 636532 kb
Host smart-155817b1-c764-433d-864a-4af69abd1a3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1380890425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1380890425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.21425167
Short name T845
Test name
Test status
Simulation time 106664766136 ps
CPU time 4405.89 seconds
Started Jul 01 12:05:44 PM PDT 24
Finished Jul 01 01:19:11 PM PDT 24
Peak memory 559752 kb
Host smart-1b0d35e7-5093-49a0-9fa9-b0b66d73f695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=21425167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.21425167 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.3725609656
Short name T353
Test name
Test status
Simulation time 14004475 ps
CPU time 0.85 seconds
Started Jul 01 12:06:20 PM PDT 24
Finished Jul 01 12:06:21 PM PDT 24
Peak memory 217856 kb
Host smart-08236587-94fa-4b8b-b549-9baf413e17a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725609656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3725609656 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.3452525881
Short name T280
Test name
Test status
Simulation time 1436356578 ps
CPU time 60.76 seconds
Started Jul 01 12:05:58 PM PDT 24
Finished Jul 01 12:07:01 PM PDT 24
Peak memory 229008 kb
Host smart-78142541-9462-4f79-b458-46dc29f9c9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452525881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3452525881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.1556252419
Short name T923
Test name
Test status
Simulation time 1315944732 ps
CPU time 12.65 seconds
Started Jul 01 12:05:57 PM PDT 24
Finished Jul 01 12:06:12 PM PDT 24
Peak memory 226252 kb
Host smart-a0a54d66-fab0-453d-b130-d77dad4c0beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556252419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1556252419 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.3078445801
Short name T395
Test name
Test status
Simulation time 106419098644 ps
CPU time 1286.32 seconds
Started Jul 01 12:05:56 PM PDT 24
Finished Jul 01 12:27:24 PM PDT 24
Peak memory 237436 kb
Host smart-5dc7b9f5-bb16-4985-af9e-0ca604019f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078445801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3078445801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.4015901324
Short name T55
Test name
Test status
Simulation time 19969292 ps
CPU time 0.95 seconds
Started Jul 01 12:06:08 PM PDT 24
Finished Jul 01 12:06:09 PM PDT 24
Peak memory 217852 kb
Host smart-59b65ef1-0a3f-4c1b-a4b0-c355fb48e3d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4015901324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.4015901324 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.214653942
Short name T651
Test name
Test status
Simulation time 159060698 ps
CPU time 0.97 seconds
Started Jul 01 12:06:14 PM PDT 24
Finished Jul 01 12:06:16 PM PDT 24
Peak memory 217724 kb
Host smart-84bdc7e7-5f6b-4032-b4f5-1731592408d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=214653942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.214653942 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.4061861347
Short name T738
Test name
Test status
Simulation time 2694130323 ps
CPU time 48.53 seconds
Started Jul 01 12:06:14 PM PDT 24
Finished Jul 01 12:07:03 PM PDT 24
Peak memory 219004 kb
Host smart-94448738-ea87-4bc3-a8ab-50281be10de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061861347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.4061861347 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.3094910578
Short name T1057
Test name
Test status
Simulation time 9078169275 ps
CPU time 66.82 seconds
Started Jul 01 12:06:05 PM PDT 24
Finished Jul 01 12:07:12 PM PDT 24
Peak memory 229656 kb
Host smart-21c1d016-ee54-45d9-ae8f-16a37d0d0c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094910578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.3094910578 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.215505676
Short name T844
Test name
Test status
Simulation time 2164009103 ps
CPU time 73.14 seconds
Started Jul 01 12:06:02 PM PDT 24
Finished Jul 01 12:07:16 PM PDT 24
Peak memory 242716 kb
Host smart-b86f3dd0-ac95-4360-b40b-360e28759981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215505676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.215505676 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.1298017409
Short name T988
Test name
Test status
Simulation time 356075159 ps
CPU time 2.95 seconds
Started Jul 01 12:06:03 PM PDT 24
Finished Jul 01 12:06:07 PM PDT 24
Peak memory 218020 kb
Host smart-1ceb038a-1e2a-4fca-9aa7-59d5d9ececdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298017409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1298017409 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.637349569
Short name T366
Test name
Test status
Simulation time 92681568562 ps
CPU time 830.66 seconds
Started Jul 01 12:05:55 PM PDT 24
Finished Jul 01 12:19:47 PM PDT 24
Peak memory 287524 kb
Host smart-c8c96c6c-0c08-4c02-8c82-5980965d6c3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637349569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and
_output.637349569 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.4031386480
Short name T588
Test name
Test status
Simulation time 29979934686 ps
CPU time 238.94 seconds
Started Jul 01 12:06:04 PM PDT 24
Finished Jul 01 12:10:04 PM PDT 24
Peak memory 244644 kb
Host smart-65fcc5b5-45a9-410f-b00d-6a9c78777bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031386480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.4031386480 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sideload.2037897562
Short name T127
Test name
Test status
Simulation time 4976308973 ps
CPU time 187.39 seconds
Started Jul 01 12:05:58 PM PDT 24
Finished Jul 01 12:09:07 PM PDT 24
Peak memory 239492 kb
Host smart-943f2b43-ed93-4624-8776-ba9f30cc41de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037897562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2037897562 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.3975400798
Short name T606
Test name
Test status
Simulation time 2616819251 ps
CPU time 13.48 seconds
Started Jul 01 12:05:56 PM PDT 24
Finished Jul 01 12:06:11 PM PDT 24
Peak memory 222772 kb
Host smart-30455e0a-3344-4a2c-9953-9899a9abd894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975400798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3975400798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.2929234719
Short name T867
Test name
Test status
Simulation time 10659257659 ps
CPU time 172.65 seconds
Started Jul 01 12:06:18 PM PDT 24
Finished Jul 01 12:09:12 PM PDT 24
Peak memory 242864 kb
Host smart-ea4a8ea4-cc7c-40c3-8f09-8c7ce10c8bb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2929234719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2929234719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_stress_all_with_rand_reset.738576618
Short name T70
Test name
Test status
Simulation time 277981431893 ps
CPU time 974.16 seconds
Started Jul 01 12:06:18 PM PDT 24
Finished Jul 01 12:22:33 PM PDT 24
Peak memory 291620 kb
Host smart-e31cef66-a7bf-4d0a-94b6-a9b0d4fd1be0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738576618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_rand_reset.738576618 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.446320320
Short name T669
Test name
Test status
Simulation time 381649341 ps
CPU time 6.72 seconds
Started Jul 01 12:05:57 PM PDT 24
Finished Jul 01 12:06:06 PM PDT 24
Peak memory 218028 kb
Host smart-e1b681a6-790d-4507-9c2d-d696ac2e6ad2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446320320 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.kmac_test_vectors_kmac.446320320 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.3036996881
Short name T911
Test name
Test status
Simulation time 254770776 ps
CPU time 6.05 seconds
Started Jul 01 12:05:57 PM PDT 24
Finished Jul 01 12:06:05 PM PDT 24
Peak memory 218160 kb
Host smart-a3dd0b12-ffae-48d2-8450-297c9ae1d945
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036996881 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3036996881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.2434210011
Short name T702
Test name
Test status
Simulation time 190676088642 ps
CPU time 2226.53 seconds
Started Jul 01 12:05:56 PM PDT 24
Finished Jul 01 12:43:05 PM PDT 24
Peak memory 389980 kb
Host smart-1fb984a4-edce-48f3-a5a8-b1fa0c701465
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2434210011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2434210011 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.770488898
Short name T215
Test name
Test status
Simulation time 128336628439 ps
CPU time 2197.23 seconds
Started Jul 01 12:05:56 PM PDT 24
Finished Jul 01 12:42:36 PM PDT 24
Peak memory 391488 kb
Host smart-6e7b5d2b-7315-475e-b878-ee9f4a62d957
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=770488898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.770488898 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.2242599909
Short name T947
Test name
Test status
Simulation time 111743684476 ps
CPU time 1735.21 seconds
Started Jul 01 12:06:02 PM PDT 24
Finished Jul 01 12:34:58 PM PDT 24
Peak memory 334268 kb
Host smart-ed56b0d1-be41-43f6-afbb-0e2d0273a8d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2242599909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2242599909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.169252896
Short name T707
Test name
Test status
Simulation time 34033350819 ps
CPU time 1270.18 seconds
Started Jul 01 12:05:57 PM PDT 24
Finished Jul 01 12:27:09 PM PDT 24
Peak memory 297652 kb
Host smart-b91c19da-e743-4103-996d-6dbc7aa67ec1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=169252896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.169252896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.492185856
Short name T768
Test name
Test status
Simulation time 2016541265283 ps
CPU time 7153.48 seconds
Started Jul 01 12:05:57 PM PDT 24
Finished Jul 01 02:05:14 PM PDT 24
Peak memory 672448 kb
Host smart-0040302d-89ab-4e95-9f13-3da403176523
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=492185856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.492185856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.3910461874
Short name T868
Test name
Test status
Simulation time 920477280658 ps
CPU time 5476 seconds
Started Jul 01 12:05:56 PM PDT 24
Finished Jul 01 01:37:16 PM PDT 24
Peak memory 572784 kb
Host smart-64bae6dd-a1d4-484d-890e-b424c8f04dfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3910461874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3910461874 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.2389548916
Short name T733
Test name
Test status
Simulation time 10713805 ps
CPU time 0.8 seconds
Started Jul 01 12:10:24 PM PDT 24
Finished Jul 01 12:10:25 PM PDT 24
Peak memory 217936 kb
Host smart-d752fa00-91f0-4c43-9f08-c6138e4c72fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389548916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2389548916 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.350829098
Short name T771
Test name
Test status
Simulation time 24672443464 ps
CPU time 273.8 seconds
Started Jul 01 12:10:17 PM PDT 24
Finished Jul 01 12:14:51 PM PDT 24
Peak memory 245424 kb
Host smart-3982bd57-a3ba-46bb-95d7-90cfefa4d578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350829098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.350829098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.2829835829
Short name T87
Test name
Test status
Simulation time 51280578545 ps
CPU time 673.71 seconds
Started Jul 01 12:10:01 PM PDT 24
Finished Jul 01 12:21:16 PM PDT 24
Peak memory 233620 kb
Host smart-ef9071cd-0943-494e-a6e3-9fa2fdd51f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829835829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.2829835829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.1344231408
Short name T123
Test name
Test status
Simulation time 134481922 ps
CPU time 1.26 seconds
Started Jul 01 12:10:18 PM PDT 24
Finished Jul 01 12:10:20 PM PDT 24
Peak memory 217960 kb
Host smart-a5bc3b1f-b6d0-4cfe-90e9-73bc9d405a1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1344231408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1344231408 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.349913387
Short name T969
Test name
Test status
Simulation time 4269999072 ps
CPU time 34.16 seconds
Started Jul 01 12:10:20 PM PDT 24
Finished Jul 01 12:10:55 PM PDT 24
Peak memory 226168 kb
Host smart-45e994b5-55ca-497a-ba70-3b712fb93b23
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=349913387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.349913387 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.1343024883
Short name T849
Test name
Test status
Simulation time 36094538811 ps
CPU time 157.17 seconds
Started Jul 01 12:10:20 PM PDT 24
Finished Jul 01 12:12:57 PM PDT 24
Peak memory 236520 kb
Host smart-c2d72ce3-4c61-4265-9dd0-e5561ca7c01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343024883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1343024883 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.1427034876
Short name T21
Test name
Test status
Simulation time 12437945731 ps
CPU time 332.58 seconds
Started Jul 01 12:10:19 PM PDT 24
Finished Jul 01 12:15:52 PM PDT 24
Peak memory 259000 kb
Host smart-23e9cb05-c9b0-42c2-97ff-f911fd978a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427034876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1427034876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.1299357480
Short name T623
Test name
Test status
Simulation time 7739815768 ps
CPU time 12.19 seconds
Started Jul 01 12:10:19 PM PDT 24
Finished Jul 01 12:10:31 PM PDT 24
Peak memory 218204 kb
Host smart-84587803-c3cb-4382-9fe5-9dcbc0cf0174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299357480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1299357480 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.3775229643
Short name T75
Test name
Test status
Simulation time 920419742 ps
CPU time 23.48 seconds
Started Jul 01 12:10:19 PM PDT 24
Finished Jul 01 12:10:43 PM PDT 24
Peak memory 233648 kb
Host smart-67eb9b8b-3cf7-490b-aeab-962f0d9965fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775229643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3775229643 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.2878815069
Short name T152
Test name
Test status
Simulation time 98385349584 ps
CPU time 2654.52 seconds
Started Jul 01 12:09:57 PM PDT 24
Finished Jul 01 12:54:12 PM PDT 24
Peak memory 436728 kb
Host smart-049b825f-e74a-4524-8867-242ba046a1a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878815069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.2878815069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.1126936378
Short name T625
Test name
Test status
Simulation time 20386133604 ps
CPU time 408.96 seconds
Started Jul 01 12:09:56 PM PDT 24
Finished Jul 01 12:16:46 PM PDT 24
Peak memory 251808 kb
Host smart-f1587010-2b8c-4e91-bd87-e9023ac01e9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126936378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1126936378 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.3133179944
Short name T790
Test name
Test status
Simulation time 4353069521 ps
CPU time 23.61 seconds
Started Jul 01 12:09:58 PM PDT 24
Finished Jul 01 12:10:22 PM PDT 24
Peak memory 218648 kb
Host smart-65fa589d-67b9-4515-9f34-be76e6b208bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133179944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3133179944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.57447619
Short name T19
Test name
Test status
Simulation time 9070906706 ps
CPU time 53.61 seconds
Started Jul 01 12:10:23 PM PDT 24
Finished Jul 01 12:11:17 PM PDT 24
Peak memory 226404 kb
Host smart-42ed9788-3620-4ea2-935e-65cf2ee9c5fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=57447619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.57447619 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.494658007
Short name T560
Test name
Test status
Simulation time 249063609 ps
CPU time 6.14 seconds
Started Jul 01 12:10:08 PM PDT 24
Finished Jul 01 12:10:15 PM PDT 24
Peak memory 218108 kb
Host smart-d3c02f05-3c78-460b-aed0-99365eb22c8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494658007 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.kmac_test_vectors_kmac.494658007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.3814179953
Short name T146
Test name
Test status
Simulation time 340160346 ps
CPU time 5.57 seconds
Started Jul 01 12:10:07 PM PDT 24
Finished Jul 01 12:10:13 PM PDT 24
Peak memory 219092 kb
Host smart-c3d5268c-d5b5-4318-8abd-bd4ba945e7d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814179953 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.3814179953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.589600134
Short name T323
Test name
Test status
Simulation time 20720260308 ps
CPU time 1886.8 seconds
Started Jul 01 12:10:04 PM PDT 24
Finished Jul 01 12:41:31 PM PDT 24
Peak memory 388524 kb
Host smart-96b7036d-2f12-43e4-adc1-165ebf3b49b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=589600134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.589600134 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.2939957382
Short name T922
Test name
Test status
Simulation time 30368104073 ps
CPU time 1881.46 seconds
Started Jul 01 12:10:02 PM PDT 24
Finished Jul 01 12:41:25 PM PDT 24
Peak memory 382140 kb
Host smart-012b73d2-7926-4a0f-82b8-26475201d7d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2939957382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.2939957382 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.2285801000
Short name T916
Test name
Test status
Simulation time 64310025070 ps
CPU time 1498.26 seconds
Started Jul 01 12:10:03 PM PDT 24
Finished Jul 01 12:35:02 PM PDT 24
Peak memory 344052 kb
Host smart-54573d7e-1a78-421e-9c82-13ae70855a3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2285801000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.2285801000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.1456826085
Short name T277
Test name
Test status
Simulation time 204722286668 ps
CPU time 1345.51 seconds
Started Jul 01 12:10:00 PM PDT 24
Finished Jul 01 12:32:27 PM PDT 24
Peak memory 296720 kb
Host smart-0ff2cd56-b82b-4422-9ac8-5e1a382e6af2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1456826085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.1456826085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.3430091860
Short name T719
Test name
Test status
Simulation time 312173472384 ps
CPU time 6147.63 seconds
Started Jul 01 12:10:08 PM PDT 24
Finished Jul 01 01:52:37 PM PDT 24
Peak memory 655780 kb
Host smart-a9791a08-7ce4-4e77-94fb-4629e4570081
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3430091860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.3430091860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_alert_test.303335730
Short name T814
Test name
Test status
Simulation time 23100069 ps
CPU time 0.8 seconds
Started Jul 01 12:10:38 PM PDT 24
Finished Jul 01 12:10:40 PM PDT 24
Peak memory 217812 kb
Host smart-b2b80154-1b1d-4cd8-8ed3-324316a7663c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303335730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.303335730 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.2964000457
Short name T915
Test name
Test status
Simulation time 22516656182 ps
CPU time 244.09 seconds
Started Jul 01 12:10:33 PM PDT 24
Finished Jul 01 12:14:38 PM PDT 24
Peak memory 244268 kb
Host smart-49b94149-de54-412c-8329-2d4863dc303d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964000457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2964000457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.4022751422
Short name T1050
Test name
Test status
Simulation time 37911355478 ps
CPU time 325.31 seconds
Started Jul 01 12:10:24 PM PDT 24
Finished Jul 01 12:15:50 PM PDT 24
Peak memory 230420 kb
Host smart-7f034563-01d8-491b-80b7-986b739a9255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022751422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.4022751422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.3722218596
Short name T789
Test name
Test status
Simulation time 43686467 ps
CPU time 0.95 seconds
Started Jul 01 12:10:34 PM PDT 24
Finished Jul 01 12:10:35 PM PDT 24
Peak memory 217824 kb
Host smart-ef0460a6-9ed7-45a4-88ad-d4b629a6534a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3722218596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3722218596 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.2106314658
Short name T577
Test name
Test status
Simulation time 49342410 ps
CPU time 1.14 seconds
Started Jul 01 12:10:34 PM PDT 24
Finished Jul 01 12:10:36 PM PDT 24
Peak memory 218000 kb
Host smart-e78aa9ff-7922-4623-a324-eec452947824
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2106314658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2106314658 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.3079565934
Short name T461
Test name
Test status
Simulation time 36595128666 ps
CPU time 429.77 seconds
Started Jul 01 12:10:34 PM PDT 24
Finished Jul 01 12:17:44 PM PDT 24
Peak memory 252360 kb
Host smart-5fd5e35c-d0b7-4aea-b1ef-c0a2e92a2df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079565934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3079565934 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.3396057853
Short name T665
Test name
Test status
Simulation time 75196782413 ps
CPU time 263.59 seconds
Started Jul 01 12:10:34 PM PDT 24
Finished Jul 01 12:14:58 PM PDT 24
Peak memory 259016 kb
Host smart-699b44ed-ed75-4e74-abe2-5fca5b94c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396057853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3396057853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.2456651417
Short name T233
Test name
Test status
Simulation time 1748683201 ps
CPU time 10.67 seconds
Started Jul 01 12:10:33 PM PDT 24
Finished Jul 01 12:10:45 PM PDT 24
Peak memory 218040 kb
Host smart-23337716-cd29-41f0-970b-6339f3c6d051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456651417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2456651417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.3174047917
Short name T515
Test name
Test status
Simulation time 49075759 ps
CPU time 1.46 seconds
Started Jul 01 12:10:35 PM PDT 24
Finished Jul 01 12:10:37 PM PDT 24
Peak memory 218212 kb
Host smart-341cb015-3511-4062-9b87-d49e5fcbef21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174047917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3174047917 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1981937917
Short name T115
Test name
Test status
Simulation time 153980232604 ps
CPU time 2032.87 seconds
Started Jul 01 12:10:25 PM PDT 24
Finished Jul 01 12:44:18 PM PDT 24
Peak memory 375316 kb
Host smart-0135137a-e043-41b2-ab7b-abb0d67ca99f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981937917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1981937917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.1549385081
Short name T452
Test name
Test status
Simulation time 12810624667 ps
CPU time 422.77 seconds
Started Jul 01 12:10:24 PM PDT 24
Finished Jul 01 12:17:27 PM PDT 24
Peak memory 252468 kb
Host smart-9f01085d-d23b-4b8a-8292-1f079878b04b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549385081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1549385081 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.1439181566
Short name T758
Test name
Test status
Simulation time 586632702 ps
CPU time 6.1 seconds
Started Jul 01 12:10:29 PM PDT 24
Finished Jul 01 12:10:36 PM PDT 24
Peak memory 219108 kb
Host smart-04c176ff-d021-4694-80bf-9a987906de16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439181566 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.1439181566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.2023693233
Short name T436
Test name
Test status
Simulation time 198575299 ps
CPU time 5.43 seconds
Started Jul 01 12:10:29 PM PDT 24
Finished Jul 01 12:10:35 PM PDT 24
Peak memory 218104 kb
Host smart-f3839382-595d-4c1a-b061-8bff8581da16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023693233 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.2023693233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.3428417362
Short name T227
Test name
Test status
Simulation time 262281069892 ps
CPU time 2219.66 seconds
Started Jul 01 12:10:24 PM PDT 24
Finished Jul 01 12:47:25 PM PDT 24
Peak memory 395624 kb
Host smart-a3bf062d-8e85-4864-82cd-4e69dd1993bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3428417362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.3428417362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.3885977412
Short name T278
Test name
Test status
Simulation time 367506358886 ps
CPU time 2413.16 seconds
Started Jul 01 12:10:23 PM PDT 24
Finished Jul 01 12:50:37 PM PDT 24
Peak memory 388156 kb
Host smart-1493dc0f-1466-4ada-a354-4e831b4ec42a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3885977412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.3885977412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.2314460774
Short name T1031
Test name
Test status
Simulation time 23178109442 ps
CPU time 1413.93 seconds
Started Jul 01 12:10:28 PM PDT 24
Finished Jul 01 12:34:02 PM PDT 24
Peak memory 343036 kb
Host smart-02e67b3b-f33e-4de7-91d1-310d822a8324
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2314460774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.2314460774 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.133323552
Short name T316
Test name
Test status
Simulation time 42663372622 ps
CPU time 1149.92 seconds
Started Jul 01 12:10:30 PM PDT 24
Finished Jul 01 12:29:41 PM PDT 24
Peak memory 302168 kb
Host smart-2c0e8658-5b83-4799-838f-d35e22c020f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=133323552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.133323552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.4280518567
Short name T315
Test name
Test status
Simulation time 743046680387 ps
CPU time 5907.25 seconds
Started Jul 01 12:10:30 PM PDT 24
Finished Jul 01 01:48:58 PM PDT 24
Peak memory 656312 kb
Host smart-b1192840-d26f-44d2-a7fd-527a8feede95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4280518567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.4280518567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.2455554369
Short name T755
Test name
Test status
Simulation time 716312714865 ps
CPU time 5225.11 seconds
Started Jul 01 12:10:28 PM PDT 24
Finished Jul 01 01:37:35 PM PDT 24
Peak memory 569352 kb
Host smart-50a5b89c-6e05-41c9-8ace-b05051f499e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2455554369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.2455554369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.4024061783
Short name T612
Test name
Test status
Simulation time 41911230 ps
CPU time 0.82 seconds
Started Jul 01 12:11:08 PM PDT 24
Finished Jul 01 12:11:09 PM PDT 24
Peak memory 217888 kb
Host smart-b07d7f16-ba2c-4c19-819d-597278852c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024061783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.4024061783 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.1630338915
Short name T354
Test name
Test status
Simulation time 2185749355 ps
CPU time 112.69 seconds
Started Jul 01 12:11:02 PM PDT 24
Finished Jul 01 12:12:55 PM PDT 24
Peak memory 232780 kb
Host smart-00127004-8aa2-4399-b864-3e31b7b0fd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630338915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1630338915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.2906418247
Short name T764
Test name
Test status
Simulation time 21912733736 ps
CPU time 1617.42 seconds
Started Jul 01 12:10:49 PM PDT 24
Finished Jul 01 12:37:48 PM PDT 24
Peak memory 242712 kb
Host smart-75b73596-5fae-4a16-b1ca-648e32057405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906418247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.2906418247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.3099332431
Short name T938
Test name
Test status
Simulation time 67047255 ps
CPU time 1.13 seconds
Started Jul 01 12:11:04 PM PDT 24
Finished Jul 01 12:11:06 PM PDT 24
Peak memory 218000 kb
Host smart-3fda1ec1-65de-44d9-a693-8b2b24f89e91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3099332431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3099332431 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.678346953
Short name T586
Test name
Test status
Simulation time 7162618935 ps
CPU time 240.7 seconds
Started Jul 01 12:11:01 PM PDT 24
Finished Jul 01 12:15:03 PM PDT 24
Peak memory 245276 kb
Host smart-42368f29-6d2b-4f43-bf5a-9c4d1049d4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678346953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.678346953 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.1929262170
Short name T1028
Test name
Test status
Simulation time 42259368334 ps
CPU time 313 seconds
Started Jul 01 12:11:05 PM PDT 24
Finished Jul 01 12:16:19 PM PDT 24
Peak memory 255988 kb
Host smart-d981e7be-003a-40e9-95f5-c2648c882ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929262170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.1929262170 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.1727431136
Short name T406
Test name
Test status
Simulation time 582736956 ps
CPU time 4.49 seconds
Started Jul 01 12:11:04 PM PDT 24
Finished Jul 01 12:11:10 PM PDT 24
Peak memory 218312 kb
Host smart-cb017119-e796-4179-9f9c-b122077dfcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727431136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.1727431136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.3832724661
Short name T451
Test name
Test status
Simulation time 37737551762 ps
CPU time 261.93 seconds
Started Jul 01 12:10:44 PM PDT 24
Finished Jul 01 12:15:07 PM PDT 24
Peak memory 243080 kb
Host smart-e557c152-2f7c-4ce0-93d7-1112d663f9ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832724661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.3832724661 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.1556408758
Short name T777
Test name
Test status
Simulation time 3140977807 ps
CPU time 99.04 seconds
Started Jul 01 12:10:44 PM PDT 24
Finished Jul 01 12:12:24 PM PDT 24
Peak memory 238200 kb
Host smart-f38958ac-fb0a-44aa-9f6f-de5bc54f2f4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556408758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1556408758 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.185414350
Short name T213
Test name
Test status
Simulation time 6818476465 ps
CPU time 75.97 seconds
Started Jul 01 12:10:45 PM PDT 24
Finished Jul 01 12:12:01 PM PDT 24
Peak memory 218184 kb
Host smart-e87227d6-9f6c-4950-9572-3784aed83f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185414350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.185414350 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.1406535133
Short name T13
Test name
Test status
Simulation time 40099297522 ps
CPU time 939.61 seconds
Started Jul 01 12:11:03 PM PDT 24
Finished Jul 01 12:26:43 PM PDT 24
Peak memory 324884 kb
Host smart-b0954600-356d-437b-8768-1b75501f41ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1406535133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1406535133 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.487063055
Short name T270
Test name
Test status
Simulation time 326368837 ps
CPU time 6.27 seconds
Started Jul 01 12:11:03 PM PDT 24
Finished Jul 01 12:11:09 PM PDT 24
Peak memory 218160 kb
Host smart-3bf2742a-9c87-4031-aa5c-454ac71dbe1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487063055 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.kmac_test_vectors_kmac_xof.487063055 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.1813722047
Short name T1005
Test name
Test status
Simulation time 30392209639 ps
CPU time 1953.06 seconds
Started Jul 01 12:10:50 PM PDT 24
Finished Jul 01 12:43:24 PM PDT 24
Peak memory 408776 kb
Host smart-0feb8b89-6113-4203-bcf6-bf3f98c57032
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1813722047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.1813722047 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.2826267393
Short name T416
Test name
Test status
Simulation time 369945402832 ps
CPU time 2268.01 seconds
Started Jul 01 12:10:50 PM PDT 24
Finished Jul 01 12:48:39 PM PDT 24
Peak memory 390268 kb
Host smart-7d353e74-efd2-450c-a3b3-4334c01869f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2826267393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.2826267393 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.2843951930
Short name T532
Test name
Test status
Simulation time 204832054115 ps
CPU time 1734.19 seconds
Started Jul 01 12:10:50 PM PDT 24
Finished Jul 01 12:39:46 PM PDT 24
Peak memory 337404 kb
Host smart-4f932f58-76cc-4ee1-8a78-9c02ac86c582
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2843951930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.2843951930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.380998670
Short name T632
Test name
Test status
Simulation time 173917329193 ps
CPU time 1266.8 seconds
Started Jul 01 12:10:50 PM PDT 24
Finished Jul 01 12:31:58 PM PDT 24
Peak memory 296904 kb
Host smart-6ac71c39-8949-497f-b180-bb606a5e78a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=380998670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.380998670 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.1401293719
Short name T574
Test name
Test status
Simulation time 733161019134 ps
CPU time 5888.97 seconds
Started Jul 01 12:10:50 PM PDT 24
Finished Jul 01 01:49:00 PM PDT 24
Peak memory 649096 kb
Host smart-8b5af068-2489-4854-bd94-9e8f08e5a55c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1401293719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.1401293719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.2618916010
Short name T254
Test name
Test status
Simulation time 298705098608 ps
CPU time 5096.64 seconds
Started Jul 01 12:11:01 PM PDT 24
Finished Jul 01 01:36:00 PM PDT 24
Peak memory 575640 kb
Host smart-faa276bf-b164-4fa4-b4bb-d91e15f22700
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2618916010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.2618916010 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.808261986
Short name T954
Test name
Test status
Simulation time 47583367 ps
CPU time 0.8 seconds
Started Jul 01 12:11:25 PM PDT 24
Finished Jul 01 12:11:26 PM PDT 24
Peak memory 217840 kb
Host smart-eda96ee3-59d5-4e17-af0d-9700a3147ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808261986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.808261986 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.2723182224
Short name T822
Test name
Test status
Simulation time 14760970009 ps
CPU time 216.54 seconds
Started Jul 01 12:11:14 PM PDT 24
Finished Jul 01 12:14:51 PM PDT 24
Peak memory 243812 kb
Host smart-fdf66c10-8511-4aba-9d1c-5ea2a4977507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723182224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2723182224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.1169305940
Short name T160
Test name
Test status
Simulation time 30248584523 ps
CPU time 811.11 seconds
Started Jul 01 12:11:09 PM PDT 24
Finished Jul 01 12:24:41 PM PDT 24
Peak memory 233792 kb
Host smart-cdf82092-d5b4-4d8b-90e4-1d9e820abaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169305940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1169305940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.2683392603
Short name T1060
Test name
Test status
Simulation time 12423856 ps
CPU time 0.87 seconds
Started Jul 01 12:11:21 PM PDT 24
Finished Jul 01 12:11:22 PM PDT 24
Peak memory 217772 kb
Host smart-d2c71716-f5ab-45d6-9c34-da5a8a5cbc2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2683392603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2683392603 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.2577447260
Short name T64
Test name
Test status
Simulation time 59285782 ps
CPU time 0.97 seconds
Started Jul 01 12:11:21 PM PDT 24
Finished Jul 01 12:11:23 PM PDT 24
Peak memory 217848 kb
Host smart-61b07e6e-18de-43d7-b3f0-cb36c3738d3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2577447260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2577447260 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.15095171
Short name T713
Test name
Test status
Simulation time 50854267214 ps
CPU time 284.86 seconds
Started Jul 01 12:11:16 PM PDT 24
Finished Jul 01 12:16:02 PM PDT 24
Peak memory 248064 kb
Host smart-912734a0-8f4e-42b4-ae90-a9affc6b1d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15095171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.15095171 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.1036697969
Short name T864
Test name
Test status
Simulation time 84283327517 ps
CPU time 499 seconds
Started Jul 01 12:11:22 PM PDT 24
Finished Jul 01 12:19:42 PM PDT 24
Peak memory 266796 kb
Host smart-e6aaefc4-ac2b-4ca1-883a-ecb9e22df150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036697969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1036697969 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.1170033017
Short name T113
Test name
Test status
Simulation time 3010838298 ps
CPU time 7.06 seconds
Started Jul 01 12:11:20 PM PDT 24
Finished Jul 01 12:11:28 PM PDT 24
Peak memory 218208 kb
Host smart-62a4a059-2541-4367-856a-fc48e13724b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170033017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1170033017 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.130911883
Short name T90
Test name
Test status
Simulation time 935541461 ps
CPU time 34.81 seconds
Started Jul 01 12:11:25 PM PDT 24
Finished Jul 01 12:12:00 PM PDT 24
Peak memory 235532 kb
Host smart-89fb5942-e166-40ea-a007-9f7a03991fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130911883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.130911883 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.3742280385
Short name T967
Test name
Test status
Simulation time 25207971114 ps
CPU time 243.09 seconds
Started Jul 01 12:11:09 PM PDT 24
Finished Jul 01 12:15:13 PM PDT 24
Peak memory 242700 kb
Host smart-5e8b11ff-4918-491d-a019-920288df3081
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742280385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.3742280385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.18310132
Short name T224
Test name
Test status
Simulation time 16408331218 ps
CPU time 141.04 seconds
Started Jul 01 12:11:09 PM PDT 24
Finished Jul 01 12:13:31 PM PDT 24
Peak memory 233528 kb
Host smart-dc19d37a-757e-459a-83d2-0bfbfd6b9e79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18310132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.18310132 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.115818800
Short name T198
Test name
Test status
Simulation time 23507658384 ps
CPU time 78.78 seconds
Started Jul 01 12:11:09 PM PDT 24
Finished Jul 01 12:12:29 PM PDT 24
Peak memory 222616 kb
Host smart-79020522-9b8c-4080-8691-1235865dcc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115818800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.115818800 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.856476134
Short name T693
Test name
Test status
Simulation time 42817728811 ps
CPU time 443.99 seconds
Started Jul 01 12:11:25 PM PDT 24
Finished Jul 01 12:18:49 PM PDT 24
Peak memory 292648 kb
Host smart-eaeaa446-6d14-4dff-862a-3192b9211b59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=856476134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.856476134 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.3806907861
Short name T300
Test name
Test status
Simulation time 3499872145 ps
CPU time 6.12 seconds
Started Jul 01 12:11:16 PM PDT 24
Finished Jul 01 12:11:23 PM PDT 24
Peak memory 218168 kb
Host smart-258112f8-6cdf-458e-962a-8d77af2d24a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806907861 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.3806907861 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.3823825519
Short name T935
Test name
Test status
Simulation time 230564375 ps
CPU time 5.72 seconds
Started Jul 01 12:11:16 PM PDT 24
Finished Jul 01 12:11:23 PM PDT 24
Peak memory 218216 kb
Host smart-df146bff-ae73-429d-9b1e-8f52d366439c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823825519 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.3823825519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.735908924
Short name T1010
Test name
Test status
Simulation time 316111377870 ps
CPU time 2374.79 seconds
Started Jul 01 12:11:10 PM PDT 24
Finished Jul 01 12:50:46 PM PDT 24
Peak memory 395828 kb
Host smart-47a6421c-7d96-4573-9319-4739cbe1b456
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=735908924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.735908924 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.1639509073
Short name T710
Test name
Test status
Simulation time 48217359841 ps
CPU time 1847.63 seconds
Started Jul 01 12:11:10 PM PDT 24
Finished Jul 01 12:41:59 PM PDT 24
Peak memory 389628 kb
Host smart-7cc3efc4-03e1-4872-a995-7abd59f24aa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1639509073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.1639509073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.3726365169
Short name T871
Test name
Test status
Simulation time 269974386677 ps
CPU time 1880.54 seconds
Started Jul 01 12:11:09 PM PDT 24
Finished Jul 01 12:42:31 PM PDT 24
Peak memory 339832 kb
Host smart-475956d0-00b7-4d04-a3c9-fec58c822bd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3726365169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.3726365169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.922528815
Short name T231
Test name
Test status
Simulation time 193277067598 ps
CPU time 1334.42 seconds
Started Jul 01 12:11:10 PM PDT 24
Finished Jul 01 12:33:26 PM PDT 24
Peak memory 297292 kb
Host smart-ecbf4279-e40e-4e2d-bec2-2c15cf75548f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=922528815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.922528815 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.2347432067
Short name T1066
Test name
Test status
Simulation time 258791848251 ps
CPU time 6214.62 seconds
Started Jul 01 12:11:11 PM PDT 24
Finished Jul 01 01:54:47 PM PDT 24
Peak memory 642524 kb
Host smart-af3fb54c-5fe3-4620-bd07-7e68d767c46c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2347432067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.2347432067 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.729741501
Short name T555
Test name
Test status
Simulation time 585732933737 ps
CPU time 5083.79 seconds
Started Jul 01 12:11:16 PM PDT 24
Finished Jul 01 01:36:01 PM PDT 24
Peak memory 569928 kb
Host smart-513a352b-60fd-46d4-b589-12f9c412c257
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=729741501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.729741501 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.385287874
Short name T835
Test name
Test status
Simulation time 13810306 ps
CPU time 0.83 seconds
Started Jul 01 12:11:46 PM PDT 24
Finished Jul 01 12:11:48 PM PDT 24
Peak memory 217936 kb
Host smart-c19e40f8-971d-4e37-bbde-8dbd185545e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385287874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.385287874 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.3150845336
Short name T962
Test name
Test status
Simulation time 6747674040 ps
CPU time 307.43 seconds
Started Jul 01 12:11:43 PM PDT 24
Finished Jul 01 12:16:50 PM PDT 24
Peak memory 248672 kb
Host smart-ef6e07b8-dd12-44c7-b40d-a791eaad27f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150845336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3150845336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.2657739368
Short name T746
Test name
Test status
Simulation time 22381424565 ps
CPU time 1004.77 seconds
Started Jul 01 12:11:31 PM PDT 24
Finished Jul 01 12:28:17 PM PDT 24
Peak memory 238456 kb
Host smart-65e4db6e-d95c-4427-9642-b0df177d5aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657739368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2657739368 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.3772915681
Short name T380
Test name
Test status
Simulation time 963702976 ps
CPU time 18.88 seconds
Started Jul 01 12:11:40 PM PDT 24
Finished Jul 01 12:11:59 PM PDT 24
Peak memory 226440 kb
Host smart-1b0f8b02-b494-4084-9674-bc0cce5d4f10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3772915681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3772915681 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.2450975083
Short name T889
Test name
Test status
Simulation time 44348276 ps
CPU time 1.15 seconds
Started Jul 01 12:11:41 PM PDT 24
Finished Jul 01 12:11:43 PM PDT 24
Peak memory 218000 kb
Host smart-03e29099-b9fd-40a9-8e90-a55632f7b88a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2450975083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2450975083 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_error.1535207516
Short name T753
Test name
Test status
Simulation time 5652179767 ps
CPU time 369.1 seconds
Started Jul 01 12:11:40 PM PDT 24
Finished Jul 01 12:17:50 PM PDT 24
Peak memory 275100 kb
Host smart-b79993ec-0701-4470-ae28-2b41b09c73fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535207516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1535207516 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.1352017222
Short name T591
Test name
Test status
Simulation time 2437786475 ps
CPU time 5.11 seconds
Started Jul 01 12:11:41 PM PDT 24
Finished Jul 01 12:11:47 PM PDT 24
Peak memory 218176 kb
Host smart-bd20f2be-957b-457c-891f-8a9344e22399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352017222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1352017222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.2273567707
Short name T568
Test name
Test status
Simulation time 53803650 ps
CPU time 1.43 seconds
Started Jul 01 12:11:48 PM PDT 24
Finished Jul 01 12:11:50 PM PDT 24
Peak memory 219032 kb
Host smart-d46f1c3e-8a19-4975-87a9-1d95b5a56166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273567707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2273567707 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.1722984971
Short name T736
Test name
Test status
Simulation time 40560776493 ps
CPU time 959.43 seconds
Started Jul 01 12:11:24 PM PDT 24
Finished Jul 01 12:27:24 PM PDT 24
Peak memory 308764 kb
Host smart-76921411-1d08-495d-9659-7da8707de475
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722984971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.1722984971 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.124099402
Short name T382
Test name
Test status
Simulation time 17354361530 ps
CPU time 443.02 seconds
Started Jul 01 12:11:25 PM PDT 24
Finished Jul 01 12:18:49 PM PDT 24
Peak memory 253340 kb
Host smart-dfb7ea3c-7eb6-4538-a656-09281fa0b257
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124099402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.124099402 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.2397041092
Short name T465
Test name
Test status
Simulation time 3104565447 ps
CPU time 42.5 seconds
Started Jul 01 12:11:30 PM PDT 24
Finished Jul 01 12:12:13 PM PDT 24
Peak memory 225252 kb
Host smart-1930b2f6-1da1-47a5-98a2-9e8024882084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397041092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2397041092 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.552195417
Short name T680
Test name
Test status
Simulation time 47428986695 ps
CPU time 982.76 seconds
Started Jul 01 12:11:47 PM PDT 24
Finished Jul 01 12:28:10 PM PDT 24
Peak memory 335032 kb
Host smart-69723b29-dc2d-4b03-8b9c-28d4d28d425e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=552195417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.552195417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.4252695184
Short name T620
Test name
Test status
Simulation time 399715904 ps
CPU time 6.68 seconds
Started Jul 01 12:11:35 PM PDT 24
Finished Jul 01 12:11:42 PM PDT 24
Peak memory 218140 kb
Host smart-4a910ddb-b6b2-40bc-ad19-537c334a77c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252695184 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.4252695184 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.1466180403
Short name T547
Test name
Test status
Simulation time 222002984 ps
CPU time 6.34 seconds
Started Jul 01 12:11:41 PM PDT 24
Finished Jul 01 12:11:48 PM PDT 24
Peak memory 219120 kb
Host smart-0cbec993-cafb-4d0d-bc1e-27e76aaea69c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466180403 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.1466180403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.3938911461
Short name T671
Test name
Test status
Simulation time 265605274602 ps
CPU time 2317.77 seconds
Started Jul 01 12:11:30 PM PDT 24
Finished Jul 01 12:50:09 PM PDT 24
Peak memory 401480 kb
Host smart-aef77fc6-82c8-4206-babf-5ff78d4a2837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3938911461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.3938911461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.2075156127
Short name T217
Test name
Test status
Simulation time 322770306625 ps
CPU time 2166.75 seconds
Started Jul 01 12:11:32 PM PDT 24
Finished Jul 01 12:47:39 PM PDT 24
Peak memory 389000 kb
Host smart-6433a4f3-7ac0-48f8-b5bd-c28c67e7c073
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2075156127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.2075156127 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.1002053025
Short name T338
Test name
Test status
Simulation time 217538011709 ps
CPU time 1732.07 seconds
Started Jul 01 12:11:32 PM PDT 24
Finished Jul 01 12:40:25 PM PDT 24
Peak memory 341780 kb
Host smart-4c644201-a766-48c3-959c-fcdd3af58035
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1002053025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.1002053025 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.4239411983
Short name T796
Test name
Test status
Simulation time 96048581955 ps
CPU time 1132.4 seconds
Started Jul 01 12:11:30 PM PDT 24
Finished Jul 01 12:30:23 PM PDT 24
Peak memory 300156 kb
Host smart-ad10299c-2697-4151-b48f-4bd8aeaf5f26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4239411983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.4239411983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.1770696188
Short name T949
Test name
Test status
Simulation time 1005530131264 ps
CPU time 4986.43 seconds
Started Jul 01 12:11:31 PM PDT 24
Finished Jul 01 01:34:38 PM PDT 24
Peak memory 646140 kb
Host smart-902bd83a-1393-49dd-b33b-bd44d14699d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1770696188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.1770696188 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.3931164493
Short name T552
Test name
Test status
Simulation time 609574724708 ps
CPU time 5765.94 seconds
Started Jul 01 12:11:30 PM PDT 24
Finished Jul 01 01:47:37 PM PDT 24
Peak memory 577744 kb
Host smart-1db5849b-8236-4ac2-ba99-7cd247df6633
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3931164493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.3931164493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.529424473
Short name T1061
Test name
Test status
Simulation time 11687419 ps
CPU time 0.78 seconds
Started Jul 01 12:12:18 PM PDT 24
Finished Jul 01 12:12:19 PM PDT 24
Peak memory 217940 kb
Host smart-2676a521-823a-47e0-bc6f-7e62c39f69b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529424473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.529424473 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.3680588648
Short name T372
Test name
Test status
Simulation time 12641688782 ps
CPU time 327.98 seconds
Started Jul 01 12:12:03 PM PDT 24
Finished Jul 01 12:17:31 PM PDT 24
Peak memory 248544 kb
Host smart-3bf9c377-9f47-4b6f-b6d2-866385731edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680588648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3680588648 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.2086695011
Short name T163
Test name
Test status
Simulation time 26055829785 ps
CPU time 627.15 seconds
Started Jul 01 12:11:51 PM PDT 24
Finished Jul 01 12:22:20 PM PDT 24
Peak memory 233740 kb
Host smart-b37a54e4-ff76-4627-92cf-2454a2ce94fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086695011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2086695011 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.2454313344
Short name T834
Test name
Test status
Simulation time 24449353 ps
CPU time 1.03 seconds
Started Jul 01 12:12:02 PM PDT 24
Finished Jul 01 12:12:04 PM PDT 24
Peak memory 217824 kb
Host smart-48af80f6-9ac1-4c40-9aa0-eb1c52f3ea22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2454313344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2454313344 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.3358591387
Short name T387
Test name
Test status
Simulation time 15037239 ps
CPU time 0.88 seconds
Started Jul 01 12:12:13 PM PDT 24
Finished Jul 01 12:12:15 PM PDT 24
Peak memory 217784 kb
Host smart-98be83ff-a2e9-4d09-9057-c610a6090025
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3358591387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.3358591387 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.1490317317
Short name T1025
Test name
Test status
Simulation time 31396309484 ps
CPU time 203.47 seconds
Started Jul 01 12:12:02 PM PDT 24
Finished Jul 01 12:15:27 PM PDT 24
Peak memory 242712 kb
Host smart-7c7beb56-05d5-42a2-8fc9-6d45ca5f019e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490317317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1490317317 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.2988764530
Short name T655
Test name
Test status
Simulation time 36469691348 ps
CPU time 315.15 seconds
Started Jul 01 12:12:02 PM PDT 24
Finished Jul 01 12:17:18 PM PDT 24
Peak memory 258976 kb
Host smart-8be94d4d-3bf0-4336-9123-4ab262dec12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988764530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2988764530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.2011851612
Short name T4
Test name
Test status
Simulation time 7214464450 ps
CPU time 12.41 seconds
Started Jul 01 12:12:03 PM PDT 24
Finished Jul 01 12:12:16 PM PDT 24
Peak memory 218256 kb
Host smart-4638a800-f840-4096-86e1-3ff0e715f9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011851612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2011851612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.1830421372
Short name T761
Test name
Test status
Simulation time 763638120 ps
CPU time 17.66 seconds
Started Jul 01 12:12:14 PM PDT 24
Finished Jul 01 12:12:32 PM PDT 24
Peak memory 235124 kb
Host smart-2789e9f3-e443-4abb-abdb-e837c3fc8ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830421372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1830421372 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.1565520105
Short name T644
Test name
Test status
Simulation time 129540753021 ps
CPU time 3370.04 seconds
Started Jul 01 12:11:47 PM PDT 24
Finished Jul 01 01:07:58 PM PDT 24
Peak memory 490396 kb
Host smart-a2fdc708-a270-4823-93b5-daf5b8ea0921
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565520105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.1565520105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.2042505
Short name T829
Test name
Test status
Simulation time 18694052575 ps
CPU time 463.66 seconds
Started Jul 01 12:11:48 PM PDT 24
Finished Jul 01 12:19:32 PM PDT 24
Peak memory 254172 kb
Host smart-6bb8956e-1fd1-4f6e-9bb1-c1aa493cbb96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2042505 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.937963685
Short name T408
Test name
Test status
Simulation time 326848200 ps
CPU time 8.74 seconds
Started Jul 01 12:11:48 PM PDT 24
Finished Jul 01 12:11:57 PM PDT 24
Peak memory 222768 kb
Host smart-3e0a6123-1318-45ed-aaa4-1b4a24b7fc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937963685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.937963685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.2148270817
Short name T941
Test name
Test status
Simulation time 141364147830 ps
CPU time 618.63 seconds
Started Jul 01 12:12:17 PM PDT 24
Finished Jul 01 12:22:37 PM PDT 24
Peak memory 292196 kb
Host smart-68c0211e-8bda-4ff4-ae72-0f74a2a42a9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2148270817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2148270817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.1889059505
Short name T813
Test name
Test status
Simulation time 268223018 ps
CPU time 6.75 seconds
Started Jul 01 12:11:57 PM PDT 24
Finished Jul 01 12:12:05 PM PDT 24
Peak memory 218112 kb
Host smart-69435422-5b7f-4c97-af52-5d118463543d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889059505 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.1889059505 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.768616713
Short name T321
Test name
Test status
Simulation time 443721809 ps
CPU time 5.89 seconds
Started Jul 01 12:11:57 PM PDT 24
Finished Jul 01 12:12:03 PM PDT 24
Peak memory 218152 kb
Host smart-7f763232-ab51-4d10-9d2a-abed4f2c1042
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768616713 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.kmac_test_vectors_kmac_xof.768616713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.31287405
Short name T917
Test name
Test status
Simulation time 74876152754 ps
CPU time 2072.89 seconds
Started Jul 01 12:11:51 PM PDT 24
Finished Jul 01 12:46:25 PM PDT 24
Peak memory 400736 kb
Host smart-31c96b37-968f-43b0-8faa-a6d6a6cd6289
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=31287405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.31287405 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.2415083042
Short name T850
Test name
Test status
Simulation time 94840442326 ps
CPU time 2164.5 seconds
Started Jul 01 12:11:51 PM PDT 24
Finished Jul 01 12:47:57 PM PDT 24
Peak memory 380004 kb
Host smart-40af5d06-61e1-4742-b912-a81fafa0fb6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2415083042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.2415083042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.2564086156
Short name T484
Test name
Test status
Simulation time 78486151522 ps
CPU time 1409.9 seconds
Started Jul 01 12:11:51 PM PDT 24
Finished Jul 01 12:35:22 PM PDT 24
Peak memory 340600 kb
Host smart-8293d21e-f1f3-4455-9452-8b2503a30472
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2564086156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.2564086156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.2856414491
Short name T324
Test name
Test status
Simulation time 50272998236 ps
CPU time 1366.99 seconds
Started Jul 01 12:11:51 PM PDT 24
Finished Jul 01 12:34:39 PM PDT 24
Peak memory 302784 kb
Host smart-8e67b5a3-d62f-4432-adc0-4c5a2cc8b451
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2856414491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.2856414491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.329676825
Short name T824
Test name
Test status
Simulation time 730231242188 ps
CPU time 5473.69 seconds
Started Jul 01 12:11:58 PM PDT 24
Finished Jul 01 01:43:14 PM PDT 24
Peak memory 636808 kb
Host smart-dd724c21-1c59-4f7a-9ce0-417d5e859a73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=329676825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.329676825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.363905754
Short name T880
Test name
Test status
Simulation time 300289321198 ps
CPU time 5065.17 seconds
Started Jul 01 12:11:59 PM PDT 24
Finished Jul 01 01:36:25 PM PDT 24
Peak memory 560828 kb
Host smart-57689474-cc11-4a58-8f10-16a2ae79feec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=363905754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.363905754 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.4084831024
Short name T806
Test name
Test status
Simulation time 37595041 ps
CPU time 0.81 seconds
Started Jul 01 12:12:50 PM PDT 24
Finished Jul 01 12:12:52 PM PDT 24
Peak memory 217928 kb
Host smart-279476d9-0c7c-47d0-8256-38e7e10f20c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084831024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.4084831024 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.1888510797
Short name T184
Test name
Test status
Simulation time 38875178203 ps
CPU time 271.64 seconds
Started Jul 01 12:12:34 PM PDT 24
Finished Jul 01 12:17:06 PM PDT 24
Peak memory 248136 kb
Host smart-2d9616ec-6521-4bc7-bb03-280caadbc7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888510797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1888510797 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.2490862970
Short name T925
Test name
Test status
Simulation time 9984995042 ps
CPU time 506.78 seconds
Started Jul 01 12:12:25 PM PDT 24
Finished Jul 01 12:20:53 PM PDT 24
Peak memory 234712 kb
Host smart-ca97df34-b4e2-43ad-8116-2e33a1c397dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490862970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.2490862970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.1229677819
Short name T1065
Test name
Test status
Simulation time 106001049 ps
CPU time 1.03 seconds
Started Jul 01 12:12:38 PM PDT 24
Finished Jul 01 12:12:40 PM PDT 24
Peak memory 217924 kb
Host smart-6dee06c2-83d3-4f61-9131-d8f3a14b7bde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1229677819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.1229677819 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.1421853481
Short name T559
Test name
Test status
Simulation time 102186300 ps
CPU time 1.13 seconds
Started Jul 01 12:12:44 PM PDT 24
Finished Jul 01 12:12:46 PM PDT 24
Peak memory 217976 kb
Host smart-2110af8b-d261-4a73-9cea-3c15a84a468c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1421853481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1421853481 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.2607458439
Short name T810
Test name
Test status
Simulation time 13566075273 ps
CPU time 374.46 seconds
Started Jul 01 12:12:37 PM PDT 24
Finished Jul 01 12:18:52 PM PDT 24
Peak memory 251264 kb
Host smart-2d6e458c-d898-4d73-b637-de059e73fd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607458439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2607458439 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.1222516403
Short name T636
Test name
Test status
Simulation time 17652781821 ps
CPU time 368.2 seconds
Started Jul 01 12:12:39 PM PDT 24
Finished Jul 01 12:18:48 PM PDT 24
Peak memory 259128 kb
Host smart-8007790b-3e64-4c33-bb9c-c07c2bbe8c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222516403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1222516403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.2922971921
Short name T444
Test name
Test status
Simulation time 5743526845 ps
CPU time 10.93 seconds
Started Jul 01 12:12:37 PM PDT 24
Finished Jul 01 12:12:49 PM PDT 24
Peak memory 218236 kb
Host smart-687edd78-17aa-48c5-8ed6-4d0bc9c92823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922971921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2922971921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.3209298927
Short name T523
Test name
Test status
Simulation time 923448821546 ps
CPU time 3222.75 seconds
Started Jul 01 12:12:20 PM PDT 24
Finished Jul 01 01:06:05 PM PDT 24
Peak memory 464204 kb
Host smart-e93979d4-ceb1-4e0c-bfed-0d279da945da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209298927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.3209298927 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.1733272676
Short name T775
Test name
Test status
Simulation time 3415521348 ps
CPU time 107.95 seconds
Started Jul 01 12:12:17 PM PDT 24
Finished Jul 01 12:14:06 PM PDT 24
Peak memory 231052 kb
Host smart-8d7b040d-79e4-40b9-bdeb-9e898158c0aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733272676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1733272676 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.1342689397
Short name T91
Test name
Test status
Simulation time 244904462 ps
CPU time 1.75 seconds
Started Jul 01 12:12:18 PM PDT 24
Finished Jul 01 12:12:21 PM PDT 24
Peak memory 223668 kb
Host smart-791dda79-f71b-41ea-91a9-725eba417895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342689397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1342689397 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.1549760589
Short name T858
Test name
Test status
Simulation time 130430632416 ps
CPU time 1264.54 seconds
Started Jul 01 12:12:48 PM PDT 24
Finished Jul 01 12:33:55 PM PDT 24
Peak memory 350496 kb
Host smart-1ca6094c-8ec8-42d5-8b8f-e7c25182a5b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1549760589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1549760589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.1218072600
Short name T336
Test name
Test status
Simulation time 311548688 ps
CPU time 6.3 seconds
Started Jul 01 12:12:35 PM PDT 24
Finished Jul 01 12:12:42 PM PDT 24
Peak memory 218136 kb
Host smart-eaf5466f-b4c4-42a7-b930-62cbdf609f8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218072600 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.1218072600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.3510160247
Short name T793
Test name
Test status
Simulation time 679247228 ps
CPU time 5.54 seconds
Started Jul 01 12:12:33 PM PDT 24
Finished Jul 01 12:12:40 PM PDT 24
Peak memory 218136 kb
Host smart-22f7bde7-f5ea-4e24-b385-c3146c3026c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510160247 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.3510160247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.4216835888
Short name T460
Test name
Test status
Simulation time 153578274713 ps
CPU time 2115.66 seconds
Started Jul 01 12:12:23 PM PDT 24
Finished Jul 01 12:47:40 PM PDT 24
Peak memory 397500 kb
Host smart-cfa2dc84-cebc-43b5-b877-d4bf41737c45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4216835888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.4216835888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.3126880688
Short name T821
Test name
Test status
Simulation time 128174897269 ps
CPU time 2206.85 seconds
Started Jul 01 12:12:25 PM PDT 24
Finished Jul 01 12:49:13 PM PDT 24
Peak memory 383360 kb
Host smart-b5b46a76-cd96-456e-8c4c-ef2c916691d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3126880688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.3126880688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.1615719533
Short name T313
Test name
Test status
Simulation time 557362735276 ps
CPU time 1752.17 seconds
Started Jul 01 12:12:25 PM PDT 24
Finished Jul 01 12:41:38 PM PDT 24
Peak memory 340256 kb
Host smart-148f4caf-816b-4b0f-9430-bea6fc59a8fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1615719533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.1615719533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.3091795009
Short name T333
Test name
Test status
Simulation time 70723240502 ps
CPU time 1324.05 seconds
Started Jul 01 12:12:28 PM PDT 24
Finished Jul 01 12:34:33 PM PDT 24
Peak memory 297500 kb
Host smart-28ebf8bc-6b47-4594-a0ac-2d60536ae4b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3091795009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.3091795009 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.3232098763
Short name T442
Test name
Test status
Simulation time 512813775839 ps
CPU time 6209.92 seconds
Started Jul 01 12:12:34 PM PDT 24
Finished Jul 01 01:56:06 PM PDT 24
Peak memory 643004 kb
Host smart-cc10d49b-6561-499a-bdef-5b87ad3650aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3232098763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.3232098763 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.4060546743
Short name T561
Test name
Test status
Simulation time 227356215770 ps
CPU time 4440.9 seconds
Started Jul 01 12:12:34 PM PDT 24
Finished Jul 01 01:26:37 PM PDT 24
Peak memory 568444 kb
Host smart-27fbc526-b2d6-4e5c-a457-df40c7fdcd5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4060546743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.4060546743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.2746544200
Short name T489
Test name
Test status
Simulation time 59219980 ps
CPU time 0.85 seconds
Started Jul 01 12:13:17 PM PDT 24
Finished Jul 01 12:13:19 PM PDT 24
Peak memory 217908 kb
Host smart-d80af762-9956-4b7c-b1ad-13551e297062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746544200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2746544200 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.3807836018
Short name T656
Test name
Test status
Simulation time 15120233709 ps
CPU time 286.6 seconds
Started Jul 01 12:13:02 PM PDT 24
Finished Jul 01 12:17:49 PM PDT 24
Peak memory 244772 kb
Host smart-d9490823-afbf-418a-8dae-ae9049450015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807836018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.3807836018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.2834671779
Short name T687
Test name
Test status
Simulation time 6232140484 ps
CPU time 300.27 seconds
Started Jul 01 12:12:53 PM PDT 24
Finished Jul 01 12:17:54 PM PDT 24
Peak memory 228492 kb
Host smart-d20cef79-d3c8-4862-8079-fa195334d5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834671779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.2834671779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.1348450064
Short name T1027
Test name
Test status
Simulation time 77819563 ps
CPU time 1.26 seconds
Started Jul 01 12:13:15 PM PDT 24
Finished Jul 01 12:13:16 PM PDT 24
Peak memory 217952 kb
Host smart-72476520-30e0-4831-844c-22407b6be71c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1348450064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1348450064 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.611924868
Short name T274
Test name
Test status
Simulation time 2752285597 ps
CPU time 33.36 seconds
Started Jul 01 12:13:15 PM PDT 24
Finished Jul 01 12:13:49 PM PDT 24
Peak memory 228144 kb
Host smart-c4b176f3-15b7-450a-9059-474b1cb616b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=611924868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.611924868 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.2728002942
Short name T717
Test name
Test status
Simulation time 53040090080 ps
CPU time 399.45 seconds
Started Jul 01 12:13:10 PM PDT 24
Finished Jul 01 12:19:51 PM PDT 24
Peak memory 251052 kb
Host smart-8a52d365-6c54-48e5-9205-1c9c750d25d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728002942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2728002942 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.1726514794
Short name T1006
Test name
Test status
Simulation time 13722639939 ps
CPU time 161.85 seconds
Started Jul 01 12:13:18 PM PDT 24
Finished Jul 01 12:16:00 PM PDT 24
Peak memory 251528 kb
Host smart-51984c87-7a56-4e93-b8a5-949bc15fabe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726514794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1726514794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.3016799157
Short name T307
Test name
Test status
Simulation time 4754074878 ps
CPU time 8.38 seconds
Started Jul 01 12:13:17 PM PDT 24
Finished Jul 01 12:13:27 PM PDT 24
Peak memory 218304 kb
Host smart-1b75af00-28b1-4d8e-aca2-3ad1ec8b5143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016799157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3016799157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.21947631
Short name T73
Test name
Test status
Simulation time 28280506 ps
CPU time 1.32 seconds
Started Jul 01 12:13:14 PM PDT 24
Finished Jul 01 12:13:16 PM PDT 24
Peak memory 218284 kb
Host smart-904d8c3a-ed47-4632-8767-9697372a5fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21947631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.21947631 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.455800951
Short name T59
Test name
Test status
Simulation time 376268972787 ps
CPU time 2403.84 seconds
Started Jul 01 12:12:48 PM PDT 24
Finished Jul 01 12:52:54 PM PDT 24
Peak memory 400064 kb
Host smart-1d7d19fe-9da8-4fd1-8d99-f67eb2871848
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455800951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_an
d_output.455800951 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.2108413609
Short name T1009
Test name
Test status
Simulation time 16614960464 ps
CPU time 445.47 seconds
Started Jul 01 12:12:52 PM PDT 24
Finished Jul 01 12:20:18 PM PDT 24
Peak memory 253432 kb
Host smart-4bd43b25-ac12-43ee-a25c-440fd08720e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108413609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2108413609 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.865595731
Short name T529
Test name
Test status
Simulation time 6529188395 ps
CPU time 59.46 seconds
Started Jul 01 12:12:48 PM PDT 24
Finished Jul 01 12:13:48 PM PDT 24
Peak memory 226344 kb
Host smart-994c235f-3227-4f54-a3a1-235ad5e79548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865595731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.865595731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.2472989687
Short name T932
Test name
Test status
Simulation time 18770085819 ps
CPU time 525.96 seconds
Started Jul 01 12:13:16 PM PDT 24
Finished Jul 01 12:22:03 PM PDT 24
Peak memory 275764 kb
Host smart-be180e58-1b03-4041-8f42-48b89ba7e7f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2472989687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2472989687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.612149475
Short name T471
Test name
Test status
Simulation time 113541006 ps
CPU time 5.55 seconds
Started Jul 01 12:12:58 PM PDT 24
Finished Jul 01 12:13:05 PM PDT 24
Peak memory 219092 kb
Host smart-9fde49b5-c568-40ad-a3d3-d7f8d4078188
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612149475 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.kmac_test_vectors_kmac.612149475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.153234892
Short name T351
Test name
Test status
Simulation time 238486186 ps
CPU time 6.02 seconds
Started Jul 01 12:13:05 PM PDT 24
Finished Jul 01 12:13:12 PM PDT 24
Peak memory 218156 kb
Host smart-404f9b86-aa98-4c12-9a45-dccb31041e4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153234892 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.kmac_test_vectors_kmac_xof.153234892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.4195677149
Short name T1019
Test name
Test status
Simulation time 199748180427 ps
CPU time 2469.39 seconds
Started Jul 01 12:12:52 PM PDT 24
Finished Jul 01 12:54:02 PM PDT 24
Peak memory 398700 kb
Host smart-0658abce-6cd8-4f01-9f8e-ccc3f4b9317e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4195677149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.4195677149 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.1027050174
Short name T792
Test name
Test status
Simulation time 438302259292 ps
CPU time 2079.37 seconds
Started Jul 01 12:12:54 PM PDT 24
Finished Jul 01 12:47:34 PM PDT 24
Peak memory 384124 kb
Host smart-1571cecf-b2f3-4a14-aa1a-b2f7a8440b9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1027050174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.1027050174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.3485184449
Short name T222
Test name
Test status
Simulation time 51526809607 ps
CPU time 1657.91 seconds
Started Jul 01 12:13:01 PM PDT 24
Finished Jul 01 12:40:40 PM PDT 24
Peak memory 340860 kb
Host smart-106dc349-1ed4-4683-bac9-dffab9f6dfe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3485184449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.3485184449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.37261353
Short name T590
Test name
Test status
Simulation time 44702586472 ps
CPU time 1182.67 seconds
Started Jul 01 12:12:57 PM PDT 24
Finished Jul 01 12:32:40 PM PDT 24
Peak memory 298636 kb
Host smart-b4b881d0-7b97-418e-815c-07c490270670
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=37261353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.37261353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.3751423318
Short name T377
Test name
Test status
Simulation time 1629985284699 ps
CPU time 6523.74 seconds
Started Jul 01 12:12:59 PM PDT 24
Finished Jul 01 02:01:44 PM PDT 24
Peak memory 662200 kb
Host smart-8a144c9c-3ae7-433a-b78b-a29d4886aa23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3751423318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.3751423318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.4085266569
Short name T992
Test name
Test status
Simulation time 148330583952 ps
CPU time 4927.32 seconds
Started Jul 01 12:12:58 PM PDT 24
Finished Jul 01 01:35:07 PM PDT 24
Peak memory 557184 kb
Host smart-3f662be7-25ee-4d3b-b5f4-b75900e0672a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4085266569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.4085266569 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_app.419615934
Short name T241
Test name
Test status
Simulation time 8866639454 ps
CPU time 193.28 seconds
Started Jul 01 12:13:38 PM PDT 24
Finished Jul 01 12:16:52 PM PDT 24
Peak memory 242640 kb
Host smart-d5d013ca-b1ec-426d-bd08-440b84829b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419615934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.419615934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.100154672
Short name T331
Test name
Test status
Simulation time 28220980415 ps
CPU time 737.26 seconds
Started Jul 01 12:13:29 PM PDT 24
Finished Jul 01 12:25:47 PM PDT 24
Peak memory 234188 kb
Host smart-e1b1bc80-74db-4aeb-81dc-cab2525d67f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100154672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.100154672 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.3882003761
Short name T54
Test name
Test status
Simulation time 73357480 ps
CPU time 1.28 seconds
Started Jul 01 12:13:44 PM PDT 24
Finished Jul 01 12:13:47 PM PDT 24
Peak memory 217984 kb
Host smart-ed2e1e1e-e401-4685-b8dd-5f3a656c7e7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3882003761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3882003761 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.2396656700
Short name T881
Test name
Test status
Simulation time 71194999 ps
CPU time 1.26 seconds
Started Jul 01 12:13:43 PM PDT 24
Finished Jul 01 12:13:46 PM PDT 24
Peak memory 217936 kb
Host smart-685eff4c-7850-4361-9030-ef18e6172783
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2396656700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2396656700 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.3468610974
Short name T369
Test name
Test status
Simulation time 218748284 ps
CPU time 4.15 seconds
Started Jul 01 12:13:45 PM PDT 24
Finished Jul 01 12:13:51 PM PDT 24
Peak memory 220148 kb
Host smart-2e11377c-0322-491e-aa55-99b97f1c0209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468610974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3468610974 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.2980303287
Short name T826
Test name
Test status
Simulation time 30118109571 ps
CPU time 406.4 seconds
Started Jul 01 12:13:44 PM PDT 24
Finished Jul 01 12:20:31 PM PDT 24
Peak memory 259036 kb
Host smart-16eed952-9757-49d1-8a01-7ea90c9dbba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980303287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.2980303287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.299816254
Short name T797
Test name
Test status
Simulation time 1142903596 ps
CPU time 10.7 seconds
Started Jul 01 12:13:44 PM PDT 24
Finished Jul 01 12:13:57 PM PDT 24
Peak memory 224312 kb
Host smart-1715645d-570f-4637-b5cc-51f608328d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299816254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.299816254 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.1883849409
Short name T504
Test name
Test status
Simulation time 55877796 ps
CPU time 1.48 seconds
Started Jul 01 12:13:49 PM PDT 24
Finished Jul 01 12:13:51 PM PDT 24
Peak memory 218224 kb
Host smart-16e7a311-0e4c-492a-9e6e-de1ade70421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883849409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1883849409 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.1916132740
Short name T888
Test name
Test status
Simulation time 49012204156 ps
CPU time 462.31 seconds
Started Jul 01 12:13:29 PM PDT 24
Finished Jul 01 12:21:12 PM PDT 24
Peak memory 262072 kb
Host smart-1acf1611-ed28-4b6e-95f4-9957eb9896b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916132740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.1916132740 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.4092210881
Short name T551
Test name
Test status
Simulation time 258404876 ps
CPU time 17.31 seconds
Started Jul 01 12:13:27 PM PDT 24
Finished Jul 01 12:13:45 PM PDT 24
Peak memory 225968 kb
Host smart-a512b79d-05d4-4241-98f1-d555211bf598
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092210881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.4092210881 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.2126323150
Short name T237
Test name
Test status
Simulation time 17092841815 ps
CPU time 38.09 seconds
Started Jul 01 12:13:17 PM PDT 24
Finished Jul 01 12:13:56 PM PDT 24
Peak memory 218604 kb
Host smart-5b6d582e-0ec8-4669-b779-de690fe0abe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126323150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2126323150 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.3743095560
Short name T759
Test name
Test status
Simulation time 929334502 ps
CPU time 6.39 seconds
Started Jul 01 12:13:32 PM PDT 24
Finished Jul 01 12:13:39 PM PDT 24
Peak memory 218156 kb
Host smart-880d86fc-f28f-4568-a601-f5efc7dd4955
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743095560 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.3743095560 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.4120053683
Short name T799
Test name
Test status
Simulation time 148719396 ps
CPU time 5.57 seconds
Started Jul 01 12:13:38 PM PDT 24
Finished Jul 01 12:13:45 PM PDT 24
Peak memory 218164 kb
Host smart-f65a2049-917f-4409-a1d8-1106a37c3443
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120053683 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.4120053683 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.2216800861
Short name T472
Test name
Test status
Simulation time 67559259504 ps
CPU time 2066.82 seconds
Started Jul 01 12:13:32 PM PDT 24
Finished Jul 01 12:47:59 PM PDT 24
Peak memory 398192 kb
Host smart-a220b4f3-38cd-49a0-90cc-1be413b7137b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2216800861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.2216800861 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.228913074
Short name T605
Test name
Test status
Simulation time 93433596793 ps
CPU time 1903.06 seconds
Started Jul 01 12:13:26 PM PDT 24
Finished Jul 01 12:45:10 PM PDT 24
Peak memory 392996 kb
Host smart-5dbaa182-7e35-453e-a07f-c29740f56ca8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=228913074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.228913074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.3409131685
Short name T400
Test name
Test status
Simulation time 134251159242 ps
CPU time 1822.92 seconds
Started Jul 01 12:13:28 PM PDT 24
Finished Jul 01 12:43:51 PM PDT 24
Peak memory 342604 kb
Host smart-b807b150-135f-43ec-bf09-de2ad551c7df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3409131685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3409131685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.1922147522
Short name T801
Test name
Test status
Simulation time 33250958433 ps
CPU time 1139.68 seconds
Started Jul 01 12:13:34 PM PDT 24
Finished Jul 01 12:32:34 PM PDT 24
Peak memory 297756 kb
Host smart-0f64455c-98df-4456-835a-24369a940c84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1922147522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1922147522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.1556067598
Short name T1040
Test name
Test status
Simulation time 206381003599 ps
CPU time 5094.17 seconds
Started Jul 01 12:13:35 PM PDT 24
Finished Jul 01 01:38:31 PM PDT 24
Peak memory 658188 kb
Host smart-165ef747-967f-4442-b6a4-fb7294a056e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1556067598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.1556067598 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.2089639452
Short name T679
Test name
Test status
Simulation time 155869861199 ps
CPU time 4938.17 seconds
Started Jul 01 12:13:33 PM PDT 24
Finished Jul 01 01:35:53 PM PDT 24
Peak memory 560080 kb
Host smart-6e5c8514-9e3c-4606-9649-23ce15794770
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2089639452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.2089639452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.3182541478
Short name T645
Test name
Test status
Simulation time 52749373 ps
CPU time 0.84 seconds
Started Jul 01 12:14:23 PM PDT 24
Finished Jul 01 12:14:25 PM PDT 24
Peak memory 217812 kb
Host smart-21dd84d3-0301-4543-972b-b0574a45aa0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182541478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3182541478 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.3171068493
Short name T1001
Test name
Test status
Simulation time 16618890173 ps
CPU time 309.94 seconds
Started Jul 01 12:14:22 PM PDT 24
Finished Jul 01 12:19:33 PM PDT 24
Peak memory 248140 kb
Host smart-7c32531b-571d-48da-a9a7-3bc9adbfc82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171068493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3171068493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.2257342282
Short name T854
Test name
Test status
Simulation time 22767133556 ps
CPU time 926.21 seconds
Started Jul 01 12:14:04 PM PDT 24
Finished Jul 01 12:29:31 PM PDT 24
Peak memory 235636 kb
Host smart-26e991c2-4462-44d4-b4aa-7034f4a09197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257342282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2257342282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.4015282229
Short name T479
Test name
Test status
Simulation time 111361927 ps
CPU time 1.05 seconds
Started Jul 01 12:14:23 PM PDT 24
Finished Jul 01 12:14:25 PM PDT 24
Peak memory 217812 kb
Host smart-ef607637-6056-4010-bbea-f4d034762560
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4015282229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.4015282229 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.284266812
Short name T63
Test name
Test status
Simulation time 27033847 ps
CPU time 1.22 seconds
Started Jul 01 12:14:25 PM PDT 24
Finished Jul 01 12:14:27 PM PDT 24
Peak memory 218000 kb
Host smart-9608d0f6-4b95-464a-b073-ebb942bc5e1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=284266812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.284266812 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.789233086
Short name T124
Test name
Test status
Simulation time 7349395347 ps
CPU time 93.6 seconds
Started Jul 01 12:14:21 PM PDT 24
Finished Jul 01 12:15:55 PM PDT 24
Peak memory 232096 kb
Host smart-ec0dbafb-c600-4ea6-bc66-f9670107eb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789233086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.789233086 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.547003739
Short name T872
Test name
Test status
Simulation time 4880897687 ps
CPU time 190.58 seconds
Started Jul 01 12:14:19 PM PDT 24
Finished Jul 01 12:17:30 PM PDT 24
Peak memory 250916 kb
Host smart-d63fc79c-f7ad-48c2-bad5-d57147e30cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547003739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.547003739 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.3580486164
Short name T714
Test name
Test status
Simulation time 3681396071 ps
CPU time 10.09 seconds
Started Jul 01 12:14:19 PM PDT 24
Finished Jul 01 12:14:30 PM PDT 24
Peak memory 218128 kb
Host smart-18d93808-13c4-452f-bb50-b790c92bf4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580486164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3580486164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.4292520663
Short name T765
Test name
Test status
Simulation time 35835777 ps
CPU time 1.22 seconds
Started Jul 01 12:14:23 PM PDT 24
Finished Jul 01 12:14:24 PM PDT 24
Peak memory 218212 kb
Host smart-616bfd9a-2f42-40b5-a3db-f5ef46022edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292520663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.4292520663 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.3974115178
Short name T349
Test name
Test status
Simulation time 140208511850 ps
CPU time 1479.78 seconds
Started Jul 01 12:13:54 PM PDT 24
Finished Jul 01 12:38:34 PM PDT 24
Peak memory 334736 kb
Host smart-7ad8fe21-149a-4dbe-8b6a-48639bcce4e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974115178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.3974115178 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.929362085
Short name T598
Test name
Test status
Simulation time 1009888269 ps
CPU time 90.98 seconds
Started Jul 01 12:13:58 PM PDT 24
Finished Jul 01 12:15:30 PM PDT 24
Peak memory 228536 kb
Host smart-b6122ab2-ea9b-47fc-a1f3-5799630d61e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929362085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.929362085 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.4200719476
Short name T1015
Test name
Test status
Simulation time 895558385 ps
CPU time 9.59 seconds
Started Jul 01 12:13:49 PM PDT 24
Finished Jul 01 12:13:59 PM PDT 24
Peak memory 226196 kb
Host smart-f1d2e406-3433-406e-a586-013c57f37621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200719476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.4200719476 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.2911344544
Short name T735
Test name
Test status
Simulation time 366965141562 ps
CPU time 1533.44 seconds
Started Jul 01 12:14:25 PM PDT 24
Finished Jul 01 12:39:59 PM PDT 24
Peak memory 356584 kb
Host smart-c28929bb-685f-4a97-b458-cd6da6938a06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2911344544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.2911344544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.620678778
Short name T987
Test name
Test status
Simulation time 455429399 ps
CPU time 6.18 seconds
Started Jul 01 12:14:14 PM PDT 24
Finished Jul 01 12:14:20 PM PDT 24
Peak memory 218228 kb
Host smart-13413249-3c12-4bc2-8840-4bc8b74c44b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620678778 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.kmac_test_vectors_kmac.620678778 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.3058098163
Short name T960
Test name
Test status
Simulation time 104031844 ps
CPU time 5.61 seconds
Started Jul 01 12:14:13 PM PDT 24
Finished Jul 01 12:14:19 PM PDT 24
Peak memory 219080 kb
Host smart-27b97615-80d9-4da5-ad94-8e57c91b4606
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058098163 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.3058098163 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.745764202
Short name T920
Test name
Test status
Simulation time 176600892422 ps
CPU time 2183.04 seconds
Started Jul 01 12:14:08 PM PDT 24
Finished Jul 01 12:50:32 PM PDT 24
Peak memory 390012 kb
Host smart-160fa20b-a9c3-41ff-adff-d3ca6df4e1ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=745764202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.745764202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.2243074541
Short name T212
Test name
Test status
Simulation time 19761815244 ps
CPU time 1913.42 seconds
Started Jul 01 12:14:05 PM PDT 24
Finished Jul 01 12:45:59 PM PDT 24
Peak memory 394024 kb
Host smart-f6ac2fe7-7ff3-4f2c-a6de-4ffc0734bb92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2243074541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.2243074541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.3417597031
Short name T558
Test name
Test status
Simulation time 197347855062 ps
CPU time 1715.4 seconds
Started Jul 01 12:14:05 PM PDT 24
Finished Jul 01 12:42:41 PM PDT 24
Peak memory 337128 kb
Host smart-6a561fa7-d87b-403e-99ac-045f7385a525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3417597031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.3417597031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.2197458484
Short name T225
Test name
Test status
Simulation time 45765838582 ps
CPU time 1188.89 seconds
Started Jul 01 12:14:06 PM PDT 24
Finished Jul 01 12:33:56 PM PDT 24
Peak memory 298740 kb
Host smart-63d9f14b-6570-4dce-b98f-65bfc2f1fdd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2197458484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.2197458484 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.3985363052
Short name T660
Test name
Test status
Simulation time 139976879267 ps
CPU time 5473.75 seconds
Started Jul 01 12:14:19 PM PDT 24
Finished Jul 01 01:45:34 PM PDT 24
Peak memory 655868 kb
Host smart-78aba2e9-1bcc-4710-ba24-7ae315293b64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3985363052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.3985363052 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.1747645526
Short name T245
Test name
Test status
Simulation time 220846240414 ps
CPU time 4573.72 seconds
Started Jul 01 12:14:14 PM PDT 24
Finished Jul 01 01:30:29 PM PDT 24
Peak memory 566160 kb
Host smart-46f11830-07d2-4523-a278-9bdfb907bb09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1747645526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.1747645526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.2520164218
Short name T953
Test name
Test status
Simulation time 35867373 ps
CPU time 0.77 seconds
Started Jul 01 12:06:48 PM PDT 24
Finished Jul 01 12:06:50 PM PDT 24
Peak memory 217916 kb
Host smart-c3f2a3bc-ea47-4c39-9785-10cd6e434164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520164218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2520164218 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.4236364007
Short name T1053
Test name
Test status
Simulation time 32421188628 ps
CPU time 232.77 seconds
Started Jul 01 12:06:35 PM PDT 24
Finished Jul 01 12:10:29 PM PDT 24
Peak memory 244216 kb
Host smart-f6f5b397-ccf6-4cb5-ba8b-75b520d70731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236364007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.4236364007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.65423840
Short name T1011
Test name
Test status
Simulation time 60785075145 ps
CPU time 413.64 seconds
Started Jul 01 12:06:34 PM PDT 24
Finished Jul 01 12:13:28 PM PDT 24
Peak memory 250956 kb
Host smart-3ba99151-b757-4aa8-8a8e-81a2dca941f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65423840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.65423840 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.1115951217
Short name T519
Test name
Test status
Simulation time 84200002582 ps
CPU time 1240.19 seconds
Started Jul 01 12:06:24 PM PDT 24
Finished Jul 01 12:27:05 PM PDT 24
Peak memory 236952 kb
Host smart-04076503-b54d-4fe8-8c18-b9c8a850db75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115951217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.1115951217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.2512198813
Short name T601
Test name
Test status
Simulation time 4130338511 ps
CPU time 30.52 seconds
Started Jul 01 12:06:47 PM PDT 24
Finished Jul 01 12:07:19 PM PDT 24
Peak memory 226192 kb
Host smart-f33fb054-0048-4802-a82f-698809b55be5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2512198813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2512198813 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.1652813399
Short name T397
Test name
Test status
Simulation time 26332821 ps
CPU time 1.22 seconds
Started Jul 01 12:06:41 PM PDT 24
Finished Jul 01 12:06:43 PM PDT 24
Peak memory 218048 kb
Host smart-9cea89c6-8dfb-4751-8ea2-9e97ffea7ad6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1652813399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1652813399 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.3590571267
Short name T412
Test name
Test status
Simulation time 3945688532 ps
CPU time 37.88 seconds
Started Jul 01 12:06:48 PM PDT 24
Finished Jul 01 12:07:27 PM PDT 24
Peak memory 218328 kb
Host smart-09ba9c94-a4b7-4189-9a7a-41f40b01b7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590571267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3590571267 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.3108445086
Short name T602
Test name
Test status
Simulation time 112395658376 ps
CPU time 277.6 seconds
Started Jul 01 12:06:35 PM PDT 24
Finished Jul 01 12:11:13 PM PDT 24
Peak memory 242680 kb
Host smart-329a2fdb-8b21-4b40-a708-69d494c3d98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108445086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3108445086 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.2721919420
Short name T901
Test name
Test status
Simulation time 13980886725 ps
CPU time 269.46 seconds
Started Jul 01 12:06:34 PM PDT 24
Finished Jul 01 12:11:04 PM PDT 24
Peak memory 253916 kb
Host smart-f5f8fe75-4eaf-46a0-ab02-ce502337077c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721919420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2721919420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.1287252591
Short name T476
Test name
Test status
Simulation time 134411659 ps
CPU time 1.66 seconds
Started Jul 01 12:06:47 PM PDT 24
Finished Jul 01 12:06:50 PM PDT 24
Peak memory 218164 kb
Host smart-946c11f3-1f4f-4591-8ec5-7210cfb177c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287252591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1287252591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.2270176875
Short name T211
Test name
Test status
Simulation time 480102498118 ps
CPU time 1603.12 seconds
Started Jul 01 12:06:20 PM PDT 24
Finished Jul 01 12:33:04 PM PDT 24
Peak memory 361112 kb
Host smart-368f23eb-a375-4fcb-be2a-a44135ca23ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270176875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.2270176875 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.1296451893
Short name T14
Test name
Test status
Simulation time 5430152372 ps
CPU time 342.94 seconds
Started Jul 01 12:06:39 PM PDT 24
Finished Jul 01 12:12:22 PM PDT 24
Peak memory 253484 kb
Host smart-cafa7fc6-ddfa-40ff-a09f-ec7e400b000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296451893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1296451893 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.4032373358
Short name T120
Test name
Test status
Simulation time 7945977799 ps
CPU time 106.96 seconds
Started Jul 01 12:06:40 PM PDT 24
Finished Jul 01 12:08:28 PM PDT 24
Peak memory 287300 kb
Host smart-d63116b3-a142-4da7-bade-207c95db4c67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032373358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.4032373358 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.1375279485
Short name T209
Test name
Test status
Simulation time 3058765370 ps
CPU time 80.01 seconds
Started Jul 01 12:06:23 PM PDT 24
Finished Jul 01 12:07:44 PM PDT 24
Peak memory 229512 kb
Host smart-b4b0125d-b9b5-4b76-bd79-e14c63635a0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375279485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1375279485 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.3381366318
Short name T589
Test name
Test status
Simulation time 66478859 ps
CPU time 1.25 seconds
Started Jul 01 12:06:18 PM PDT 24
Finished Jul 01 12:06:20 PM PDT 24
Peak memory 218184 kb
Host smart-ca4a231f-7a17-455f-9b1a-c0299beb2173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381366318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3381366318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.824913784
Short name T456
Test name
Test status
Simulation time 3953764693 ps
CPU time 98.19 seconds
Started Jul 01 12:06:49 PM PDT 24
Finished Jul 01 12:08:27 PM PDT 24
Peak memory 250888 kb
Host smart-7cf28a54-d18e-4bee-b4d0-ba881596a3b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=824913784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.824913784 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.3181989994
Short name T800
Test name
Test status
Simulation time 251159587 ps
CPU time 6.04 seconds
Started Jul 01 12:06:35 PM PDT 24
Finished Jul 01 12:06:42 PM PDT 24
Peak memory 218076 kb
Host smart-6352554b-4e41-4a5b-a893-2fd072bdf879
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181989994 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.3181989994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.207946397
Short name T903
Test name
Test status
Simulation time 961276753 ps
CPU time 5.74 seconds
Started Jul 01 12:06:39 PM PDT 24
Finished Jul 01 12:06:45 PM PDT 24
Peak memory 218112 kb
Host smart-63e86173-2dea-46d0-ad28-03956983c3d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207946397 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.kmac_test_vectors_kmac_xof.207946397 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.1198578934
Short name T455
Test name
Test status
Simulation time 129042340744 ps
CPU time 2132.54 seconds
Started Jul 01 12:06:28 PM PDT 24
Finished Jul 01 12:42:02 PM PDT 24
Peak memory 401576 kb
Host smart-95fdae93-0236-4b67-861e-96cd72fc0a34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1198578934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.1198578934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.2684345470
Short name T342
Test name
Test status
Simulation time 90080912781 ps
CPU time 1971.54 seconds
Started Jul 01 12:06:24 PM PDT 24
Finished Jul 01 12:39:16 PM PDT 24
Peak memory 380488 kb
Host smart-7cce85b1-926d-47aa-b078-7e1bd29b6cad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2684345470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.2684345470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.2305374778
Short name T403
Test name
Test status
Simulation time 46949709766 ps
CPU time 1641.61 seconds
Started Jul 01 12:06:29 PM PDT 24
Finished Jul 01 12:33:53 PM PDT 24
Peak memory 336584 kb
Host smart-cddcd3a7-15b6-4af5-836b-b57da750cb1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2305374778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2305374778 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.3649287685
Short name T870
Test name
Test status
Simulation time 482267371442 ps
CPU time 1207.56 seconds
Started Jul 01 12:06:29 PM PDT 24
Finished Jul 01 12:26:38 PM PDT 24
Peak memory 302036 kb
Host smart-54d4e9a2-7268-452e-b39b-00eb5186816d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3649287685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3649287685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.907879241
Short name T204
Test name
Test status
Simulation time 194123991929 ps
CPU time 5400.07 seconds
Started Jul 01 12:06:30 PM PDT 24
Finished Jul 01 01:36:32 PM PDT 24
Peak memory 652696 kb
Host smart-e18dc190-d2ed-46e7-856b-1fe850db7cde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=907879241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.907879241 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.1806225287
Short name T898
Test name
Test status
Simulation time 214963446241 ps
CPU time 4791.6 seconds
Started Jul 01 12:06:35 PM PDT 24
Finished Jul 01 01:26:28 PM PDT 24
Peak memory 578944 kb
Host smart-27c1ac2c-0843-466c-9aae-e35b44cf0e25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1806225287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.1806225287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.1745576242
Short name T240
Test name
Test status
Simulation time 24212814 ps
CPU time 0.82 seconds
Started Jul 01 12:14:49 PM PDT 24
Finished Jul 01 12:14:52 PM PDT 24
Peak memory 217856 kb
Host smart-fa63dde2-3c4f-40f7-a6c4-8bddb6924699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745576242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.1745576242 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.796230275
Short name T1049
Test name
Test status
Simulation time 1849207179 ps
CPU time 45.19 seconds
Started Jul 01 12:14:35 PM PDT 24
Finished Jul 01 12:15:21 PM PDT 24
Peak memory 227764 kb
Host smart-f291685c-770f-4ea4-8e85-a87f0df981d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796230275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.796230275 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.3882934185
Short name T711
Test name
Test status
Simulation time 14463693881 ps
CPU time 412.03 seconds
Started Jul 01 12:14:24 PM PDT 24
Finished Jul 01 12:21:17 PM PDT 24
Peak memory 231536 kb
Host smart-6f026b4d-6a1a-42c5-b24f-8e5d3245903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882934185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.3882934185 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.549729897
Short name T752
Test name
Test status
Simulation time 3051686557 ps
CPU time 76.84 seconds
Started Jul 01 12:14:41 PM PDT 24
Finished Jul 01 12:15:58 PM PDT 24
Peak memory 231700 kb
Host smart-f8c3b63b-5384-49d4-8b44-f3ba8fad3019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549729897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.549729897 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.3175473334
Short name T526
Test name
Test status
Simulation time 1240244434 ps
CPU time 108.73 seconds
Started Jul 01 12:14:41 PM PDT 24
Finished Jul 01 12:16:31 PM PDT 24
Peak memory 242640 kb
Host smart-9ffb11a6-697f-4b20-9d39-07b683eaaeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175473334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3175473334 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.539850739
Short name T5
Test name
Test status
Simulation time 5679966647 ps
CPU time 12.43 seconds
Started Jul 01 12:14:46 PM PDT 24
Finished Jul 01 12:14:58 PM PDT 24
Peak memory 218268 kb
Host smart-3e7d8b31-09ba-4571-9c78-95dde0034bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539850739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.539850739 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.1425650857
Short name T1058
Test name
Test status
Simulation time 39632093 ps
CPU time 1.28 seconds
Started Jul 01 12:14:44 PM PDT 24
Finished Jul 01 12:14:46 PM PDT 24
Peak memory 218192 kb
Host smart-729b856f-e003-4e9a-a004-542193492c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425650857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1425650857 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.773274649
Short name T1035
Test name
Test status
Simulation time 53718436166 ps
CPU time 1425.19 seconds
Started Jul 01 12:14:24 PM PDT 24
Finished Jul 01 12:38:10 PM PDT 24
Peak memory 345052 kb
Host smart-8b0278df-b25b-4d1c-a5cb-f7e77dc0def4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773274649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_an
d_output.773274649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.224088315
Short name T930
Test name
Test status
Simulation time 4871103497 ps
CPU time 44.32 seconds
Started Jul 01 12:14:25 PM PDT 24
Finished Jul 01 12:15:10 PM PDT 24
Peak memory 226316 kb
Host smart-78d3f631-ace0-4b7e-8eee-c3d836209203
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224088315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.224088315 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.4249691760
Short name T454
Test name
Test status
Simulation time 7140304557 ps
CPU time 78.75 seconds
Started Jul 01 12:14:24 PM PDT 24
Finished Jul 01 12:15:43 PM PDT 24
Peak memory 218248 kb
Host smart-618d5055-e373-4962-a8fc-f1064c0035d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249691760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.4249691760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.1208439765
Short name T818
Test name
Test status
Simulation time 21010290201 ps
CPU time 936.89 seconds
Started Jul 01 12:14:44 PM PDT 24
Finished Jul 01 12:30:22 PM PDT 24
Peak memory 319832 kb
Host smart-248e107d-88e1-4a58-807e-3c654c4b356b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1208439765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.1208439765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.3437620750
Short name T1017
Test name
Test status
Simulation time 536321680 ps
CPU time 5.44 seconds
Started Jul 01 12:14:29 PM PDT 24
Finished Jul 01 12:14:35 PM PDT 24
Peak memory 218108 kb
Host smart-f316b466-c32c-4b6b-8162-d6822f67bf6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437620750 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.3437620750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.2347341885
Short name T921
Test name
Test status
Simulation time 187133713 ps
CPU time 6.24 seconds
Started Jul 01 12:14:33 PM PDT 24
Finished Jul 01 12:14:40 PM PDT 24
Peak memory 218128 kb
Host smart-3a8f42ee-8c16-4cd5-a6e6-1868ecc886f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347341885 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.2347341885 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.567713053
Short name T322
Test name
Test status
Simulation time 96214637854 ps
CPU time 2556.97 seconds
Started Jul 01 12:14:30 PM PDT 24
Finished Jul 01 12:57:07 PM PDT 24
Peak memory 393780 kb
Host smart-a5d0d3da-cb9f-4062-bccf-90d56d24a224
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=567713053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.567713053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.2894381387
Short name T129
Test name
Test status
Simulation time 19333835927 ps
CPU time 1955.32 seconds
Started Jul 01 12:14:32 PM PDT 24
Finished Jul 01 12:47:08 PM PDT 24
Peak memory 381936 kb
Host smart-ead3af2c-b34c-46d9-99de-1c5016a96a15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2894381387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.2894381387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.1148809642
Short name T229
Test name
Test status
Simulation time 101311927890 ps
CPU time 1762.52 seconds
Started Jul 01 12:14:32 PM PDT 24
Finished Jul 01 12:43:55 PM PDT 24
Peak memory 341460 kb
Host smart-57a1e62b-6d90-4646-aea8-5b033a13bef2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1148809642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.1148809642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.1329902325
Short name T619
Test name
Test status
Simulation time 43953749718 ps
CPU time 1181.09 seconds
Started Jul 01 12:14:31 PM PDT 24
Finished Jul 01 12:34:13 PM PDT 24
Peak memory 299488 kb
Host smart-78cd3309-cd2a-4577-8aca-485468730b3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1329902325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.1329902325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.2157803155
Short name T438
Test name
Test status
Simulation time 232620072705 ps
CPU time 5933.49 seconds
Started Jul 01 12:14:31 PM PDT 24
Finished Jul 01 01:53:26 PM PDT 24
Peak memory 644204 kb
Host smart-22d590d9-6331-4def-9169-953a729a1a92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2157803155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.2157803155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.2211193444
Short name T481
Test name
Test status
Simulation time 391998691111 ps
CPU time 4715.22 seconds
Started Jul 01 12:14:28 PM PDT 24
Finished Jul 01 01:33:04 PM PDT 24
Peak memory 576416 kb
Host smart-034952dc-b858-427c-a1e7-0b189883381c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2211193444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.2211193444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.3513222298
Short name T422
Test name
Test status
Simulation time 15032057 ps
CPU time 0.8 seconds
Started Jul 01 12:15:14 PM PDT 24
Finished Jul 01 12:15:15 PM PDT 24
Peak memory 217912 kb
Host smart-f7cf20bc-26ea-4df6-b0d5-88bb2c945fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513222298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3513222298 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.3722463742
Short name T355
Test name
Test status
Simulation time 15953799688 ps
CPU time 162.11 seconds
Started Jul 01 12:14:58 PM PDT 24
Finished Jul 01 12:17:41 PM PDT 24
Peak memory 239832 kb
Host smart-51962fd3-47ce-4afa-921a-07dd5f8e407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722463742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3722463742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.1582485876
Short name T865
Test name
Test status
Simulation time 9915390993 ps
CPU time 1005.88 seconds
Started Jul 01 12:14:55 PM PDT 24
Finished Jul 01 12:31:42 PM PDT 24
Peak memory 236892 kb
Host smart-4a85c94c-a24f-42f8-98e6-2e972476ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582485876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1582485876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.2509811057
Short name T899
Test name
Test status
Simulation time 3927677867 ps
CPU time 108.42 seconds
Started Jul 01 12:15:04 PM PDT 24
Finished Jul 01 12:16:53 PM PDT 24
Peak memory 235020 kb
Host smart-05928388-de02-4680-ba50-4c2adc8e0a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509811057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.2509811057 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.4067515498
Short name T1045
Test name
Test status
Simulation time 1474090496 ps
CPU time 47.29 seconds
Started Jul 01 12:15:06 PM PDT 24
Finished Jul 01 12:15:54 PM PDT 24
Peak memory 242616 kb
Host smart-4e79c062-d4b0-4e7e-840e-d2d695aca8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067515498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.4067515498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.2122981968
Short name T78
Test name
Test status
Simulation time 210809709 ps
CPU time 1.34 seconds
Started Jul 01 12:15:08 PM PDT 24
Finished Jul 01 12:15:10 PM PDT 24
Peak memory 218156 kb
Host smart-28b9b6b8-8791-4b2b-a373-48158f95a6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122981968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2122981968 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.4012673788
Short name T32
Test name
Test status
Simulation time 16869216401 ps
CPU time 814.89 seconds
Started Jul 01 12:14:51 PM PDT 24
Finished Jul 01 12:28:27 PM PDT 24
Peak memory 299764 kb
Host smart-65e32a89-b59a-4d9d-85ae-ad45385f5c55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012673788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.4012673788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.2381460995
Short name T686
Test name
Test status
Simulation time 47091623381 ps
CPU time 466.11 seconds
Started Jul 01 12:14:55 PM PDT 24
Finished Jul 01 12:22:41 PM PDT 24
Peak memory 258516 kb
Host smart-0400c5a6-5a4f-400c-a9ba-808118fb225b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381460995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2381460995 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.1333409913
Short name T524
Test name
Test status
Simulation time 1028054916 ps
CPU time 36.29 seconds
Started Jul 01 12:14:49 PM PDT 24
Finished Jul 01 12:15:28 PM PDT 24
Peak memory 226204 kb
Host smart-c7503af6-5239-4698-a653-3e25cab1f3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333409913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.1333409913 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.2058629588
Short name T731
Test name
Test status
Simulation time 264791087700 ps
CPU time 3191.63 seconds
Started Jul 01 12:15:15 PM PDT 24
Finished Jul 01 01:08:28 PM PDT 24
Peak memory 447676 kb
Host smart-4f55a0f5-831e-49cd-b58e-29f876bf413e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2058629588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.2058629588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.748637323
Short name T401
Test name
Test status
Simulation time 359589310 ps
CPU time 6.32 seconds
Started Jul 01 12:15:00 PM PDT 24
Finished Jul 01 12:15:07 PM PDT 24
Peak memory 218196 kb
Host smart-569f5cc0-a6df-4d30-8a53-6f7c8a8ad53d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748637323 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.kmac_test_vectors_kmac.748637323 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.1711164923
Short name T673
Test name
Test status
Simulation time 261827707 ps
CPU time 7.15 seconds
Started Jul 01 12:14:59 PM PDT 24
Finished Jul 01 12:15:06 PM PDT 24
Peak memory 219128 kb
Host smart-935ced07-6f84-4fb1-92be-19d20941835d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711164923 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.1711164923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.4058604604
Short name T219
Test name
Test status
Simulation time 133666589040 ps
CPU time 2140.67 seconds
Started Jul 01 12:14:55 PM PDT 24
Finished Jul 01 12:50:37 PM PDT 24
Peak memory 390640 kb
Host smart-b3243b42-51c9-44d0-a38e-ae01b37abaa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4058604604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.4058604604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.3619810821
Short name T722
Test name
Test status
Simulation time 401653961357 ps
CPU time 2182.9 seconds
Started Jul 01 12:14:55 PM PDT 24
Finished Jul 01 12:51:18 PM PDT 24
Peak memory 377256 kb
Host smart-bee2378d-544f-4fff-9fc7-dcab9284b579
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3619810821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3619810821 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.3075338544
Short name T458
Test name
Test status
Simulation time 46508890579 ps
CPU time 1636.95 seconds
Started Jul 01 12:14:58 PM PDT 24
Finished Jul 01 12:42:16 PM PDT 24
Peak memory 334872 kb
Host smart-56577143-5494-4205-842e-7a597c8e08dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3075338544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.3075338544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.186652201
Short name T346
Test name
Test status
Simulation time 53005267842 ps
CPU time 1449.11 seconds
Started Jul 01 12:14:57 PM PDT 24
Finished Jul 01 12:39:07 PM PDT 24
Peak memory 300304 kb
Host smart-c995bbc4-7fff-4ed7-b7c9-7624657552a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=186652201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.186652201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.579008964
Short name T739
Test name
Test status
Simulation time 189791768167 ps
CPU time 5846.83 seconds
Started Jul 01 12:15:00 PM PDT 24
Finished Jul 01 01:52:28 PM PDT 24
Peak memory 665816 kb
Host smart-90920c00-e9e4-41e8-8c24-dbe722b87359
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=579008964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.579008964 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.3635731258
Short name T432
Test name
Test status
Simulation time 162209052362 ps
CPU time 4884.91 seconds
Started Jul 01 12:15:00 PM PDT 24
Finished Jul 01 01:36:26 PM PDT 24
Peak memory 579720 kb
Host smart-b8e6907b-614c-4f98-b727-b8fe35798596
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3635731258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.3635731258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.799178863
Short name T95
Test name
Test status
Simulation time 13516229 ps
CPU time 0.84 seconds
Started Jul 01 12:15:42 PM PDT 24
Finished Jul 01 12:15:43 PM PDT 24
Peak memory 217852 kb
Host smart-eab40ee3-3bb1-43fb-8ffb-749aca0569ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799178863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.799178863 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.917582219
Short name T740
Test name
Test status
Simulation time 6270777327 ps
CPU time 170.83 seconds
Started Jul 01 12:15:33 PM PDT 24
Finished Jul 01 12:18:24 PM PDT 24
Peak memory 238984 kb
Host smart-1f04e1b7-73d3-48b5-810d-4c4a0212cf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917582219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.917582219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.2527896540
Short name T747
Test name
Test status
Simulation time 65602544716 ps
CPU time 668.23 seconds
Started Jul 01 12:15:19 PM PDT 24
Finished Jul 01 12:26:28 PM PDT 24
Peak memory 234796 kb
Host smart-a5859892-40f0-4b53-b502-ae04a8fa8620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527896540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.2527896540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_error.532439799
Short name T678
Test name
Test status
Simulation time 20801240798 ps
CPU time 356.14 seconds
Started Jul 01 12:15:35 PM PDT 24
Finished Jul 01 12:21:32 PM PDT 24
Peak memory 256000 kb
Host smart-b505c44b-bf30-4783-952a-f74e1e47a12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532439799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.532439799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.4194173806
Short name T514
Test name
Test status
Simulation time 1425908086 ps
CPU time 11.06 seconds
Started Jul 01 12:15:40 PM PDT 24
Finished Jul 01 12:15:52 PM PDT 24
Peak memory 218136 kb
Host smart-01dea14e-e2e6-4d2b-ba8d-2316bc8786f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194173806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.4194173806 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.2884565763
Short name T788
Test name
Test status
Simulation time 166663912 ps
CPU time 1.58 seconds
Started Jul 01 12:15:38 PM PDT 24
Finished Jul 01 12:15:40 PM PDT 24
Peak memory 218292 kb
Host smart-e932e4cd-bef7-4d12-8941-4c25cfe86377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884565763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2884565763 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.1920765320
Short name T1026
Test name
Test status
Simulation time 6124958161 ps
CPU time 575.53 seconds
Started Jul 01 12:15:13 PM PDT 24
Finished Jul 01 12:24:50 PM PDT 24
Peak memory 276152 kb
Host smart-e748f6b5-d90d-488c-81c6-e69d48d6ee34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920765320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.1920765320 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.3159252612
Short name T350
Test name
Test status
Simulation time 3947887010 ps
CPU time 122.48 seconds
Started Jul 01 12:15:13 PM PDT 24
Finished Jul 01 12:17:16 PM PDT 24
Peak memory 233816 kb
Host smart-6149604b-a481-4d4b-8721-b4d04c06aa6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159252612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3159252612 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.1984807272
Short name T318
Test name
Test status
Simulation time 5395891235 ps
CPU time 50.34 seconds
Started Jul 01 12:15:12 PM PDT 24
Finished Jul 01 12:16:03 PM PDT 24
Peak memory 226356 kb
Host smart-b5b51da8-ed7d-41ce-a5f0-88917c6c94b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984807272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1984807272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.2362599718
Short name T653
Test name
Test status
Simulation time 22532572825 ps
CPU time 633.33 seconds
Started Jul 01 12:15:40 PM PDT 24
Finished Jul 01 12:26:14 PM PDT 24
Peak memory 308512 kb
Host smart-0f25d75f-f0ab-4452-ab22-3260ae972e6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2362599718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2362599718 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.1545065875
Short name T642
Test name
Test status
Simulation time 721054368 ps
CPU time 6.46 seconds
Started Jul 01 12:15:30 PM PDT 24
Finished Jul 01 12:15:37 PM PDT 24
Peak memory 218212 kb
Host smart-760e351d-058a-4838-9f6f-4da9badac70e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545065875 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.1545065875 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.2906773118
Short name T344
Test name
Test status
Simulation time 757646238 ps
CPU time 5.95 seconds
Started Jul 01 12:15:34 PM PDT 24
Finished Jul 01 12:15:41 PM PDT 24
Peak memory 218188 kb
Host smart-c401872b-0f42-4865-8f66-199ff4eb7095
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906773118 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.2906773118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.394303283
Short name T847
Test name
Test status
Simulation time 20851215963 ps
CPU time 2015.52 seconds
Started Jul 01 12:15:26 PM PDT 24
Finished Jul 01 12:49:02 PM PDT 24
Peak memory 393372 kb
Host smart-a0d455c3-a1a0-4bab-9fe1-3fa44b6edf18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=394303283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.394303283 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.3669579375
Short name T235
Test name
Test status
Simulation time 75326350346 ps
CPU time 1859.1 seconds
Started Jul 01 12:15:26 PM PDT 24
Finished Jul 01 12:46:26 PM PDT 24
Peak memory 381376 kb
Host smart-42c534c8-740c-424f-92f0-3bd22fe16674
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3669579375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.3669579375 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.2130811346
Short name T457
Test name
Test status
Simulation time 61962671720 ps
CPU time 1777.09 seconds
Started Jul 01 12:15:24 PM PDT 24
Finished Jul 01 12:45:02 PM PDT 24
Peak memory 340408 kb
Host smart-7944cb63-971e-401c-ad82-c2adb1c0ea4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2130811346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.2130811346 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.1722850540
Short name T779
Test name
Test status
Simulation time 38621188433 ps
CPU time 1172.28 seconds
Started Jul 01 12:15:23 PM PDT 24
Finished Jul 01 12:34:56 PM PDT 24
Peak memory 299016 kb
Host smart-a1cf4e9e-9f65-4a38-86e5-26827a72aa33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1722850540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.1722850540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.3601115853
Short name T878
Test name
Test status
Simulation time 274602851859 ps
CPU time 6244.15 seconds
Started Jul 01 12:15:34 PM PDT 24
Finished Jul 01 01:59:40 PM PDT 24
Peak memory 654100 kb
Host smart-8915039b-cf97-468f-b473-d478ece9fe94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3601115853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.3601115853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.3950011440
Short name T725
Test name
Test status
Simulation time 54920967743 ps
CPU time 4609.64 seconds
Started Jul 01 12:15:31 PM PDT 24
Finished Jul 01 01:32:22 PM PDT 24
Peak memory 584188 kb
Host smart-f5bb7e5d-c6a9-41ae-97db-b638526699a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3950011440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.3950011440 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.157496283
Short name T855
Test name
Test status
Simulation time 37484125 ps
CPU time 0.79 seconds
Started Jul 01 12:16:00 PM PDT 24
Finished Jul 01 12:16:01 PM PDT 24
Peak memory 217940 kb
Host smart-ffc96f87-ef87-421e-a991-9274286ca8ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157496283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.157496283 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.2945762148
Short name T726
Test name
Test status
Simulation time 15061389459 ps
CPU time 103.65 seconds
Started Jul 01 12:15:50 PM PDT 24
Finished Jul 01 12:17:34 PM PDT 24
Peak memory 234796 kb
Host smart-62bd6b17-46fd-4e67-8c92-254cfefc2772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945762148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2945762148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.3398868656
Short name T161
Test name
Test status
Simulation time 126955410215 ps
CPU time 789.32 seconds
Started Jul 01 12:15:41 PM PDT 24
Finished Jul 01 12:28:51 PM PDT 24
Peak memory 242732 kb
Host smart-52b459d9-9b9a-4bb2-898b-1e821b9f77e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398868656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3398868656 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.1830472162
Short name T473
Test name
Test status
Simulation time 44564440991 ps
CPU time 361.34 seconds
Started Jul 01 12:15:50 PM PDT 24
Finished Jul 01 12:21:52 PM PDT 24
Peak memory 250668 kb
Host smart-c368b131-8b63-40a4-b385-f7fa3b6c6e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830472162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1830472162 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.1049601137
Short name T478
Test name
Test status
Simulation time 21362331753 ps
CPU time 403.97 seconds
Started Jul 01 12:15:50 PM PDT 24
Finished Jul 01 12:22:35 PM PDT 24
Peak memory 259076 kb
Host smart-dab44728-a188-4cf6-bf7f-7cc5327d4fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049601137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1049601137 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.354643635
Short name T427
Test name
Test status
Simulation time 537176522 ps
CPU time 2.24 seconds
Started Jul 01 12:15:55 PM PDT 24
Finished Jul 01 12:15:58 PM PDT 24
Peak memory 218116 kb
Host smart-d3a45812-e829-4b8e-8a67-b783a1abfb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354643635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.354643635 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.1682015825
Short name T46
Test name
Test status
Simulation time 824324035 ps
CPU time 18.72 seconds
Started Jul 01 12:15:53 PM PDT 24
Finished Jul 01 12:16:12 PM PDT 24
Peak memory 234540 kb
Host smart-33576d71-eda4-414b-ad1c-88f8b7b3dbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682015825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1682015825 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.1455025880
Short name T88
Test name
Test status
Simulation time 73263625946 ps
CPU time 2677.12 seconds
Started Jul 01 12:15:40 PM PDT 24
Finished Jul 01 01:00:18 PM PDT 24
Peak memory 434860 kb
Host smart-5f526e3c-9e8e-4194-8288-4565a50ae4b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455025880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.1455025880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.2161077231
Short name T464
Test name
Test status
Simulation time 2526842444 ps
CPU time 17.53 seconds
Started Jul 01 12:15:39 PM PDT 24
Finished Jul 01 12:15:57 PM PDT 24
Peak memory 225224 kb
Host smart-84005b88-2ebf-4b5c-ba49-36235aa54e06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161077231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2161077231 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.84280311
Short name T1054
Test name
Test status
Simulation time 1758581723 ps
CPU time 42.05 seconds
Started Jul 01 12:15:42 PM PDT 24
Finished Jul 01 12:16:25 PM PDT 24
Peak memory 226232 kb
Host smart-841c32cb-7d1d-4869-a3b7-1c386553dbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84280311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.84280311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.1614993774
Short name T900
Test name
Test status
Simulation time 61563664987 ps
CPU time 353.85 seconds
Started Jul 01 12:15:53 PM PDT 24
Finished Jul 01 12:21:48 PM PDT 24
Peak memory 257284 kb
Host smart-6be6ab34-4d38-4881-9afd-bea4aea41a19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1614993774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1614993774 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.3574590082
Short name T150
Test name
Test status
Simulation time 1222592829 ps
CPU time 8.27 seconds
Started Jul 01 12:15:43 PM PDT 24
Finished Jul 01 12:15:52 PM PDT 24
Peak memory 219148 kb
Host smart-1f1e903a-e918-482c-a9f8-fb0c3f10a2e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574590082 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.3574590082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.4100166004
Short name T831
Test name
Test status
Simulation time 106979433 ps
CPU time 5.38 seconds
Started Jul 01 12:15:49 PM PDT 24
Finished Jul 01 12:15:55 PM PDT 24
Peak memory 218224 kb
Host smart-4b15a432-90aa-41f6-8264-52bba574a913
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100166004 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.4100166004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.3558427438
Short name T791
Test name
Test status
Simulation time 66196879593 ps
CPU time 1940.21 seconds
Started Jul 01 12:15:43 PM PDT 24
Finished Jul 01 12:48:05 PM PDT 24
Peak memory 385028 kb
Host smart-beb2deac-de77-4e72-8356-dfd9088fccc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3558427438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.3558427438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.2077882780
Short name T859
Test name
Test status
Simulation time 19095608536 ps
CPU time 1830.05 seconds
Started Jul 01 12:15:45 PM PDT 24
Finished Jul 01 12:46:16 PM PDT 24
Peak memory 377892 kb
Host smart-064568a9-b1ca-4d4f-99f5-d73a61c73e6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2077882780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.2077882780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.659543912
Short name T815
Test name
Test status
Simulation time 50639096279 ps
CPU time 1676.7 seconds
Started Jul 01 12:15:43 PM PDT 24
Finished Jul 01 12:43:41 PM PDT 24
Peak memory 344532 kb
Host smart-87a2faf7-8e44-4646-9841-51c270dbf43f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=659543912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.659543912 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.1259672733
Short name T309
Test name
Test status
Simulation time 33701706056 ps
CPU time 1274.52 seconds
Started Jul 01 12:15:46 PM PDT 24
Finished Jul 01 12:37:01 PM PDT 24
Peak memory 301932 kb
Host smart-ff77f5ee-efbc-47c2-af5d-9c4c9f734a0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1259672733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.1259672733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.3821268991
Short name T119
Test name
Test status
Simulation time 129307882550 ps
CPU time 5771.94 seconds
Started Jul 01 12:15:45 PM PDT 24
Finished Jul 01 01:51:59 PM PDT 24
Peak memory 656108 kb
Host smart-46d7874a-e8d5-4081-8821-d426057f0719
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3821268991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3821268991 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.3015264539
Short name T982
Test name
Test status
Simulation time 1044957894383 ps
CPU time 5788.06 seconds
Started Jul 01 12:15:44 PM PDT 24
Finished Jul 01 01:52:13 PM PDT 24
Peak memory 571884 kb
Host smart-988086aa-eab9-4607-8007-953e686a9597
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3015264539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3015264539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.4004538012
Short name T626
Test name
Test status
Simulation time 17605852 ps
CPU time 0.81 seconds
Started Jul 01 12:16:24 PM PDT 24
Finished Jul 01 12:16:26 PM PDT 24
Peak memory 217904 kb
Host smart-22210529-847b-4189-9b0c-a1cff209524a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004538012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.4004538012 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.3641541228
Short name T544
Test name
Test status
Simulation time 2995569377 ps
CPU time 52.52 seconds
Started Jul 01 12:16:14 PM PDT 24
Finished Jul 01 12:17:07 PM PDT 24
Peak memory 229380 kb
Host smart-5535db32-db27-421f-a5ec-f79370840414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641541228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3641541228 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.2193778382
Short name T164
Test name
Test status
Simulation time 151119555752 ps
CPU time 531.41 seconds
Started Jul 01 12:16:07 PM PDT 24
Finished Jul 01 12:25:00 PM PDT 24
Peak memory 240264 kb
Host smart-b3c906a3-1e73-403e-a269-b1b6924a34a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193778382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.2193778382 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.410372956
Short name T706
Test name
Test status
Simulation time 10730984660 ps
CPU time 211.07 seconds
Started Jul 01 12:16:25 PM PDT 24
Finished Jul 01 12:19:57 PM PDT 24
Peak memory 242172 kb
Host smart-41fb6e9f-0f51-4eac-939c-8919af6b87d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410372956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.410372956 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.1319314335
Short name T708
Test name
Test status
Simulation time 9321863806 ps
CPU time 80.23 seconds
Started Jul 01 12:16:19 PM PDT 24
Finished Jul 01 12:17:40 PM PDT 24
Peak memory 242728 kb
Host smart-fee8c607-30db-4b48-a443-5a30b33aba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319314335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1319314335 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.4239939788
Short name T723
Test name
Test status
Simulation time 1087020418 ps
CPU time 8.17 seconds
Started Jul 01 12:16:18 PM PDT 24
Finished Jul 01 12:16:27 PM PDT 24
Peak memory 218144 kb
Host smart-bb62651f-3a4f-4267-883b-83e424a4cf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239939788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.4239939788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.2616514648
Short name T1
Test name
Test status
Simulation time 254468829 ps
CPU time 1.36 seconds
Started Jul 01 12:16:23 PM PDT 24
Finished Jul 01 12:16:25 PM PDT 24
Peak memory 218148 kb
Host smart-a206d0b6-395c-47d0-9c3c-56b103c1616a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616514648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2616514648 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.3502666857
Short name T595
Test name
Test status
Simulation time 60850320156 ps
CPU time 2968.4 seconds
Started Jul 01 12:16:06 PM PDT 24
Finished Jul 01 01:05:36 PM PDT 24
Peak memory 494756 kb
Host smart-d393617c-f3b1-48c3-b2cb-1231abece78f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502666857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.3502666857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.2164108786
Short name T720
Test name
Test status
Simulation time 8807844877 ps
CPU time 243.11 seconds
Started Jul 01 12:16:10 PM PDT 24
Finished Jul 01 12:20:13 PM PDT 24
Peak memory 242684 kb
Host smart-85c88b15-caba-476a-87b9-5fcb74fc4645
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164108786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2164108786 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.1898403653
Short name T288
Test name
Test status
Simulation time 519861656 ps
CPU time 25.1 seconds
Started Jul 01 12:15:59 PM PDT 24
Finished Jul 01 12:16:25 PM PDT 24
Peak memory 226240 kb
Host smart-4b479210-10c6-4210-8eb5-ec87a94a50e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898403653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1898403653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.3192751954
Short name T109
Test name
Test status
Simulation time 8219944546 ps
CPU time 742.05 seconds
Started Jul 01 12:16:25 PM PDT 24
Finished Jul 01 12:28:48 PM PDT 24
Peak memory 308188 kb
Host smart-2f57043f-e0f8-475b-ae7c-a799d987691b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3192751954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3192751954 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.210919329
Short name T948
Test name
Test status
Simulation time 439696831 ps
CPU time 5.86 seconds
Started Jul 01 12:16:15 PM PDT 24
Finished Jul 01 12:16:21 PM PDT 24
Peak memory 218136 kb
Host smart-c74787ce-def6-41de-aaa3-fa6c9e1e953f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210919329 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.kmac_test_vectors_kmac.210919329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.653637578
Short name T631
Test name
Test status
Simulation time 460388070 ps
CPU time 5.52 seconds
Started Jul 01 12:16:15 PM PDT 24
Finished Jul 01 12:16:21 PM PDT 24
Peak memory 218140 kb
Host smart-73c2c941-588a-4f3d-ab9a-678fbcf34fff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653637578 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.kmac_test_vectors_kmac_xof.653637578 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.2930415522
Short name T545
Test name
Test status
Simulation time 86385040965 ps
CPU time 2069.92 seconds
Started Jul 01 12:16:09 PM PDT 24
Finished Jul 01 12:50:40 PM PDT 24
Peak memory 403492 kb
Host smart-d7e36504-187b-4e38-bad0-ac2b6482c0d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2930415522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2930415522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.4079417432
Short name T268
Test name
Test status
Simulation time 371371198340 ps
CPU time 2357.57 seconds
Started Jul 01 12:16:07 PM PDT 24
Finished Jul 01 12:55:25 PM PDT 24
Peak memory 390720 kb
Host smart-378fa2bb-1191-4b9c-a714-df18e6110f54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4079417432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.4079417432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.651842475
Short name T756
Test name
Test status
Simulation time 191482057169 ps
CPU time 1607.39 seconds
Started Jul 01 12:16:13 PM PDT 24
Finished Jul 01 12:43:01 PM PDT 24
Peak memory 331444 kb
Host smart-5f1f8417-b2f4-4cc2-b234-4123401b9695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=651842475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.651842475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.4110553333
Short name T373
Test name
Test status
Simulation time 44179732433 ps
CPU time 1320.99 seconds
Started Jul 01 12:16:09 PM PDT 24
Finished Jul 01 12:38:10 PM PDT 24
Peak memory 300960 kb
Host smart-b4c84ac9-83d5-467e-af15-b644881d2233
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4110553333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.4110553333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.3242187724
Short name T244
Test name
Test status
Simulation time 1363721165167 ps
CPU time 6450.64 seconds
Started Jul 01 12:16:13 PM PDT 24
Finished Jul 01 02:03:45 PM PDT 24
Peak memory 649336 kb
Host smart-b9d0d7f7-44c5-4ade-8818-3fddc2e83df3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3242187724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3242187724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.3204812733
Short name T556
Test name
Test status
Simulation time 231578552866 ps
CPU time 5481.22 seconds
Started Jul 01 12:16:13 PM PDT 24
Finished Jul 01 01:47:36 PM PDT 24
Peak memory 587520 kb
Host smart-b265f153-0c60-4dcd-a23f-6a24d390179a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3204812733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.3204812733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.1869483714
Short name T477
Test name
Test status
Simulation time 22682776 ps
CPU time 0.82 seconds
Started Jul 01 12:16:47 PM PDT 24
Finished Jul 01 12:16:49 PM PDT 24
Peak memory 217872 kb
Host smart-ef88201e-f668-4055-8ed6-8d255421cc0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869483714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1869483714 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.2520333195
Short name T1020
Test name
Test status
Simulation time 11542897321 ps
CPU time 354.79 seconds
Started Jul 01 12:16:32 PM PDT 24
Finished Jul 01 12:22:28 PM PDT 24
Peak memory 250696 kb
Host smart-33f46703-96d0-4c0d-9c96-67518c2962e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520333195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2520333195 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.430005646
Short name T944
Test name
Test status
Simulation time 4889660171 ps
CPU time 45.12 seconds
Started Jul 01 12:16:28 PM PDT 24
Finished Jul 01 12:17:14 PM PDT 24
Peak memory 223980 kb
Host smart-9aca44e6-d054-4a2f-9b7d-2102af36bbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430005646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.430005646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_error.1729445780
Short name T956
Test name
Test status
Simulation time 6987687491 ps
CPU time 217.6 seconds
Started Jul 01 12:16:38 PM PDT 24
Finished Jul 01 12:20:17 PM PDT 24
Peak memory 251804 kb
Host smart-a1c62b01-3fc6-4780-97ef-ff51f1d454b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729445780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1729445780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.1955810912
Short name T817
Test name
Test status
Simulation time 24853698868 ps
CPU time 21.5 seconds
Started Jul 01 12:16:38 PM PDT 24
Finished Jul 01 12:17:01 PM PDT 24
Peak memory 218164 kb
Host smart-a397e090-5b73-49af-9f1f-f3a296a72c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955810912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.1955810912 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.1746536826
Short name T812
Test name
Test status
Simulation time 262153682717 ps
CPU time 1864.68 seconds
Started Jul 01 12:16:28 PM PDT 24
Finished Jul 01 12:47:34 PM PDT 24
Peak memory 356268 kb
Host smart-31304e30-b32f-40c3-9a49-f01bd971547c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746536826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.1746536826 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.2888423441
Short name T863
Test name
Test status
Simulation time 26361565607 ps
CPU time 328.2 seconds
Started Jul 01 12:16:27 PM PDT 24
Finished Jul 01 12:21:56 PM PDT 24
Peak memory 245828 kb
Host smart-6a23f27c-a8e0-46d2-987c-a3354557acfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888423441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2888423441 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.1398143089
Short name T243
Test name
Test status
Simulation time 1353454847 ps
CPU time 27.65 seconds
Started Jul 01 12:16:25 PM PDT 24
Finished Jul 01 12:16:53 PM PDT 24
Peak memory 218104 kb
Host smart-1e7d5e70-e739-46ed-859c-2ef02436306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398143089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1398143089 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.3524464072
Short name T467
Test name
Test status
Simulation time 36620726579 ps
CPU time 1399.42 seconds
Started Jul 01 12:16:48 PM PDT 24
Finished Jul 01 12:40:08 PM PDT 24
Peak memory 378520 kb
Host smart-f75f1e8c-70e2-4b9d-beed-2bae8e4757e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3524464072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3524464072 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.4074192928
Short name T650
Test name
Test status
Simulation time 262876447 ps
CPU time 6.97 seconds
Started Jul 01 12:16:33 PM PDT 24
Finished Jul 01 12:16:41 PM PDT 24
Peak memory 218156 kb
Host smart-2c10c2a1-8f78-4ef4-a2e8-d19c9f469c3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074192928 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.4074192928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.453430408
Short name T534
Test name
Test status
Simulation time 111503108 ps
CPU time 5.46 seconds
Started Jul 01 12:16:34 PM PDT 24
Finished Jul 01 12:16:40 PM PDT 24
Peak memory 218160 kb
Host smart-6250c243-bcbb-4953-b37b-e91048611b83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453430408 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.kmac_test_vectors_kmac_xof.453430408 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.3941426009
Short name T425
Test name
Test status
Simulation time 76095649809 ps
CPU time 2196.25 seconds
Started Jul 01 12:16:30 PM PDT 24
Finished Jul 01 12:53:06 PM PDT 24
Peak memory 395432 kb
Host smart-7fa36dc2-bd73-476d-85ec-674f29426cb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3941426009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.3941426009 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.1436747608
Short name T991
Test name
Test status
Simulation time 63054277727 ps
CPU time 2121.93 seconds
Started Jul 01 12:16:29 PM PDT 24
Finished Jul 01 12:51:52 PM PDT 24
Peak memory 387648 kb
Host smart-603f1150-9c96-4d66-9b6b-7190a2b85043
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1436747608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.1436747608 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.3141629394
Short name T299
Test name
Test status
Simulation time 257118894470 ps
CPU time 1768.66 seconds
Started Jul 01 12:16:28 PM PDT 24
Finished Jul 01 12:45:58 PM PDT 24
Peak memory 340604 kb
Host smart-e1e6513b-49df-4ff5-bf84-b9cae1e3d312
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3141629394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.3141629394 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.2404504522
Short name T691
Test name
Test status
Simulation time 34683716542 ps
CPU time 1231.04 seconds
Started Jul 01 12:16:33 PM PDT 24
Finished Jul 01 12:37:05 PM PDT 24
Peak memory 303092 kb
Host smart-58a656dc-d493-41d6-b8b3-0be6a99ea0cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2404504522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.2404504522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.2150490362
Short name T830
Test name
Test status
Simulation time 272693827627 ps
CPU time 5701.02 seconds
Started Jul 01 12:16:33 PM PDT 24
Finished Jul 01 01:51:36 PM PDT 24
Peak memory 649520 kb
Host smart-36259f5a-3cb0-47c9-8f06-2188e20eba1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2150490362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.2150490362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.2155575976
Short name T250
Test name
Test status
Simulation time 393091803557 ps
CPU time 4937.17 seconds
Started Jul 01 12:16:32 PM PDT 24
Finished Jul 01 01:38:51 PM PDT 24
Peak memory 560884 kb
Host smart-28e4a383-8f0d-458f-b662-0da9ad543198
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2155575976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.2155575976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.2984554443
Short name T570
Test name
Test status
Simulation time 62380122 ps
CPU time 0.89 seconds
Started Jul 01 12:17:19 PM PDT 24
Finished Jul 01 12:17:20 PM PDT 24
Peak memory 217916 kb
Host smart-5a67ed74-ad53-46cb-a16e-3a3223fa4a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984554443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2984554443 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.3711322351
Short name T802
Test name
Test status
Simulation time 7707376520 ps
CPU time 115.78 seconds
Started Jul 01 12:17:02 PM PDT 24
Finished Jul 01 12:18:58 PM PDT 24
Peak memory 236684 kb
Host smart-c84aeafb-92d8-4c30-b7db-8a803e860930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711322351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3711322351 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.2505858426
Short name T1055
Test name
Test status
Simulation time 9807069519 ps
CPU time 338.15 seconds
Started Jul 01 12:16:53 PM PDT 24
Finished Jul 01 12:22:32 PM PDT 24
Peak memory 230480 kb
Host smart-bbf9c98c-d224-4683-ab74-4d96e7793143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505858426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2505858426 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.2997538585
Short name T869
Test name
Test status
Simulation time 7389334371 ps
CPU time 362.47 seconds
Started Jul 01 12:17:04 PM PDT 24
Finished Jul 01 12:23:07 PM PDT 24
Peak memory 250956 kb
Host smart-5a763b84-8b2c-4e10-96d4-e730354ccae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997538585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2997538585 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.321975960
Short name T334
Test name
Test status
Simulation time 5631510671 ps
CPU time 143.3 seconds
Started Jul 01 12:17:08 PM PDT 24
Finished Jul 01 12:19:32 PM PDT 24
Peak memory 242688 kb
Host smart-bab080b9-e0ee-4b05-bdf4-ba8a1acade7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321975960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.321975960 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.2579296361
Short name T378
Test name
Test status
Simulation time 13704983635 ps
CPU time 9.05 seconds
Started Jul 01 12:17:13 PM PDT 24
Finished Jul 01 12:17:23 PM PDT 24
Peak memory 223756 kb
Host smart-b4dcb0a9-583d-467d-9249-612a4bb93812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579296361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2579296361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.744892775
Short name T639
Test name
Test status
Simulation time 26500030 ps
CPU time 1.25 seconds
Started Jul 01 12:17:13 PM PDT 24
Finished Jul 01 12:17:14 PM PDT 24
Peak memory 218272 kb
Host smart-55292ece-3a00-4999-941c-fbb387412cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744892775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.744892775 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.2530884461
Short name T933
Test name
Test status
Simulation time 8509939630 ps
CPU time 457.6 seconds
Started Jul 01 12:16:53 PM PDT 24
Finished Jul 01 12:24:32 PM PDT 24
Peak memory 261420 kb
Host smart-ea6b6fe9-ff86-4d08-8b4a-71ffe7e15305
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530884461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.2530884461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.1982697419
Short name T550
Test name
Test status
Simulation time 25560588689 ps
CPU time 394.99 seconds
Started Jul 01 12:16:53 PM PDT 24
Finished Jul 01 12:23:29 PM PDT 24
Peak memory 251916 kb
Host smart-b0396f4c-0a8e-467c-9609-5203479f8376
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982697419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1982697419 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.2243241526
Short name T263
Test name
Test status
Simulation time 231601859 ps
CPU time 2.7 seconds
Started Jul 01 12:16:54 PM PDT 24
Finished Jul 01 12:16:57 PM PDT 24
Peak memory 225444 kb
Host smart-cd43e0a7-abcd-4576-89c2-ef93f4136386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243241526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2243241526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.3461428700
Short name T737
Test name
Test status
Simulation time 20724106123 ps
CPU time 931.27 seconds
Started Jul 01 12:17:14 PM PDT 24
Finished Jul 01 12:32:46 PM PDT 24
Peak memory 291744 kb
Host smart-2b989950-9beb-4260-86df-0507c31f19fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3461428700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3461428700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.3447580759
Short name T750
Test name
Test status
Simulation time 309806886 ps
CPU time 5.96 seconds
Started Jul 01 12:16:57 PM PDT 24
Finished Jul 01 12:17:04 PM PDT 24
Peak memory 219036 kb
Host smart-820211bc-a484-4c13-89c0-d9d03428c6a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447580759 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.3447580759 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1708659035
Short name T392
Test name
Test status
Simulation time 119339253 ps
CPU time 6.61 seconds
Started Jul 01 12:17:03 PM PDT 24
Finished Jul 01 12:17:10 PM PDT 24
Peak memory 218176 kb
Host smart-25a5f716-964f-441d-ba66-731022311901
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708659035 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1708659035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.359803026
Short name T497
Test name
Test status
Simulation time 101121516441 ps
CPU time 2295.27 seconds
Started Jul 01 12:16:54 PM PDT 24
Finished Jul 01 12:55:10 PM PDT 24
Peak memory 395320 kb
Host smart-4ada57ed-570a-46ed-93ac-cb21bbe13fb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=359803026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.359803026 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.257809339
Short name T206
Test name
Test status
Simulation time 599556946812 ps
CPU time 2283.08 seconds
Started Jul 01 12:16:53 PM PDT 24
Finished Jul 01 12:54:57 PM PDT 24
Peak memory 379228 kb
Host smart-2ac0fdaf-58ba-48dd-b80d-93bdc3ddae64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=257809339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.257809339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.3327426136
Short name T819
Test name
Test status
Simulation time 300686291543 ps
CPU time 1739.6 seconds
Started Jul 01 12:17:01 PM PDT 24
Finished Jul 01 12:46:01 PM PDT 24
Peak memory 335740 kb
Host smart-150b1c99-67e3-4584-bc54-05cd14190d1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3327426136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.3327426136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.3472582950
Short name T293
Test name
Test status
Simulation time 10886232126 ps
CPU time 1194.69 seconds
Started Jul 01 12:16:59 PM PDT 24
Finished Jul 01 12:36:54 PM PDT 24
Peak memory 300376 kb
Host smart-3d0e0fb1-cfbd-4455-bc2b-f7278f1d71fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3472582950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.3472582950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.636662004
Short name T368
Test name
Test status
Simulation time 126328322815 ps
CPU time 5183.29 seconds
Started Jul 01 12:16:58 PM PDT 24
Finished Jul 01 01:43:22 PM PDT 24
Peak memory 647964 kb
Host smart-d0836638-d4e0-4529-a0f1-23f45aa0c40d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=636662004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.636662004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.4163068270
Short name T328
Test name
Test status
Simulation time 111978072616 ps
CPU time 4568.97 seconds
Started Jul 01 12:16:57 PM PDT 24
Finished Jul 01 01:33:07 PM PDT 24
Peak memory 552916 kb
Host smart-966968d3-c4ad-46ff-81a9-f3c1be8ac28f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4163068270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.4163068270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.2945748232
Short name T462
Test name
Test status
Simulation time 91817493 ps
CPU time 0.81 seconds
Started Jul 01 12:17:39 PM PDT 24
Finished Jul 01 12:17:41 PM PDT 24
Peak memory 217916 kb
Host smart-47576bb1-a456-4c41-ae12-8bdfda6d9c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945748232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2945748232 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.3811029061
Short name T585
Test name
Test status
Simulation time 10315404086 ps
CPU time 169.95 seconds
Started Jul 01 12:17:35 PM PDT 24
Finished Jul 01 12:20:25 PM PDT 24
Peak memory 240452 kb
Host smart-03e81102-de1f-43ee-ae1c-217e27349966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811029061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3811029061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.707158173
Short name T162
Test name
Test status
Simulation time 4207380502 ps
CPU time 122.97 seconds
Started Jul 01 12:17:23 PM PDT 24
Finished Jul 01 12:19:26 PM PDT 24
Peak memory 226848 kb
Host smart-15e4a1a8-73f7-4064-87a8-4c50d443e3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707158173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.707158173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.1542279096
Short name T407
Test name
Test status
Simulation time 68372504959 ps
CPU time 294.22 seconds
Started Jul 01 12:17:33 PM PDT 24
Finished Jul 01 12:22:28 PM PDT 24
Peak memory 246132 kb
Host smart-4ff38557-46c3-4056-96dc-f705e08bcfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542279096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1542279096 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.360090446
Short name T683
Test name
Test status
Simulation time 2323304442 ps
CPU time 163.35 seconds
Started Jul 01 12:17:33 PM PDT 24
Finished Jul 01 12:20:17 PM PDT 24
Peak memory 250880 kb
Host smart-27bb1897-a6e0-4430-8d04-5a632688eef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360090446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.360090446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.2580634869
Short name T1056
Test name
Test status
Simulation time 165339486 ps
CPU time 2.85 seconds
Started Jul 01 12:17:38 PM PDT 24
Finished Jul 01 12:17:41 PM PDT 24
Peak memory 218112 kb
Host smart-5780b1d3-cb5d-4fa9-9782-e463f17b07e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580634869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2580634869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.2654459221
Short name T1018
Test name
Test status
Simulation time 163101162 ps
CPU time 1.42 seconds
Started Jul 01 12:17:40 PM PDT 24
Finished Jul 01 12:17:42 PM PDT 24
Peak memory 218156 kb
Host smart-4f6b0b29-3530-4a85-8bed-97666a1a308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654459221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2654459221 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.3149594713
Short name T929
Test name
Test status
Simulation time 72801148480 ps
CPU time 2102.05 seconds
Started Jul 01 12:17:19 PM PDT 24
Finished Jul 01 12:52:22 PM PDT 24
Peak memory 388540 kb
Host smart-a0ca4f63-014b-435a-be51-61638bd8c58a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149594713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.3149594713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.738704108
Short name T786
Test name
Test status
Simulation time 9465091675 ps
CPU time 66.99 seconds
Started Jul 01 12:17:18 PM PDT 24
Finished Jul 01 12:18:26 PM PDT 24
Peak memory 229416 kb
Host smart-18ba8dec-80a4-4601-bb8f-c06d02801e4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738704108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.738704108 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.1732306882
Short name T1039
Test name
Test status
Simulation time 67957631 ps
CPU time 1.88 seconds
Started Jul 01 12:17:19 PM PDT 24
Finished Jul 01 12:17:21 PM PDT 24
Peak memory 221008 kb
Host smart-4a26e80e-35d0-4887-ab07-8e5e9db84eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732306882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1732306882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.647571673
Short name T126
Test name
Test status
Simulation time 29794292800 ps
CPU time 191.14 seconds
Started Jul 01 12:17:38 PM PDT 24
Finished Jul 01 12:20:50 PM PDT 24
Peak memory 251228 kb
Host smart-77f3c263-e4cf-48c8-bd09-6c016b9a66ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=647571673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.647571673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.3476560183
Short name T35
Test name
Test status
Simulation time 225173274 ps
CPU time 6.37 seconds
Started Jul 01 12:17:27 PM PDT 24
Finished Jul 01 12:17:34 PM PDT 24
Peak memory 218124 kb
Host smart-7b45f2f7-a16e-41d3-b288-65adf63ad3b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476560183 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.3476560183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.2074184079
Short name T729
Test name
Test status
Simulation time 253537889 ps
CPU time 6.62 seconds
Started Jul 01 12:17:29 PM PDT 24
Finished Jul 01 12:17:36 PM PDT 24
Peak memory 219144 kb
Host smart-27cfafa0-b936-448e-8aca-61366ee4c2ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074184079 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.2074184079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.688388661
Short name T804
Test name
Test status
Simulation time 102553888724 ps
CPU time 2351.99 seconds
Started Jul 01 12:17:21 PM PDT 24
Finished Jul 01 12:56:34 PM PDT 24
Peak memory 398644 kb
Host smart-7f82b55e-caac-41d7-a305-448b7c61150f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=688388661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.688388661 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.10605169
Short name T325
Test name
Test status
Simulation time 321255211055 ps
CPU time 2129.32 seconds
Started Jul 01 12:17:22 PM PDT 24
Finished Jul 01 12:52:53 PM PDT 24
Peak memory 382280 kb
Host smart-d19fdb56-e885-40f8-aef7-8ba8d932c293
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=10605169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.10605169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.4273433483
Short name T386
Test name
Test status
Simulation time 70455296662 ps
CPU time 1885.78 seconds
Started Jul 01 12:17:22 PM PDT 24
Finished Jul 01 12:48:49 PM PDT 24
Peak memory 337216 kb
Host smart-9c2bd92f-98e5-4a08-836d-af51c85b414d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4273433483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.4273433483 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.1932450767
Short name T690
Test name
Test status
Simulation time 100617334411 ps
CPU time 1278.79 seconds
Started Jul 01 12:17:23 PM PDT 24
Finished Jul 01 12:38:42 PM PDT 24
Peak memory 300440 kb
Host smart-7513c182-c403-4916-bee2-6951f1c77bb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1932450767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.1932450767 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.3850302854
Short name T919
Test name
Test status
Simulation time 536928363042 ps
CPU time 6596.42 seconds
Started Jul 01 12:17:29 PM PDT 24
Finished Jul 01 02:07:27 PM PDT 24
Peak memory 666696 kb
Host smart-9ef6f90a-393b-4770-9f9c-325263ad131a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3850302854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.3850302854 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.2776716539
Short name T196
Test name
Test status
Simulation time 722243790028 ps
CPU time 5120.38 seconds
Started Jul 01 12:17:28 PM PDT 24
Finished Jul 01 01:42:50 PM PDT 24
Peak memory 578404 kb
Host smart-c22f4d6e-2707-42ba-b218-1b5cbc8315d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2776716539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.2776716539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.652875142
Short name T308
Test name
Test status
Simulation time 71385042 ps
CPU time 0.86 seconds
Started Jul 01 12:18:02 PM PDT 24
Finished Jul 01 12:18:03 PM PDT 24
Peak memory 217880 kb
Host smart-7cf24bb3-928d-4032-afa2-e05a234c7321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652875142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.652875142 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.1678368811
Short name T508
Test name
Test status
Simulation time 58458534637 ps
CPU time 379.93 seconds
Started Jul 01 12:17:57 PM PDT 24
Finished Jul 01 12:24:18 PM PDT 24
Peak memory 248764 kb
Host smart-6ee080b2-ceff-403a-9ada-625fadc36032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678368811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1678368811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.1027066011
Short name T940
Test name
Test status
Simulation time 10456594375 ps
CPU time 1168.36 seconds
Started Jul 01 12:17:46 PM PDT 24
Finished Jul 01 12:37:15 PM PDT 24
Peak memory 242688 kb
Host smart-629cdd0b-7eb0-4899-b4cb-a3d961ee3595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027066011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1027066011 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.1442563270
Short name T357
Test name
Test status
Simulation time 4674303388 ps
CPU time 59.29 seconds
Started Jul 01 12:17:54 PM PDT 24
Finished Jul 01 12:18:54 PM PDT 24
Peak memory 227808 kb
Host smart-554a6efc-d161-4421-ab40-854c2acb8022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442563270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1442563270 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.1078351967
Short name T882
Test name
Test status
Simulation time 12518762417 ps
CPU time 508.71 seconds
Started Jul 01 12:17:56 PM PDT 24
Finished Jul 01 12:26:25 PM PDT 24
Peak memory 260016 kb
Host smart-cf1734f7-99d3-46c5-be2b-82f896f6d608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078351967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1078351967 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.79590048
Short name T608
Test name
Test status
Simulation time 3394798817 ps
CPU time 12.74 seconds
Started Jul 01 12:17:57 PM PDT 24
Finished Jul 01 12:18:10 PM PDT 24
Peak memory 218436 kb
Host smart-2a2a1211-b95b-4edb-b02e-249de3a40303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79590048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.79590048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.1698218600
Short name T71
Test name
Test status
Simulation time 2137445551 ps
CPU time 25.01 seconds
Started Jul 01 12:17:55 PM PDT 24
Finished Jul 01 12:18:21 PM PDT 24
Peak memory 235028 kb
Host smart-a7284b0c-345a-442d-9da8-50359c5d3311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698218600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.1698218600 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.437016447
Short name T840
Test name
Test status
Simulation time 411856850583 ps
CPU time 3315.33 seconds
Started Jul 01 12:17:44 PM PDT 24
Finished Jul 01 01:13:01 PM PDT 24
Peak memory 486712 kb
Host smart-c1550362-45c9-49e9-9310-8614b349be91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437016447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_an
d_output.437016447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.832660029
Short name T261
Test name
Test status
Simulation time 26027995097 ps
CPU time 432.17 seconds
Started Jul 01 12:17:44 PM PDT 24
Finished Jul 01 12:24:57 PM PDT 24
Peak memory 252164 kb
Host smart-383ed2e4-e8f1-4336-82e1-0aa5e276c4a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832660029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.832660029 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.3744119470
Short name T1022
Test name
Test status
Simulation time 1969765092 ps
CPU time 71.14 seconds
Started Jul 01 12:17:44 PM PDT 24
Finished Jul 01 12:18:57 PM PDT 24
Peak memory 221768 kb
Host smart-86df0dbb-008a-4606-82f2-e901f0fc28f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744119470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.3744119470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.1379040690
Short name T430
Test name
Test status
Simulation time 19159416326 ps
CPU time 1395.73 seconds
Started Jul 01 12:18:00 PM PDT 24
Finished Jul 01 12:41:17 PM PDT 24
Peak memory 357404 kb
Host smart-7ad8d8eb-8934-48d2-a5ab-d526a40ecfec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1379040690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1379040690 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.4187446131
Short name T234
Test name
Test status
Simulation time 411017450 ps
CPU time 6.1 seconds
Started Jul 01 12:17:56 PM PDT 24
Finished Jul 01 12:18:03 PM PDT 24
Peak memory 219116 kb
Host smart-c50d1553-d0d0-48d7-b2dc-010859d70bd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187446131 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.4187446131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.3248397829
Short name T670
Test name
Test status
Simulation time 2245925382 ps
CPU time 6.63 seconds
Started Jul 01 12:17:56 PM PDT 24
Finished Jul 01 12:18:03 PM PDT 24
Peak memory 218152 kb
Host smart-bb7ccfae-4b64-444a-a964-1cde79348a89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248397829 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.3248397829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.695684360
Short name T230
Test name
Test status
Simulation time 339815102212 ps
CPU time 2192.58 seconds
Started Jul 01 12:17:50 PM PDT 24
Finished Jul 01 12:54:23 PM PDT 24
Peak memory 399304 kb
Host smart-2b618435-582f-43b6-bb83-44cec5ab0fb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=695684360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.695684360 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.520587593
Short name T490
Test name
Test status
Simulation time 91301414061 ps
CPU time 2323.63 seconds
Started Jul 01 12:17:51 PM PDT 24
Finished Jul 01 12:56:36 PM PDT 24
Peak memory 380708 kb
Host smart-68c39991-5a75-4650-8f6e-988681cf8146
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=520587593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.520587593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.2554065647
Short name T18
Test name
Test status
Simulation time 73346704841 ps
CPU time 1767.12 seconds
Started Jul 01 12:17:51 PM PDT 24
Finished Jul 01 12:47:19 PM PDT 24
Peak memory 338128 kb
Host smart-b94f9674-5977-4436-b068-b008297bd974
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2554065647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.2554065647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.257135205
Short name T838
Test name
Test status
Simulation time 150859859223 ps
CPU time 1231.24 seconds
Started Jul 01 12:17:51 PM PDT 24
Finished Jul 01 12:38:23 PM PDT 24
Peak memory 300192 kb
Host smart-5d465ed1-2f8d-4a05-aade-40e002c6a72d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=257135205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.257135205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.263157380
Short name T520
Test name
Test status
Simulation time 358057066492 ps
CPU time 5909.58 seconds
Started Jul 01 12:17:52 PM PDT 24
Finished Jul 01 01:56:23 PM PDT 24
Peak memory 649792 kb
Host smart-2b5a2210-afc9-49bf-8c2d-73e6c43fa431
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=263157380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.263157380 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.3341068334
Short name T576
Test name
Test status
Simulation time 439593281737 ps
CPU time 4164.81 seconds
Started Jul 01 12:17:52 PM PDT 24
Finished Jul 01 01:27:18 PM PDT 24
Peak memory 566456 kb
Host smart-8d31d59d-45ae-444d-bbd6-42c332d937fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3341068334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.3341068334 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.1768178589
Short name T652
Test name
Test status
Simulation time 15707967 ps
CPU time 0.82 seconds
Started Jul 01 12:18:38 PM PDT 24
Finished Jul 01 12:18:40 PM PDT 24
Peak memory 217944 kb
Host smart-578897be-fb06-4563-a095-d46cde7bd1f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768178589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1768178589 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.614273353
Short name T1021
Test name
Test status
Simulation time 3265869512 ps
CPU time 90.29 seconds
Started Jul 01 12:18:14 PM PDT 24
Finished Jul 01 12:19:46 PM PDT 24
Peak memory 233692 kb
Host smart-08d86898-9696-4164-b27b-d4acebe75128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614273353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.614273353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.3755735044
Short name T971
Test name
Test status
Simulation time 148865049963 ps
CPU time 769.88 seconds
Started Jul 01 12:18:05 PM PDT 24
Finished Jul 01 12:30:55 PM PDT 24
Peak memory 234484 kb
Host smart-72b7acca-2b28-4b67-9b5d-d40afb9b36ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755735044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3755735044 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.2256571311
Short name T16
Test name
Test status
Simulation time 178848671890 ps
CPU time 409.31 seconds
Started Jul 01 12:18:21 PM PDT 24
Finished Jul 01 12:25:11 PM PDT 24
Peak memory 252524 kb
Host smart-9115f2fe-3893-486e-89d2-a2a832bbf837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256571311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2256571311 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.1666551627
Short name T449
Test name
Test status
Simulation time 5255385680 ps
CPU time 101.63 seconds
Started Jul 01 12:18:25 PM PDT 24
Finished Jul 01 12:20:07 PM PDT 24
Peak memory 242656 kb
Host smart-c9106301-d6f9-4890-8b76-ae695df2182a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666551627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1666551627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.396366297
Short name T38
Test name
Test status
Simulation time 3400217540 ps
CPU time 7.93 seconds
Started Jul 01 12:18:27 PM PDT 24
Finished Jul 01 12:18:35 PM PDT 24
Peak memory 218176 kb
Host smart-5974ede1-edbc-4707-8384-a1ce7c3a2506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396366297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.396366297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.3865450377
Short name T475
Test name
Test status
Simulation time 129795247 ps
CPU time 1.33 seconds
Started Jul 01 12:18:24 PM PDT 24
Finished Jul 01 12:18:26 PM PDT 24
Peak memory 218280 kb
Host smart-96df8ba0-7a2d-4993-9e03-6eff95455833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865450377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3865450377 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.3205606435
Short name T957
Test name
Test status
Simulation time 15210363128 ps
CPU time 1443.88 seconds
Started Jul 01 12:18:05 PM PDT 24
Finished Jul 01 12:42:10 PM PDT 24
Peak memory 345820 kb
Host smart-c1e2ccf5-88ea-49dd-8649-18bd7210ed28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205606435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.3205606435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.1753269909
Short name T778
Test name
Test status
Simulation time 11933415817 ps
CPU time 243.11 seconds
Started Jul 01 12:18:05 PM PDT 24
Finished Jul 01 12:22:09 PM PDT 24
Peak memory 243892 kb
Host smart-2e089b29-b313-4e73-aa7f-16d12cc0f917
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753269909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1753269909 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.539910625
Short name T194
Test name
Test status
Simulation time 13327350185 ps
CPU time 76.21 seconds
Started Jul 01 12:18:06 PM PDT 24
Finished Jul 01 12:19:23 PM PDT 24
Peak memory 226356 kb
Host smart-3cd1bb2c-a399-4be0-b9d3-211d87446270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539910625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.539910625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.3522967596
Short name T525
Test name
Test status
Simulation time 33583199698 ps
CPU time 912.87 seconds
Started Jul 01 12:18:30 PM PDT 24
Finished Jul 01 12:33:44 PM PDT 24
Peak memory 291328 kb
Host smart-2a5adb96-503f-42e0-ae81-c0d985f73a54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3522967596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3522967596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.275898185
Short name T966
Test name
Test status
Simulation time 407315883 ps
CPU time 5.71 seconds
Started Jul 01 12:18:15 PM PDT 24
Finished Jul 01 12:18:22 PM PDT 24
Peak memory 218184 kb
Host smart-26e82153-9d8b-494d-beda-82a512c8b846
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275898185 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.kmac_test_vectors_kmac.275898185 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.2477778204
Short name T681
Test name
Test status
Simulation time 364208921 ps
CPU time 7.1 seconds
Started Jul 01 12:18:15 PM PDT 24
Finished Jul 01 12:18:23 PM PDT 24
Peak memory 218188 kb
Host smart-5e4b12b2-4d04-4628-8b44-75dc52da5cf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477778204 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.2477778204 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.2899544537
Short name T887
Test name
Test status
Simulation time 195932685042 ps
CPU time 2430.72 seconds
Started Jul 01 12:18:11 PM PDT 24
Finished Jul 01 12:58:42 PM PDT 24
Peak memory 391612 kb
Host smart-77f0e6a0-228c-4bdd-9f56-1279338a43d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2899544537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.2899544537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.215273859
Short name T848
Test name
Test status
Simulation time 20317633967 ps
CPU time 1898.66 seconds
Started Jul 01 12:18:10 PM PDT 24
Finished Jul 01 12:49:49 PM PDT 24
Peak memory 391608 kb
Host smart-37b1d9e0-a805-45a8-9053-fcb6f9475e3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=215273859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.215273859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.1877183897
Short name T972
Test name
Test status
Simulation time 49890893997 ps
CPU time 1757.84 seconds
Started Jul 01 12:18:08 PM PDT 24
Finished Jul 01 12:47:27 PM PDT 24
Peak memory 342844 kb
Host smart-c789a3d1-813c-4063-9c8c-119fd0ee5c73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1877183897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.1877183897 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.3598435049
Short name T429
Test name
Test status
Simulation time 10454906871 ps
CPU time 1150.57 seconds
Started Jul 01 12:18:14 PM PDT 24
Finished Jul 01 12:37:26 PM PDT 24
Peak memory 300348 kb
Host smart-cc74c692-fd25-4861-9e87-0067312f81b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3598435049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.3598435049 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.1162801205
Short name T754
Test name
Test status
Simulation time 248830448213 ps
CPU time 5371.65 seconds
Started Jul 01 12:18:17 PM PDT 24
Finished Jul 01 01:47:50 PM PDT 24
Peak memory 644400 kb
Host smart-7c484134-45e6-43a3-abed-ab048122668d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1162801205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.1162801205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.1839168069
Short name T297
Test name
Test status
Simulation time 913987233999 ps
CPU time 5481.66 seconds
Started Jul 01 12:18:14 PM PDT 24
Finished Jul 01 01:49:38 PM PDT 24
Peak memory 577152 kb
Host smart-f39a02f3-53e7-4d40-955c-5e061ce2d4cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1839168069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.1839168069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.1923954756
Short name T365
Test name
Test status
Simulation time 94845745 ps
CPU time 0.83 seconds
Started Jul 01 12:07:15 PM PDT 24
Finished Jul 01 12:07:17 PM PDT 24
Peak memory 217928 kb
Host smart-88a7dfe7-104b-4c65-9e71-cdebb1e1776e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923954756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1923954756 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.1460754
Short name T692
Test name
Test status
Simulation time 3724019392 ps
CPU time 28.45 seconds
Started Jul 01 12:07:01 PM PDT 24
Finished Jul 01 12:07:30 PM PDT 24
Peak memory 227092 kb
Host smart-2f4a2d99-2cfb-4dcb-9e51-1de2c2356937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.1460754 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.2072510150
Short name T562
Test name
Test status
Simulation time 14996723211 ps
CPU time 265.12 seconds
Started Jul 01 12:07:00 PM PDT 24
Finished Jul 01 12:11:26 PM PDT 24
Peak memory 242508 kb
Host smart-381345fa-4ffc-411d-bb44-8df6eed020e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072510150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2072510150 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.2471474997
Short name T294
Test name
Test status
Simulation time 49902475668 ps
CPU time 1294.15 seconds
Started Jul 01 12:06:46 PM PDT 24
Finished Jul 01 12:28:21 PM PDT 24
Peak memory 242556 kb
Host smart-1a95227e-ab3e-4f88-85fd-49dca2c8bf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471474997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2471474997 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.3522161435
Short name T808
Test name
Test status
Simulation time 2441831500 ps
CPU time 15.87 seconds
Started Jul 01 12:07:10 PM PDT 24
Finished Jul 01 12:07:27 PM PDT 24
Peak memory 231544 kb
Host smart-e3766b44-c660-4fc0-8f59-07ca82b6d5b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3522161435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3522161435 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.4141574218
Short name T65
Test name
Test status
Simulation time 46808781 ps
CPU time 0.88 seconds
Started Jul 01 12:07:10 PM PDT 24
Finished Jul 01 12:07:11 PM PDT 24
Peak memory 217848 kb
Host smart-2e8c3664-9495-4471-9a65-70ade4a040d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4141574218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.4141574218 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.234857816
Short name T634
Test name
Test status
Simulation time 8348387564 ps
CPU time 323.18 seconds
Started Jul 01 12:06:59 PM PDT 24
Finished Jul 01 12:12:22 PM PDT 24
Peak memory 247548 kb
Host smart-79b2b989-a6c6-452d-ae6d-8a45cc637024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234857816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.234857816 +enable_masking=1 +sw_
key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.331162492
Short name T918
Test name
Test status
Simulation time 7275834452 ps
CPU time 301.73 seconds
Started Jul 01 12:07:05 PM PDT 24
Finished Jul 01 12:12:08 PM PDT 24
Peak memory 259080 kb
Host smart-3ac66fe9-c0b2-4b78-81e0-1d1a51ef383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331162492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.331162492 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.1598235220
Short name T628
Test name
Test status
Simulation time 3888778184 ps
CPU time 7.2 seconds
Started Jul 01 12:07:08 PM PDT 24
Finished Jul 01 12:07:16 PM PDT 24
Peak memory 218156 kb
Host smart-cb1b5181-6f63-4746-8c5d-ab89fc3543ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598235220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1598235220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.1689873211
Short name T327
Test name
Test status
Simulation time 1141877632 ps
CPU time 52.47 seconds
Started Jul 01 12:06:46 PM PDT 24
Finished Jul 01 12:07:39 PM PDT 24
Peak memory 226260 kb
Host smart-bef46bec-124e-40e9-ad15-f623cb13c1af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689873211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.1689873211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.749134750
Short name T81
Test name
Test status
Simulation time 2808525550 ps
CPU time 162.22 seconds
Started Jul 01 12:07:06 PM PDT 24
Finished Jul 01 12:09:49 PM PDT 24
Peak memory 242924 kb
Host smart-a812f4a1-a175-41c6-90f9-6b7e9e95fc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749134750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.749134750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sideload.1402893645
Short name T942
Test name
Test status
Simulation time 14523745899 ps
CPU time 514.24 seconds
Started Jul 01 12:06:47 PM PDT 24
Finished Jul 01 12:15:21 PM PDT 24
Peak memory 256464 kb
Host smart-fd1d0d83-09c8-4589-a10d-bb3467d35711
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402893645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1402893645 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.1077671779
Short name T970
Test name
Test status
Simulation time 16439930721 ps
CPU time 57.68 seconds
Started Jul 01 12:06:41 PM PDT 24
Finished Jul 01 12:07:40 PM PDT 24
Peak memory 225524 kb
Host smart-ad43ee0f-43b4-4f75-8032-47cc582e4be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077671779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1077671779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.1245974765
Short name T187
Test name
Test status
Simulation time 42338104216 ps
CPU time 245.28 seconds
Started Jul 01 12:07:14 PM PDT 24
Finished Jul 01 12:11:20 PM PDT 24
Peak memory 269644 kb
Host smart-477e20b9-3aeb-45fe-a8d1-b987e099b434
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1245974765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1245974765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.560467796
Short name T912
Test name
Test status
Simulation time 298182551 ps
CPU time 7.07 seconds
Started Jul 01 12:06:56 PM PDT 24
Finished Jul 01 12:07:03 PM PDT 24
Peak memory 219048 kb
Host smart-7081a634-d348-4497-8a09-66e53b033de1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560467796 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.kmac_test_vectors_kmac.560467796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.200218710
Short name T587
Test name
Test status
Simulation time 1325161690 ps
CPU time 7.35 seconds
Started Jul 01 12:06:56 PM PDT 24
Finished Jul 01 12:07:03 PM PDT 24
Peak memory 218044 kb
Host smart-0eda6344-b30c-46a0-b28d-07c7b5f09339
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200218710 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.kmac_test_vectors_kmac_xof.200218710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.1069523253
Short name T356
Test name
Test status
Simulation time 67678971957 ps
CPU time 2200.25 seconds
Started Jul 01 12:06:46 PM PDT 24
Finished Jul 01 12:43:27 PM PDT 24
Peak memory 393776 kb
Host smart-8b5262e8-1614-4842-9978-52e166319c41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1069523253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1069523253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.335692342
Short name T856
Test name
Test status
Simulation time 882156133373 ps
CPU time 2025.91 seconds
Started Jul 01 12:06:51 PM PDT 24
Finished Jul 01 12:40:37 PM PDT 24
Peak memory 382228 kb
Host smart-ce2af09b-5f6f-4334-8bc8-88ce58176529
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=335692342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.335692342 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.1565338317
Short name T832
Test name
Test status
Simulation time 15878408030 ps
CPU time 1533.39 seconds
Started Jul 01 12:06:50 PM PDT 24
Finished Jul 01 12:32:24 PM PDT 24
Peak memory 335748 kb
Host smart-876e8db2-ede3-4690-9e51-359fc0eae457
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1565338317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.1565338317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.451439298
Short name T1014
Test name
Test status
Simulation time 132974885714 ps
CPU time 1280.19 seconds
Started Jul 01 12:06:51 PM PDT 24
Finished Jul 01 12:28:12 PM PDT 24
Peak memory 299532 kb
Host smart-0ceb0bc6-a9f4-4f21-9bae-df29cc3add14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=451439298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.451439298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.3201615093
Short name T276
Test name
Test status
Simulation time 313591085138 ps
CPU time 6058.72 seconds
Started Jul 01 12:06:50 PM PDT 24
Finished Jul 01 01:47:50 PM PDT 24
Peak memory 655060 kb
Host smart-d77df878-bd06-4feb-b046-d3da6d7cd413
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3201615093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3201615093 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.139259450
Short name T677
Test name
Test status
Simulation time 155540850373 ps
CPU time 4895.75 seconds
Started Jul 01 12:06:56 PM PDT 24
Finished Jul 01 01:28:33 PM PDT 24
Peak memory 561880 kb
Host smart-8b03bbda-18c7-4a68-9f17-4ff6530e24f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=139259450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.139259450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.2636189326
Short name T993
Test name
Test status
Simulation time 32118481 ps
CPU time 0.83 seconds
Started Jul 01 12:19:10 PM PDT 24
Finished Jul 01 12:19:11 PM PDT 24
Peak memory 218016 kb
Host smart-de9686d9-a9d8-4650-b112-0a1d35abff30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636189326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2636189326 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.746767713
Short name T610
Test name
Test status
Simulation time 9726465025 ps
CPU time 225.75 seconds
Started Jul 01 12:18:57 PM PDT 24
Finished Jul 01 12:22:43 PM PDT 24
Peak memory 243604 kb
Host smart-91286f53-4053-4fed-961f-6b07c88ce149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746767713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.746767713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.3657339939
Short name T861
Test name
Test status
Simulation time 8973067850 ps
CPU time 110.18 seconds
Started Jul 01 12:18:43 PM PDT 24
Finished Jul 01 12:20:34 PM PDT 24
Peak memory 226484 kb
Host smart-655975a0-1e17-4870-b4f2-99202e5e5eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657339939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3657339939 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.252823740
Short name T1044
Test name
Test status
Simulation time 12640521458 ps
CPU time 147.44 seconds
Started Jul 01 12:18:56 PM PDT 24
Finished Jul 01 12:21:24 PM PDT 24
Peak memory 242692 kb
Host smart-ca1f507d-f80c-4897-aa65-a956af585424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252823740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.252823740 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.1749616309
Short name T531
Test name
Test status
Simulation time 12148453829 ps
CPU time 136.66 seconds
Started Jul 01 12:18:59 PM PDT 24
Finished Jul 01 12:21:17 PM PDT 24
Peak memory 250784 kb
Host smart-3202cdaf-49cc-438f-b8eb-f9e701e0b33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749616309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1749616309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.2288578714
Short name T1052
Test name
Test status
Simulation time 3455847983 ps
CPU time 11.97 seconds
Started Jul 01 12:19:02 PM PDT 24
Finished Jul 01 12:19:14 PM PDT 24
Peak memory 218176 kb
Host smart-6091f224-851c-4204-8706-4e24f3da2fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288578714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2288578714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.2914528119
Short name T827
Test name
Test status
Simulation time 248238854 ps
CPU time 1.54 seconds
Started Jul 01 12:19:01 PM PDT 24
Finished Jul 01 12:19:03 PM PDT 24
Peak memory 218224 kb
Host smart-2d83fa21-9bef-4d7f-ab5e-cc0993066222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914528119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.2914528119 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.3450192687
Short name T661
Test name
Test status
Simulation time 169051374678 ps
CPU time 1066.51 seconds
Started Jul 01 12:18:37 PM PDT 24
Finished Jul 01 12:36:24 PM PDT 24
Peak memory 289112 kb
Host smart-dc31b038-d1b7-4b89-bfeb-1c91e480ac75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450192687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.3450192687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.3422316064
Short name T402
Test name
Test status
Simulation time 22650851611 ps
CPU time 85.79 seconds
Started Jul 01 12:18:42 PM PDT 24
Finished Jul 01 12:20:08 PM PDT 24
Peak memory 228868 kb
Host smart-ff9550f3-2f77-46ce-8a6d-030c178281f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422316064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3422316064 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.3608854116
Short name T890
Test name
Test status
Simulation time 363077322 ps
CPU time 4.34 seconds
Started Jul 01 12:18:38 PM PDT 24
Finished Jul 01 12:18:43 PM PDT 24
Peak memory 222148 kb
Host smart-843314e6-5d42-4e36-b43f-609f5c5ec0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608854116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.3608854116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.1422434153
Short name T567
Test name
Test status
Simulation time 12821392037 ps
CPU time 420.09 seconds
Started Jul 01 12:19:07 PM PDT 24
Finished Jul 01 12:26:07 PM PDT 24
Peak memory 292244 kb
Host smart-96b910e4-d333-4a43-a0a8-1a16ee632b24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1422434153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1422434153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.1147027450
Short name T208
Test name
Test status
Simulation time 1732478709 ps
CPU time 5.84 seconds
Started Jul 01 12:19:00 PM PDT 24
Finished Jul 01 12:19:07 PM PDT 24
Peak memory 218088 kb
Host smart-3b6f243b-b930-4f1c-b8a6-3ae714f96cdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147027450 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.1147027450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.3740437250
Short name T573
Test name
Test status
Simulation time 169329224 ps
CPU time 5.71 seconds
Started Jul 01 12:18:55 PM PDT 24
Finished Jul 01 12:19:02 PM PDT 24
Peak memory 218080 kb
Host smart-671df47b-95c4-4e81-b8ce-18057df68a02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740437250 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.3740437250 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.1598543980
Short name T760
Test name
Test status
Simulation time 68503182018 ps
CPU time 2302.82 seconds
Started Jul 01 12:18:48 PM PDT 24
Finished Jul 01 12:57:12 PM PDT 24
Peak memory 396080 kb
Host smart-fd7b67ee-d08f-4820-936d-9a7a8ca0d765
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1598543980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.1598543980 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.3299407505
Short name T383
Test name
Test status
Simulation time 80897701264 ps
CPU time 2124.28 seconds
Started Jul 01 12:18:50 PM PDT 24
Finished Jul 01 12:54:15 PM PDT 24
Peak memory 387036 kb
Host smart-c689de11-7f28-4bff-ad17-4d3a10b0adb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3299407505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.3299407505 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.1924052856
Short name T907
Test name
Test status
Simulation time 143880515328 ps
CPU time 1797.32 seconds
Started Jul 01 12:18:59 PM PDT 24
Finished Jul 01 12:48:58 PM PDT 24
Peak memory 345320 kb
Host smart-670db3ff-e6ba-4097-986d-e641f02f84af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1924052856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.1924052856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.2569191058
Short name T536
Test name
Test status
Simulation time 50897204493 ps
CPU time 1365.92 seconds
Started Jul 01 12:18:59 PM PDT 24
Finished Jul 01 12:41:46 PM PDT 24
Peak memory 302644 kb
Host smart-9ee6881f-b299-4042-9372-bd66377a16e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2569191058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.2569191058 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.568992688
Short name T1002
Test name
Test status
Simulation time 746894010806 ps
CPU time 5731.74 seconds
Started Jul 01 12:18:59 PM PDT 24
Finished Jul 01 01:54:33 PM PDT 24
Peak memory 665472 kb
Host smart-4e5f8b27-c8e9-474e-bc29-3e443e7f2d7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=568992688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.568992688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.1584976949
Short name T371
Test name
Test status
Simulation time 303391111588 ps
CPU time 5058.5 seconds
Started Jul 01 12:18:52 PM PDT 24
Finished Jul 01 01:43:12 PM PDT 24
Peak memory 554616 kb
Host smart-8c699429-bc21-4c23-a603-e87fae61bc69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1584976949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.1584976949 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.870001638
Short name T876
Test name
Test status
Simulation time 24386684 ps
CPU time 0.85 seconds
Started Jul 01 12:19:32 PM PDT 24
Finished Jul 01 12:19:33 PM PDT 24
Peak memory 217932 kb
Host smart-602428db-1d52-4920-9d2e-4ccbe7631fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870001638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.870001638 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.818588444
Short name T664
Test name
Test status
Simulation time 18522467405 ps
CPU time 215.23 seconds
Started Jul 01 12:19:27 PM PDT 24
Finished Jul 01 12:23:03 PM PDT 24
Peak memory 240852 kb
Host smart-d8b9c63e-d6ac-44d7-8d21-8dd48bf05a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818588444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.818588444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.2953859781
Short name T939
Test name
Test status
Simulation time 93597023046 ps
CPU time 904.3 seconds
Started Jul 01 12:19:16 PM PDT 24
Finished Jul 01 12:34:21 PM PDT 24
Peak memory 236212 kb
Host smart-fd14deaf-0c47-4d61-aeb3-8c3ba5ca9d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953859781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2953859781 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.3865336391
Short name T186
Test name
Test status
Simulation time 14204097482 ps
CPU time 336.81 seconds
Started Jul 01 12:19:25 PM PDT 24
Finished Jul 01 12:25:02 PM PDT 24
Peak memory 249024 kb
Host smart-b68ee42a-95a3-44ad-9a52-054ee766cbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865336391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3865336391 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.2833262128
Short name T8
Test name
Test status
Simulation time 3191658117 ps
CPU time 61.83 seconds
Started Jul 01 12:19:32 PM PDT 24
Finished Jul 01 12:20:35 PM PDT 24
Peak memory 242680 kb
Host smart-cb95818f-9fff-4808-8a7b-edc139b3d0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833262128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2833262128 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.2159621915
Short name T491
Test name
Test status
Simulation time 896954436 ps
CPU time 4.64 seconds
Started Jul 01 12:19:32 PM PDT 24
Finished Jul 01 12:19:37 PM PDT 24
Peak memory 218016 kb
Host smart-b6ea17a2-987a-4938-9822-cefe95f1b5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159621915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2159621915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.3261661345
Short name T676
Test name
Test status
Simulation time 64310847 ps
CPU time 1.35 seconds
Started Jul 01 12:19:31 PM PDT 24
Finished Jul 01 12:19:33 PM PDT 24
Peak memory 218180 kb
Host smart-11b6309a-2d02-4608-a699-79d5c5b8a976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261661345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.3261661345 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.1676651626
Short name T248
Test name
Test status
Simulation time 137088397723 ps
CPU time 3500.21 seconds
Started Jul 01 12:19:12 PM PDT 24
Finished Jul 01 01:17:33 PM PDT 24
Peak memory 488392 kb
Host smart-fbd81ddc-5f73-416b-98be-2b6cf749cc23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676651626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.1676651626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.2125106313
Short name T415
Test name
Test status
Simulation time 778015708 ps
CPU time 17.53 seconds
Started Jul 01 12:19:10 PM PDT 24
Finished Jul 01 12:19:28 PM PDT 24
Peak memory 224512 kb
Host smart-8dab5c16-073e-4619-a577-c9217d8631e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125106313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2125106313 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.2603833036
Short name T977
Test name
Test status
Simulation time 2567370923 ps
CPU time 10.08 seconds
Started Jul 01 12:19:11 PM PDT 24
Finished Jul 01 12:19:22 PM PDT 24
Peak memory 224320 kb
Host smart-e2de61fd-898a-4b9e-a502-687468d9183a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603833036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2603833036 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.285033902
Short name T979
Test name
Test status
Simulation time 44624156878 ps
CPU time 713.78 seconds
Started Jul 01 12:19:31 PM PDT 24
Finished Jul 01 12:31:26 PM PDT 24
Peak memory 303568 kb
Host smart-fc7c8292-89d7-4187-804d-302a5264bc45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=285033902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.285033902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.1504241183
Short name T290
Test name
Test status
Simulation time 483300924 ps
CPU time 6.39 seconds
Started Jul 01 12:19:26 PM PDT 24
Finished Jul 01 12:19:33 PM PDT 24
Peak memory 219036 kb
Host smart-e11a1b4a-2fd7-4304-9174-b34b5dc049a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504241183 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.1504241183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.2087168395
Short name T811
Test name
Test status
Simulation time 1615810363 ps
CPU time 5.59 seconds
Started Jul 01 12:19:25 PM PDT 24
Finished Jul 01 12:19:31 PM PDT 24
Peak memory 218164 kb
Host smart-0c8166fe-3239-4409-a70b-5e79c94e4f64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087168395 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.2087168395 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.3622229752
Short name T381
Test name
Test status
Simulation time 21834234674 ps
CPU time 1979.5 seconds
Started Jul 01 12:19:18 PM PDT 24
Finished Jul 01 12:52:18 PM PDT 24
Peak memory 394160 kb
Host smart-2b69844e-9543-4ef2-9354-4667ead91f45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3622229752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.3622229752 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.2231118082
Short name T199
Test name
Test status
Simulation time 60593173006 ps
CPU time 2075.55 seconds
Started Jul 01 12:19:19 PM PDT 24
Finished Jul 01 12:53:55 PM PDT 24
Peak memory 378928 kb
Host smart-0eb9567a-8823-4974-a892-df78e1be2d91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2231118082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.2231118082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.4030032477
Short name T638
Test name
Test status
Simulation time 217885343372 ps
CPU time 1801.61 seconds
Started Jul 01 12:19:21 PM PDT 24
Finished Jul 01 12:49:23 PM PDT 24
Peak memory 338496 kb
Host smart-4f63d7b8-d08c-4a02-a963-904383b6824a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4030032477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.4030032477 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.4191075517
Short name T41
Test name
Test status
Simulation time 49749036711 ps
CPU time 1232.87 seconds
Started Jul 01 12:19:20 PM PDT 24
Finished Jul 01 12:39:54 PM PDT 24
Peak memory 300784 kb
Host smart-9b9da7ff-e4eb-4492-9ee0-50f92b6cf706
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4191075517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.4191075517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.3847071477
Short name T666
Test name
Test status
Simulation time 421303475933 ps
CPU time 5911.82 seconds
Started Jul 01 12:19:21 PM PDT 24
Finished Jul 01 01:57:54 PM PDT 24
Peak memory 643236 kb
Host smart-4f3f883d-cb5a-42ab-bee9-5d88f8fe0a6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3847071477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.3847071477 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.4046485268
Short name T629
Test name
Test status
Simulation time 77638683635 ps
CPU time 4461.59 seconds
Started Jul 01 12:19:27 PM PDT 24
Finished Jul 01 01:33:49 PM PDT 24
Peak memory 561264 kb
Host smart-b2628ae4-cdd2-4aaa-94d3-14bbfdd6190f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4046485268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.4046485268 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.2198070009
Short name T895
Test name
Test status
Simulation time 15671471 ps
CPU time 0.84 seconds
Started Jul 01 12:20:06 PM PDT 24
Finished Jul 01 12:20:08 PM PDT 24
Peak memory 217924 kb
Host smart-5d0dc92c-26e0-48f6-8fa9-86e950a704d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198070009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2198070009 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.2991158943
Short name T1038
Test name
Test status
Simulation time 20778578682 ps
CPU time 182.99 seconds
Started Jul 01 12:19:53 PM PDT 24
Finished Jul 01 12:22:56 PM PDT 24
Peak memory 239968 kb
Host smart-5e34e76e-2943-41ca-8d33-d68374b42e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991158943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2991158943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.4161479166
Short name T1062
Test name
Test status
Simulation time 6673063687 ps
CPU time 167.99 seconds
Started Jul 01 12:19:37 PM PDT 24
Finished Jul 01 12:22:25 PM PDT 24
Peak memory 234600 kb
Host smart-65e73129-2b95-4804-b580-1c7d83100179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161479166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.4161479166 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.1736784100
Short name T62
Test name
Test status
Simulation time 2903313561 ps
CPU time 101.25 seconds
Started Jul 01 12:19:59 PM PDT 24
Finished Jul 01 12:21:41 PM PDT 24
Peak memory 232316 kb
Host smart-c30affdc-fed6-4797-8bcc-4a7b7bac23cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736784100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1736784100 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.1824263392
Short name T913
Test name
Test status
Simulation time 5336337779 ps
CPU time 173.69 seconds
Started Jul 01 12:20:03 PM PDT 24
Finished Jul 01 12:22:57 PM PDT 24
Peak memory 250844 kb
Host smart-dcee2b03-ea66-4934-aba3-084b9a67cdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824263392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1824263392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.2935778847
Short name T447
Test name
Test status
Simulation time 10879302642 ps
CPU time 11.94 seconds
Started Jul 01 12:20:01 PM PDT 24
Finished Jul 01 12:20:13 PM PDT 24
Peak memory 218260 kb
Host smart-4cb64876-d01e-4f7a-859e-c7a3d88e7db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935778847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2935778847 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.1829639758
Short name T26
Test name
Test status
Simulation time 75715602 ps
CPU time 1.3 seconds
Started Jul 01 12:20:03 PM PDT 24
Finished Jul 01 12:20:05 PM PDT 24
Peak memory 218224 kb
Host smart-928220c5-4f69-4ee0-b610-1a107f8c4bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829639758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.1829639758 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.2987296668
Short name T303
Test name
Test status
Simulation time 49256722147 ps
CPU time 1114.37 seconds
Started Jul 01 12:19:36 PM PDT 24
Finished Jul 01 12:38:11 PM PDT 24
Peak memory 315264 kb
Host smart-f22bfb20-e848-4d54-958f-632ea40e070c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987296668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.2987296668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.1993155997
Short name T470
Test name
Test status
Simulation time 13573275566 ps
CPU time 428.63 seconds
Started Jul 01 12:19:36 PM PDT 24
Finished Jul 01 12:26:46 PM PDT 24
Peak memory 253472 kb
Host smart-f0e587a7-42eb-4b0c-a899-6e3638c18f91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993155997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1993155997 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.1183110702
Short name T1032
Test name
Test status
Simulation time 3689916502 ps
CPU time 85.5 seconds
Started Jul 01 12:19:38 PM PDT 24
Finished Jul 01 12:21:04 PM PDT 24
Peak memory 223124 kb
Host smart-d1d93060-df39-41fa-8a94-06b1f67391cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183110702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1183110702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.3684845452
Short name T480
Test name
Test status
Simulation time 167873991263 ps
CPU time 1039.16 seconds
Started Jul 01 12:20:06 PM PDT 24
Finished Jul 01 12:37:26 PM PDT 24
Peak memory 340792 kb
Host smart-59951583-13e3-458e-b1d0-5376517f8e69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3684845452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3684845452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.2737204142
Short name T981
Test name
Test status
Simulation time 106573391 ps
CPU time 5.86 seconds
Started Jul 01 12:19:55 PM PDT 24
Finished Jul 01 12:20:02 PM PDT 24
Peak memory 218180 kb
Host smart-55696e24-0460-41f3-84a3-79d4f1d94f44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737204142 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.2737204142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.1875759784
Short name T339
Test name
Test status
Simulation time 214815634 ps
CPU time 6.05 seconds
Started Jul 01 12:19:52 PM PDT 24
Finished Jul 01 12:19:59 PM PDT 24
Peak memory 218200 kb
Host smart-2aec6256-debf-4a66-8c12-1c0dd7c9dc97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875759784 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.1875759784 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.405473179
Short name T272
Test name
Test status
Simulation time 206921482866 ps
CPU time 2340.2 seconds
Started Jul 01 12:19:42 PM PDT 24
Finished Jul 01 12:58:43 PM PDT 24
Peak memory 399348 kb
Host smart-b29b8b4a-e8a2-4ec9-850f-00e3f078b7ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=405473179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.405473179 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.299120772
Short name T421
Test name
Test status
Simulation time 135343270795 ps
CPU time 2152.14 seconds
Started Jul 01 12:19:42 PM PDT 24
Finished Jul 01 12:55:35 PM PDT 24
Peak memory 378560 kb
Host smart-19b11fab-d2ed-4888-9afa-7e68feaecf73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=299120772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.299120772 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.2018458005
Short name T337
Test name
Test status
Simulation time 73740600242 ps
CPU time 1751.78 seconds
Started Jul 01 12:19:47 PM PDT 24
Finished Jul 01 12:48:59 PM PDT 24
Peak memory 342488 kb
Host smart-14f82ff6-8d3e-4b6c-90d5-0553e44b5f55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2018458005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.2018458005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.3201804992
Short name T763
Test name
Test status
Simulation time 10431831905 ps
CPU time 1139.05 seconds
Started Jul 01 12:19:49 PM PDT 24
Finished Jul 01 12:38:49 PM PDT 24
Peak memory 298700 kb
Host smart-f0c9c08e-6d05-4056-a769-5c7666214fea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3201804992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.3201804992 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.3202967565
Short name T1047
Test name
Test status
Simulation time 132320095202 ps
CPU time 5109.11 seconds
Started Jul 01 12:19:51 PM PDT 24
Finished Jul 01 01:45:01 PM PDT 24
Peak memory 650940 kb
Host smart-d8b88d86-0bdb-4844-b676-89aad0c51060
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3202967565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.3202967565 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.2724217562
Short name T236
Test name
Test status
Simulation time 218949312084 ps
CPU time 5175.6 seconds
Started Jul 01 12:19:54 PM PDT 24
Finished Jul 01 01:46:11 PM PDT 24
Peak memory 571464 kb
Host smart-85dfa06e-74a8-4468-a46d-c0aabbaa8082
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2724217562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.2724217562 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.852995382
Short name T292
Test name
Test status
Simulation time 102116845 ps
CPU time 0.8 seconds
Started Jul 01 12:20:24 PM PDT 24
Finished Jul 01 12:20:25 PM PDT 24
Peak memory 217896 kb
Host smart-25becc23-d16e-4559-8fe1-9a78090c8c14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852995382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.852995382 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.380034980
Short name T183
Test name
Test status
Simulation time 18893269317 ps
CPU time 259.91 seconds
Started Jul 01 12:20:13 PM PDT 24
Finished Jul 01 12:24:33 PM PDT 24
Peak memory 247368 kb
Host smart-b0fd6e17-89ee-4710-926b-1f486a705652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380034980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.380034980 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.2648754174
Short name T40
Test name
Test status
Simulation time 1623649253 ps
CPU time 180.04 seconds
Started Jul 01 12:20:08 PM PDT 24
Finished Jul 01 12:23:08 PM PDT 24
Peak memory 226248 kb
Host smart-7b09a77b-b030-4015-ae1a-3dddb3611f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648754174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.2648754174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.362860507
Short name T414
Test name
Test status
Simulation time 3282651587 ps
CPU time 66.88 seconds
Started Jul 01 12:20:18 PM PDT 24
Finished Jul 01 12:21:25 PM PDT 24
Peak memory 229464 kb
Host smart-a66922b2-8f9b-470e-8184-bf768a33af5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362860507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.362860507 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.3451892787
Short name T978
Test name
Test status
Simulation time 6194840619 ps
CPU time 522.38 seconds
Started Jul 01 12:20:18 PM PDT 24
Finished Jul 01 12:29:01 PM PDT 24
Peak memory 267256 kb
Host smart-f7f36819-4c5a-49c7-b437-c8ea2447fd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451892787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3451892787 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.3826609615
Short name T112
Test name
Test status
Simulation time 992021353 ps
CPU time 4.14 seconds
Started Jul 01 12:20:23 PM PDT 24
Finished Jul 01 12:20:27 PM PDT 24
Peak memory 218140 kb
Host smart-34e655cc-8fc9-45fc-8ddb-12c72163cafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826609615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3826609615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.117468068
Short name T767
Test name
Test status
Simulation time 68485639 ps
CPU time 1.19 seconds
Started Jul 01 12:20:24 PM PDT 24
Finished Jul 01 12:20:25 PM PDT 24
Peak memory 218212 kb
Host smart-8684bca6-6026-4314-9fe7-26cdd0ff06b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117468068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.117468068 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.532015459
Short name T1067
Test name
Test status
Simulation time 42386984391 ps
CPU time 2464.83 seconds
Started Jul 01 12:20:04 PM PDT 24
Finished Jul 01 01:01:09 PM PDT 24
Peak memory 433604 kb
Host smart-adf9379e-bd82-4e50-9bb5-93b4c37a1474
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532015459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_an
d_output.532015459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.2138104009
Short name T600
Test name
Test status
Simulation time 1924512275 ps
CPU time 143.75 seconds
Started Jul 01 12:20:04 PM PDT 24
Finished Jul 01 12:22:29 PM PDT 24
Peak memory 235992 kb
Host smart-891367e4-6b70-4f98-bb46-1004c7944d25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138104009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2138104009 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.4176002799
Short name T253
Test name
Test status
Simulation time 504370839 ps
CPU time 5.48 seconds
Started Jul 01 12:20:03 PM PDT 24
Finished Jul 01 12:20:09 PM PDT 24
Peak memory 222172 kb
Host smart-b15a3ab9-7cf8-47a4-b51f-51aaac88c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176002799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.4176002799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.2561968868
Short name T709
Test name
Test status
Simulation time 96383093389 ps
CPU time 1676.48 seconds
Started Jul 01 12:20:24 PM PDT 24
Finished Jul 01 12:48:21 PM PDT 24
Peak memory 378680 kb
Host smart-198cd520-2246-4377-bc8f-03b024a53c2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2561968868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2561968868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.4203009989
Short name T330
Test name
Test status
Simulation time 1074202028 ps
CPU time 6.96 seconds
Started Jul 01 12:20:13 PM PDT 24
Finished Jul 01 12:20:21 PM PDT 24
Peak memory 218088 kb
Host smart-7c430392-f9be-4bdd-9293-bc94b4f71a01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203009989 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.4203009989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.3847538640
Short name T635
Test name
Test status
Simulation time 194994583 ps
CPU time 5.88 seconds
Started Jul 01 12:20:13 PM PDT 24
Finished Jul 01 12:20:20 PM PDT 24
Peak memory 218148 kb
Host smart-137563a2-d784-4cff-a3d6-b02b7a0f1b70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847538640 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.3847538640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.4049537962
Short name T205
Test name
Test status
Simulation time 66198920625 ps
CPU time 2069.2 seconds
Started Jul 01 12:20:09 PM PDT 24
Finished Jul 01 12:54:39 PM PDT 24
Peak memory 393460 kb
Host smart-c09102bb-57cf-4ef5-94c3-44dc6e9d83ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4049537962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.4049537962 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.3153853928
Short name T648
Test name
Test status
Simulation time 326520279486 ps
CPU time 2182.22 seconds
Started Jul 01 12:20:08 PM PDT 24
Finished Jul 01 12:56:32 PM PDT 24
Peak memory 380256 kb
Host smart-30c22659-3c60-4cf9-9c29-d7963f01d9c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3153853928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.3153853928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.2615147224
Short name T418
Test name
Test status
Simulation time 30013251249 ps
CPU time 1625.74 seconds
Started Jul 01 12:20:08 PM PDT 24
Finished Jul 01 12:47:14 PM PDT 24
Peak memory 340816 kb
Host smart-a326b001-0d9a-41ef-b9ff-28be6be3a8c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2615147224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.2615147224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.2771017555
Short name T79
Test name
Test status
Simulation time 10831156116 ps
CPU time 1238.06 seconds
Started Jul 01 12:20:07 PM PDT 24
Finished Jul 01 12:40:46 PM PDT 24
Peak memory 298596 kb
Host smart-89ce0827-63de-44fc-8cfa-1d4ec92ca475
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2771017555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.2771017555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.2018601248
Short name T509
Test name
Test status
Simulation time 362058491358 ps
CPU time 5865.77 seconds
Started Jul 01 12:20:07 PM PDT 24
Finished Jul 01 01:57:55 PM PDT 24
Peak memory 656760 kb
Host smart-0c887706-689a-45de-acc7-7aa785c18270
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2018601248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.2018601248 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.4269735617
Short name T785
Test name
Test status
Simulation time 158055489403 ps
CPU time 5156.86 seconds
Started Jul 01 12:20:09 PM PDT 24
Finished Jul 01 01:46:07 PM PDT 24
Peak memory 576108 kb
Host smart-0c92ad96-fc54-4b0c-a495-e4e59ea3a782
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4269735617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.4269735617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.1172308360
Short name T696
Test name
Test status
Simulation time 68703568 ps
CPU time 0.79 seconds
Started Jul 01 12:20:48 PM PDT 24
Finished Jul 01 12:20:50 PM PDT 24
Peak memory 217912 kb
Host smart-0590ba76-347a-4bbc-8fd7-76d8acc6832d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172308360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.1172308360 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.625197793
Short name T148
Test name
Test status
Simulation time 8565816639 ps
CPU time 164.99 seconds
Started Jul 01 12:20:44 PM PDT 24
Finished Jul 01 12:23:30 PM PDT 24
Peak memory 239292 kb
Host smart-017e18f1-79fa-4a4b-bc09-fbe3dea97dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625197793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.625197793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.4284297413
Short name T553
Test name
Test status
Simulation time 3203394810 ps
CPU time 150.16 seconds
Started Jul 01 12:20:36 PM PDT 24
Finished Jul 01 12:23:06 PM PDT 24
Peak memory 235520 kb
Host smart-74d0b22f-319d-48a1-831d-0099cdc54d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284297413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.4284297413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.4059370373
Short name T17
Test name
Test status
Simulation time 13626032454 ps
CPU time 408.75 seconds
Started Jul 01 12:20:43 PM PDT 24
Finished Jul 01 12:27:33 PM PDT 24
Peak memory 253420 kb
Host smart-7f8f190c-e41e-4cb1-a1f5-d36e65c88341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059370373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.4059370373 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_key_error.583798222
Short name T996
Test name
Test status
Simulation time 3038087824 ps
CPU time 4.42 seconds
Started Jul 01 12:20:43 PM PDT 24
Finished Jul 01 12:20:48 PM PDT 24
Peak memory 218172 kb
Host smart-d32d9bac-60a8-4e94-b412-7b70eec26275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583798222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.583798222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.268194463
Short name T47
Test name
Test status
Simulation time 143394153 ps
CPU time 1.4 seconds
Started Jul 01 12:20:48 PM PDT 24
Finished Jul 01 12:20:50 PM PDT 24
Peak memory 218200 kb
Host smart-a4914d7e-951d-40f0-81d2-82c985e2a57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268194463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.268194463 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.131094544
Short name T424
Test name
Test status
Simulation time 158729626633 ps
CPU time 1182.4 seconds
Started Jul 01 12:20:38 PM PDT 24
Finished Jul 01 12:40:22 PM PDT 24
Peak memory 330268 kb
Host smart-5ea908c1-aa4d-4e58-93fe-563ae11330e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131094544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_an
d_output.131094544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.2112575412
Short name T1016
Test name
Test status
Simulation time 18398796866 ps
CPU time 458.59 seconds
Started Jul 01 12:20:36 PM PDT 24
Finished Jul 01 12:28:15 PM PDT 24
Peak memory 251444 kb
Host smart-bb3b0176-0bdf-4d3f-be15-54650caac1c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112575412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2112575412 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.117856092
Short name T398
Test name
Test status
Simulation time 1332595257 ps
CPU time 31.72 seconds
Started Jul 01 12:20:29 PM PDT 24
Finished Jul 01 12:21:01 PM PDT 24
Peak memory 226248 kb
Host smart-b9f3585e-8207-45b2-8384-ca6e4e28bb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117856092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.117856092 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.3800222014
Short name T795
Test name
Test status
Simulation time 4752456787 ps
CPU time 262.52 seconds
Started Jul 01 12:20:50 PM PDT 24
Finished Jul 01 12:25:13 PM PDT 24
Peak memory 269364 kb
Host smart-45d91f22-a603-4c64-bed4-79c52df1d584
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3800222014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.3800222014 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.1996432146
Short name T505
Test name
Test status
Simulation time 216608981 ps
CPU time 6.65 seconds
Started Jul 01 12:20:44 PM PDT 24
Finished Jul 01 12:20:51 PM PDT 24
Peak memory 218084 kb
Host smart-e713e9c7-c284-48ce-ab96-c466bb072112
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996432146 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.1996432146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.1134522413
Short name T298
Test name
Test status
Simulation time 987324298 ps
CPU time 6.3 seconds
Started Jul 01 12:20:43 PM PDT 24
Finished Jul 01 12:20:50 PM PDT 24
Peak memory 218172 kb
Host smart-e356433a-449f-4410-9e8f-bc4ad9b35e45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134522413 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.1134522413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.2775777724
Short name T557
Test name
Test status
Simulation time 75282349964 ps
CPU time 2215.95 seconds
Started Jul 01 12:20:57 PM PDT 24
Finished Jul 01 12:57:54 PM PDT 24
Peak memory 394692 kb
Host smart-68777021-e006-42ce-8813-e65704f8956a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2775777724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.2775777724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.1629400199
Short name T627
Test name
Test status
Simulation time 20536724293 ps
CPU time 2029.56 seconds
Started Jul 01 12:20:42 PM PDT 24
Finished Jul 01 12:54:32 PM PDT 24
Peak memory 396316 kb
Host smart-37cf04d2-61fe-4193-9beb-0b740c531607
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1629400199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.1629400199 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.1447893169
Short name T924
Test name
Test status
Simulation time 425909386032 ps
CPU time 1692.14 seconds
Started Jul 01 12:20:43 PM PDT 24
Finished Jul 01 12:48:56 PM PDT 24
Peak memory 339336 kb
Host smart-3123791b-5250-4637-84bc-05fbd7676447
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1447893169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.1447893169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.195722813
Short name T787
Test name
Test status
Simulation time 370984021185 ps
CPU time 1352.62 seconds
Started Jul 01 12:20:39 PM PDT 24
Finished Jul 01 12:43:12 PM PDT 24
Peak memory 300616 kb
Host smart-694a3a76-e724-45b8-9e0b-9ffd45e5bb30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=195722813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.195722813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.2686164438
Short name T980
Test name
Test status
Simulation time 62344615176 ps
CPU time 5581.73 seconds
Started Jul 01 12:20:40 PM PDT 24
Finished Jul 01 01:53:43 PM PDT 24
Peak memory 663348 kb
Host smart-09392caf-ca5a-454b-aa58-84212c3e5204
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2686164438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.2686164438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.3646973065
Short name T507
Test name
Test status
Simulation time 1558613755368 ps
CPU time 5345.21 seconds
Started Jul 01 12:20:43 PM PDT 24
Finished Jul 01 01:49:50 PM PDT 24
Peak memory 563244 kb
Host smart-6cd78592-2135-4d95-ac5b-a1724b8f6fa9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3646973065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.3646973065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.144144320
Short name T283
Test name
Test status
Simulation time 15852861 ps
CPU time 0.85 seconds
Started Jul 01 12:21:21 PM PDT 24
Finished Jul 01 12:21:23 PM PDT 24
Peak memory 217932 kb
Host smart-b4140d7a-b81f-442d-aefc-795e9f53e8ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144144320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.144144320 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.3384973451
Short name T659
Test name
Test status
Simulation time 729537559 ps
CPU time 38.55 seconds
Started Jul 01 12:21:12 PM PDT 24
Finished Jul 01 12:21:51 PM PDT 24
Peak memory 226436 kb
Host smart-63b1c185-8c3b-4b92-ad72-32b341f11151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384973451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3384973451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.1664020386
Short name T394
Test name
Test status
Simulation time 23107669646 ps
CPU time 1344.26 seconds
Started Jul 01 12:20:55 PM PDT 24
Finished Jul 01 12:43:20 PM PDT 24
Peak memory 242768 kb
Host smart-e0ad03f7-da3c-47b4-b2e4-d5109d7ebca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664020386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.1664020386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.1293435491
Short name T594
Test name
Test status
Simulation time 109046482397 ps
CPU time 267.55 seconds
Started Jul 01 12:21:10 PM PDT 24
Finished Jul 01 12:25:38 PM PDT 24
Peak memory 247436 kb
Host smart-135ec733-251a-49e9-bbc1-2b3bb0640990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293435491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1293435491 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.1406779649
Short name T22
Test name
Test status
Simulation time 5598900785 ps
CPU time 137.31 seconds
Started Jul 01 12:21:09 PM PDT 24
Finished Jul 01 12:23:27 PM PDT 24
Peak memory 242696 kb
Host smart-0b53fff1-1e1f-488d-a829-b1360aebde42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406779649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1406779649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.504116203
Short name T114
Test name
Test status
Simulation time 785006106 ps
CPU time 4.29 seconds
Started Jul 01 12:21:16 PM PDT 24
Finished Jul 01 12:21:20 PM PDT 24
Peak memory 218208 kb
Host smart-5bdfeb3e-faa3-4c6d-a637-68c3c1b0a01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504116203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.504116203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.3502766111
Short name T44
Test name
Test status
Simulation time 61422140 ps
CPU time 1.6 seconds
Started Jul 01 12:21:21 PM PDT 24
Finished Jul 01 12:21:24 PM PDT 24
Peak memory 218196 kb
Host smart-1ed71eb6-8059-44ea-a275-d0a64f21d4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502766111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3502766111 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.2704835216
Short name T118
Test name
Test status
Simulation time 449309120821 ps
CPU time 3491.61 seconds
Started Jul 01 12:20:53 PM PDT 24
Finished Jul 01 01:19:05 PM PDT 24
Peak memory 475544 kb
Host smart-1a8bfc52-6b98-4e60-b7e9-dc0967413b8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704835216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.2704835216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_smoke.3753263446
Short name T975
Test name
Test status
Simulation time 34583249121 ps
CPU time 89.08 seconds
Started Jul 01 12:20:48 PM PDT 24
Finished Jul 01 12:22:18 PM PDT 24
Peak memory 226320 kb
Host smart-edaf13d1-cc69-4ac6-b1c7-be9ac6360b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753263446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3753263446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.739458979
Short name T512
Test name
Test status
Simulation time 35181556118 ps
CPU time 1164.4 seconds
Started Jul 01 12:21:22 PM PDT 24
Finished Jul 01 12:40:47 PM PDT 24
Peak memory 351356 kb
Host smart-091ebb46-4778-4ae4-b28f-22d94c7df424
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=739458979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.739458979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.1407858103
Short name T1012
Test name
Test status
Simulation time 297787285 ps
CPU time 6.77 seconds
Started Jul 01 12:21:05 PM PDT 24
Finished Jul 01 12:21:12 PM PDT 24
Peak memory 218272 kb
Host smart-265690d2-50fa-448b-a167-6e4476cd70be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407858103 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.1407858103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.1111734186
Short name T93
Test name
Test status
Simulation time 294781553 ps
CPU time 6.8 seconds
Started Jul 01 12:21:09 PM PDT 24
Finished Jul 01 12:21:16 PM PDT 24
Peak memory 218060 kb
Host smart-93d6c50e-1a19-44bf-bdd5-20fb74c22474
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111734186 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.1111734186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.3435325395
Short name T33
Test name
Test status
Simulation time 41325995879 ps
CPU time 1863.45 seconds
Started Jul 01 12:20:59 PM PDT 24
Finished Jul 01 12:52:03 PM PDT 24
Peak memory 388564 kb
Host smart-46dc8a87-b711-454b-9622-e6e62254eed6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3435325395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.3435325395 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.4027676918
Short name T340
Test name
Test status
Simulation time 130816134020 ps
CPU time 2195.48 seconds
Started Jul 01 12:21:00 PM PDT 24
Finished Jul 01 12:57:36 PM PDT 24
Peak memory 391172 kb
Host smart-a29330a4-1a22-40f4-b279-73613805d2d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4027676918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.4027676918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.3620166657
Short name T689
Test name
Test status
Simulation time 239278405380 ps
CPU time 1753.63 seconds
Started Jul 01 12:21:00 PM PDT 24
Finished Jul 01 12:50:15 PM PDT 24
Peak memory 331816 kb
Host smart-c447ad45-17b3-4e5b-a4a2-e06951e4465a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3620166657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.3620166657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.910205062
Short name T905
Test name
Test status
Simulation time 102939327345 ps
CPU time 1331.08 seconds
Started Jul 01 12:21:03 PM PDT 24
Finished Jul 01 12:43:14 PM PDT 24
Peak memory 301440 kb
Host smart-1309fde1-fe6c-4828-b475-ffc067d3ae88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=910205062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.910205062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.1926789743
Short name T304
Test name
Test status
Simulation time 239277504537 ps
CPU time 5258.44 seconds
Started Jul 01 12:21:05 PM PDT 24
Finished Jul 01 01:48:45 PM PDT 24
Peak memory 651516 kb
Host smart-202eca10-b8b1-4fce-a6ba-2e5acc4eaf99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1926789743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.1926789743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.579565222
Short name T286
Test name
Test status
Simulation time 53100405050 ps
CPU time 4798.33 seconds
Started Jul 01 12:21:04 PM PDT 24
Finished Jul 01 01:41:03 PM PDT 24
Peak memory 569516 kb
Host smart-0a82659d-666a-4bbd-98e6-da981ccbd237
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=579565222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.579565222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.4219588960
Short name T715
Test name
Test status
Simulation time 14181235 ps
CPU time 0.83 seconds
Started Jul 01 12:21:50 PM PDT 24
Finished Jul 01 12:21:51 PM PDT 24
Peak memory 217944 kb
Host smart-bc5564e2-2b1e-4a12-a465-8da2ac8e81b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219588960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.4219588960 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.2210906973
Short name T548
Test name
Test status
Simulation time 1908801654 ps
CPU time 28.78 seconds
Started Jul 01 12:21:41 PM PDT 24
Finished Jul 01 12:22:10 PM PDT 24
Peak memory 223220 kb
Host smart-39e20c05-f130-40df-b53f-7f1c612a835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210906973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2210906973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.2668606401
Short name T762
Test name
Test status
Simulation time 19665291583 ps
CPU time 807.02 seconds
Started Jul 01 12:21:26 PM PDT 24
Finished Jul 01 12:34:54 PM PDT 24
Peak memory 241356 kb
Host smart-c59c4e57-6757-43a0-98fe-733e3c53793c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668606401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.2668606401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.862324234
Short name T256
Test name
Test status
Simulation time 14062574037 ps
CPU time 79.83 seconds
Started Jul 01 12:21:37 PM PDT 24
Finished Jul 01 12:22:57 PM PDT 24
Peak memory 229604 kb
Host smart-70ca1163-50aa-45cb-baf6-1c57c4d2e62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862324234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.862324234 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.361132523
Short name T23
Test name
Test status
Simulation time 5548864911 ps
CPU time 485.39 seconds
Started Jul 01 12:21:40 PM PDT 24
Finished Jul 01 12:29:47 PM PDT 24
Peak memory 267868 kb
Host smart-779c3330-753b-49a1-a90a-75cef54ee05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361132523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.361132523 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.2566526032
Short name T955
Test name
Test status
Simulation time 2208629807 ps
CPU time 11.46 seconds
Started Jul 01 12:21:38 PM PDT 24
Finished Jul 01 12:21:50 PM PDT 24
Peak memory 223824 kb
Host smart-7676b7c9-876b-4a25-99e7-5718a263f558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566526032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2566526032 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.3643411160
Short name T498
Test name
Test status
Simulation time 100438322 ps
CPU time 1.27 seconds
Started Jul 01 12:21:43 PM PDT 24
Finished Jul 01 12:21:45 PM PDT 24
Peak memory 218228 kb
Host smart-0749c9d5-483b-4e6b-b918-90b672994c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643411160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3643411160 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.3562874550
Short name T999
Test name
Test status
Simulation time 302802601492 ps
CPU time 1997.59 seconds
Started Jul 01 12:21:25 PM PDT 24
Finished Jul 01 12:54:43 PM PDT 24
Peak memory 375976 kb
Host smart-299c522d-18cb-4b93-ae28-3e80f7856724
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562874550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.3562874550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.3432597698
Short name T952
Test name
Test status
Simulation time 29506066482 ps
CPU time 47.74 seconds
Started Jul 01 12:21:26 PM PDT 24
Finished Jul 01 12:22:15 PM PDT 24
Peak memory 226240 kb
Host smart-cd8fdc67-feff-4dd4-8151-c96cdb60c51b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432597698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3432597698 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.1841435241
Short name T569
Test name
Test status
Simulation time 11960793173 ps
CPU time 57.13 seconds
Started Jul 01 12:21:28 PM PDT 24
Finished Jul 01 12:22:26 PM PDT 24
Peak memory 226240 kb
Host smart-fabcc575-081e-4784-9704-c7b6ee810e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841435241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1841435241 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.715230156
Short name T667
Test name
Test status
Simulation time 1193376425 ps
CPU time 6.73 seconds
Started Jul 01 12:21:31 PM PDT 24
Finished Jul 01 12:21:38 PM PDT 24
Peak memory 219060 kb
Host smart-86f970ee-e3f1-43e5-8c2b-0810d124e8b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715230156 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.kmac_test_vectors_kmac.715230156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.723355931
Short name T891
Test name
Test status
Simulation time 160478306 ps
CPU time 5.77 seconds
Started Jul 01 12:21:32 PM PDT 24
Finished Jul 01 12:21:38 PM PDT 24
Peak memory 219264 kb
Host smart-a0ea303b-9db9-414b-b977-3195dbe8a504
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723355931 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.kmac_test_vectors_kmac_xof.723355931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.698779863
Short name T630
Test name
Test status
Simulation time 438172667592 ps
CPU time 2455.82 seconds
Started Jul 01 12:21:26 PM PDT 24
Finished Jul 01 01:02:23 PM PDT 24
Peak memory 394532 kb
Host smart-54642e68-979c-461b-a588-a537404eb4e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=698779863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.698779863 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.326057328
Short name T846
Test name
Test status
Simulation time 189199493542 ps
CPU time 2195.28 seconds
Started Jul 01 12:21:27 PM PDT 24
Finished Jul 01 12:58:03 PM PDT 24
Peak memory 389888 kb
Host smart-2803e76c-dabf-43d7-b7e4-3f2f7489e201
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=326057328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.326057328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.848196097
Short name T347
Test name
Test status
Simulation time 47490476157 ps
CPU time 1735.63 seconds
Started Jul 01 12:21:28 PM PDT 24
Finished Jul 01 12:50:24 PM PDT 24
Peak memory 336100 kb
Host smart-ed91a8d6-a77c-434e-8cd4-19711f003a0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=848196097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.848196097 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.811641710
Short name T364
Test name
Test status
Simulation time 234720613060 ps
CPU time 1285.12 seconds
Started Jul 01 12:21:25 PM PDT 24
Finished Jul 01 12:42:51 PM PDT 24
Peak memory 298460 kb
Host smart-97a6dd17-4677-4ed2-a281-04c552537613
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=811641710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.811641710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.1354451587
Short name T668
Test name
Test status
Simulation time 563722706459 ps
CPU time 6765.36 seconds
Started Jul 01 12:21:25 PM PDT 24
Finished Jul 01 02:14:11 PM PDT 24
Peak memory 656708 kb
Host smart-dde6f172-5361-4859-bc23-800d0cf3da4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1354451587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.1354451587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.369242923
Short name T419
Test name
Test status
Simulation time 443189350141 ps
CPU time 5344.68 seconds
Started Jul 01 12:21:27 PM PDT 24
Finished Jul 01 01:50:33 PM PDT 24
Peak memory 568460 kb
Host smart-744c7576-81d4-4456-a6a1-ff9afcaf5b31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=369242923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.369242923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.4049697727
Short name T643
Test name
Test status
Simulation time 28496882 ps
CPU time 0.86 seconds
Started Jul 01 12:22:13 PM PDT 24
Finished Jul 01 12:22:15 PM PDT 24
Peak memory 218116 kb
Host smart-eecc6fd0-1d95-4c9a-9270-165e375f147b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049697727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.4049697727 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.1704074196
Short name T675
Test name
Test status
Simulation time 31621970114 ps
CPU time 298.11 seconds
Started Jul 01 12:22:00 PM PDT 24
Finished Jul 01 12:26:59 PM PDT 24
Peak memory 246192 kb
Host smart-a6e39efe-fc20-4c8a-858c-e79e564aab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704074196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1704074196 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.1704117479
Short name T603
Test name
Test status
Simulation time 109330323404 ps
CPU time 1357 seconds
Started Jul 01 12:21:54 PM PDT 24
Finished Jul 01 12:44:32 PM PDT 24
Peak memory 236824 kb
Host smart-5e8be83e-8bc2-4dc0-89f9-7c309b0aef24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704117479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1704117479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.2469291656
Short name T904
Test name
Test status
Simulation time 9322172246 ps
CPU time 198.42 seconds
Started Jul 01 12:22:06 PM PDT 24
Finished Jul 01 12:25:25 PM PDT 24
Peak memory 241760 kb
Host smart-29f407ed-5fcf-4874-a432-01d86d918e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469291656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2469291656 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.3013516558
Short name T584
Test name
Test status
Simulation time 13118482186 ps
CPU time 220.73 seconds
Started Jul 01 12:22:04 PM PDT 24
Finished Jul 01 12:25:45 PM PDT 24
Peak memory 252936 kb
Host smart-8224dbeb-2721-4192-895b-9e4f1008cc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013516558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3013516558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.420286720
Short name T658
Test name
Test status
Simulation time 2418591338 ps
CPU time 4.93 seconds
Started Jul 01 12:22:06 PM PDT 24
Finished Jul 01 12:22:12 PM PDT 24
Peak memory 218240 kb
Host smart-59b4d16f-39d0-4e9e-af21-41062694c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420286720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.420286720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.2867138344
Short name T959
Test name
Test status
Simulation time 195077541 ps
CPU time 16.43 seconds
Started Jul 01 12:22:06 PM PDT 24
Finished Jul 01 12:22:23 PM PDT 24
Peak memory 229656 kb
Host smart-cf686a8c-03de-4c18-b1f4-653692627133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867138344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2867138344 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.3052407336
Short name T15
Test name
Test status
Simulation time 119412970116 ps
CPU time 2983.03 seconds
Started Jul 01 12:21:49 PM PDT 24
Finished Jul 01 01:11:33 PM PDT 24
Peak memory 451944 kb
Host smart-e15abf4f-7772-4f98-933b-089175e86070
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052407336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.3052407336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.377274731
Short name T908
Test name
Test status
Simulation time 6995672288 ps
CPU time 84.29 seconds
Started Jul 01 12:21:48 PM PDT 24
Finished Jul 01 12:23:12 PM PDT 24
Peak memory 229760 kb
Host smart-b61424f1-5aab-48cd-bef2-fd754322d4ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377274731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.377274731 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.3279920619
Short name T267
Test name
Test status
Simulation time 8723400257 ps
CPU time 70.48 seconds
Started Jul 01 12:21:47 PM PDT 24
Finished Jul 01 12:22:58 PM PDT 24
Peak memory 218328 kb
Host smart-26c59440-658d-4098-84c4-975534066da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279920619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3279920619 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.1239355128
Short name T359
Test name
Test status
Simulation time 70686427713 ps
CPU time 1864.8 seconds
Started Jul 01 12:22:15 PM PDT 24
Finished Jul 01 12:53:21 PM PDT 24
Peak memory 400468 kb
Host smart-9d6d6ee2-6fa4-4007-b055-dddb653fbcdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1239355128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1239355128 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.606984014
Short name T743
Test name
Test status
Simulation time 1347838200 ps
CPU time 7.08 seconds
Started Jul 01 12:22:05 PM PDT 24
Finished Jul 01 12:22:13 PM PDT 24
Peak memory 219088 kb
Host smart-911e8e4e-13ef-4dce-a8a2-b5c918d34025
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606984014 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.kmac_test_vectors_kmac.606984014 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.48547805
Short name T776
Test name
Test status
Simulation time 1066384774 ps
CPU time 6.66 seconds
Started Jul 01 12:22:04 PM PDT 24
Finished Jul 01 12:22:12 PM PDT 24
Peak memory 218164 kb
Host smart-71a1dc7c-fadf-4d71-beba-3a145084c325
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48547805 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.kmac_test_vectors_kmac_xof.48547805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.1287975338
Short name T884
Test name
Test status
Simulation time 270791980565 ps
CPU time 2445.95 seconds
Started Jul 01 12:21:56 PM PDT 24
Finished Jul 01 01:02:42 PM PDT 24
Peak memory 394664 kb
Host smart-f55385c8-9652-44d9-af23-057292a138a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1287975338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.1287975338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.1032166511
Short name T36
Test name
Test status
Simulation time 199148214073 ps
CPU time 2255.1 seconds
Started Jul 01 12:21:56 PM PDT 24
Finished Jul 01 12:59:32 PM PDT 24
Peak memory 383364 kb
Host smart-52917534-a213-443e-8b33-4a34f5840839
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1032166511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.1032166511 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.731564936
Short name T989
Test name
Test status
Simulation time 153601684125 ps
CPU time 1671.47 seconds
Started Jul 01 12:21:56 PM PDT 24
Finished Jul 01 12:49:48 PM PDT 24
Peak memory 338472 kb
Host smart-459008a9-c2d2-4a31-8e51-b3489bb0456e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=731564936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.731564936 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.2144297620
Short name T228
Test name
Test status
Simulation time 43720106941 ps
CPU time 1246.52 seconds
Started Jul 01 12:21:54 PM PDT 24
Finished Jul 01 12:42:41 PM PDT 24
Peak memory 300860 kb
Host smart-f0c8e0ac-b477-45cc-98d9-006e50efd03f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2144297620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.2144297620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.793510490
Short name T251
Test name
Test status
Simulation time 399109826836 ps
CPU time 5211.12 seconds
Started Jul 01 12:21:55 PM PDT 24
Finished Jul 01 01:48:47 PM PDT 24
Peak memory 650876 kb
Host smart-063f6629-71eb-4365-ba15-bff00565e77d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=793510490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.793510490 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.1375825183
Short name T1030
Test name
Test status
Simulation time 236971429328 ps
CPU time 4379.49 seconds
Started Jul 01 12:22:01 PM PDT 24
Finished Jul 01 01:35:02 PM PDT 24
Peak memory 566648 kb
Host smart-cab8122b-e296-47c4-8606-f92481b5670d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1375825183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.1375825183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.3387056958
Short name T255
Test name
Test status
Simulation time 14611592 ps
CPU time 0.82 seconds
Started Jul 01 12:22:37 PM PDT 24
Finished Jul 01 12:22:39 PM PDT 24
Peak memory 217916 kb
Host smart-8ca43b4f-aa4c-4b21-8e9c-2bb45c5c48a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387056958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3387056958 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.1353791688
Short name T781
Test name
Test status
Simulation time 12553270521 ps
CPU time 115.23 seconds
Started Jul 01 12:22:31 PM PDT 24
Finished Jul 01 12:24:26 PM PDT 24
Peak memory 235392 kb
Host smart-1f5e2463-328d-4b67-bc5f-66f4e2828612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353791688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1353791688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.2922278293
Short name T159
Test name
Test status
Simulation time 22609271251 ps
CPU time 1086.25 seconds
Started Jul 01 12:22:20 PM PDT 24
Finished Jul 01 12:40:26 PM PDT 24
Peak memory 238488 kb
Host smart-4d4bde18-ba29-4283-9001-e2d7c98fbd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922278293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.2922278293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.2693750457
Short name T521
Test name
Test status
Simulation time 5887101082 ps
CPU time 40.72 seconds
Started Jul 01 12:22:31 PM PDT 24
Finished Jul 01 12:23:12 PM PDT 24
Peak memory 226276 kb
Host smart-1d330273-b54a-4a11-99b8-e1f836bf7b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693750457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2693750457 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.1634558305
Short name T1036
Test name
Test status
Simulation time 11666222588 ps
CPU time 414.89 seconds
Started Jul 01 12:22:32 PM PDT 24
Finished Jul 01 12:29:28 PM PDT 24
Peak memory 267264 kb
Host smart-7f8be712-947c-4186-a7f5-bdeaa247b055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634558305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1634558305 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.1087085890
Short name T873
Test name
Test status
Simulation time 1722018554 ps
CPU time 6.81 seconds
Started Jul 01 12:22:37 PM PDT 24
Finished Jul 01 12:22:44 PM PDT 24
Peak memory 218368 kb
Host smart-342494d5-e94d-48d6-987a-2623169d4e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087085890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1087085890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.1983077749
Short name T897
Test name
Test status
Simulation time 583191336 ps
CPU time 18.18 seconds
Started Jul 01 12:22:37 PM PDT 24
Finished Jul 01 12:22:56 PM PDT 24
Peak memory 234560 kb
Host smart-c6b909db-4275-498b-819b-4073ad9bcb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983077749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1983077749 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.1864896948
Short name T125
Test name
Test status
Simulation time 77376240968 ps
CPU time 2029.08 seconds
Started Jul 01 12:22:18 PM PDT 24
Finished Jul 01 12:56:08 PM PDT 24
Peak memory 403860 kb
Host smart-74df36a9-95af-440a-99f1-108eb9ac46f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864896948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.1864896948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.3345277598
Short name T1064
Test name
Test status
Simulation time 1356344955 ps
CPU time 8.15 seconds
Started Jul 01 12:22:19 PM PDT 24
Finished Jul 01 12:22:28 PM PDT 24
Peak memory 222924 kb
Host smart-adb1ed25-f6d3-4137-b896-93b5d627682f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345277598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.3345277598 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.1210848125
Short name T950
Test name
Test status
Simulation time 1796368716 ps
CPU time 37.45 seconds
Started Jul 01 12:22:13 PM PDT 24
Finished Jul 01 12:22:51 PM PDT 24
Peak memory 226256 kb
Host smart-59d566d3-b731-42c4-9c59-cdef146cfe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210848125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1210848125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.2983176887
Short name T82
Test name
Test status
Simulation time 322068446012 ps
CPU time 2537.08 seconds
Started Jul 01 12:22:40 PM PDT 24
Finished Jul 01 01:04:57 PM PDT 24
Peak memory 455960 kb
Host smart-d2be12eb-0f17-4641-87af-ddded194601c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2983176887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.2983176887 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.2577733336
Short name T616
Test name
Test status
Simulation time 860745616 ps
CPU time 5.95 seconds
Started Jul 01 12:22:32 PM PDT 24
Finished Jul 01 12:22:38 PM PDT 24
Peak memory 218208 kb
Host smart-f8870f5b-6803-46d7-bd93-b2ed7c616591
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577733336 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.2577733336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.2854562029
Short name T862
Test name
Test status
Simulation time 571009844 ps
CPU time 6.76 seconds
Started Jul 01 12:22:32 PM PDT 24
Finished Jul 01 12:22:39 PM PDT 24
Peak memory 218204 kb
Host smart-8fd4c0fe-5aad-4642-b021-df20a0ba3899
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854562029 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.2854562029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.1337689936
Short name T943
Test name
Test status
Simulation time 21608164542 ps
CPU time 1701.66 seconds
Started Jul 01 12:22:25 PM PDT 24
Finished Jul 01 12:50:47 PM PDT 24
Peak memory 389120 kb
Host smart-7997b0ba-fd53-4fe3-a6c9-e421a2ad4222
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1337689936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.1337689936 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.1266700807
Short name T624
Test name
Test status
Simulation time 29831899257 ps
CPU time 1399.85 seconds
Started Jul 01 12:22:25 PM PDT 24
Finished Jul 01 12:45:46 PM PDT 24
Peak memory 336660 kb
Host smart-d8319927-f1ac-4b6e-92ce-dcc2d2eb763b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1266700807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.1266700807 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.2105007748
Short name T617
Test name
Test status
Simulation time 98557676656 ps
CPU time 1343.07 seconds
Started Jul 01 12:22:25 PM PDT 24
Finished Jul 01 12:44:49 PM PDT 24
Peak memory 297832 kb
Host smart-35922f1d-e051-4075-9c6f-4facc8cce882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2105007748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.2105007748 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.2687952717
Short name T533
Test name
Test status
Simulation time 850293506173 ps
CPU time 5553.74 seconds
Started Jul 01 12:22:32 PM PDT 24
Finished Jul 01 01:55:07 PM PDT 24
Peak memory 647272 kb
Host smart-a9805dcc-da0d-4330-9135-9f9ef68cf779
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2687952717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.2687952717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.1797002833
Short name T249
Test name
Test status
Simulation time 118499285972 ps
CPU time 4776.34 seconds
Started Jul 01 12:22:32 PM PDT 24
Finished Jul 01 01:42:10 PM PDT 24
Peak memory 571184 kb
Host smart-bf342258-10f0-4dab-97d6-6af5ff5a47c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1797002833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.1797002833 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.4172853733
Short name T705
Test name
Test status
Simulation time 17807191 ps
CPU time 0.86 seconds
Started Jul 01 12:23:07 PM PDT 24
Finished Jul 01 12:23:08 PM PDT 24
Peak memory 217828 kb
Host smart-d67cfe94-4e4b-4fb3-8587-868314db8492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172853733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.4172853733 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.2990344155
Short name T1063
Test name
Test status
Simulation time 92817832047 ps
CPU time 459.3 seconds
Started Jul 01 12:22:59 PM PDT 24
Finished Jul 01 12:30:39 PM PDT 24
Peak memory 254068 kb
Host smart-a339ef75-31d5-4ecd-9905-55efee5a228b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990344155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2990344155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.3818602374
Short name T1042
Test name
Test status
Simulation time 39293337402 ps
CPU time 1389.85 seconds
Started Jul 01 12:22:47 PM PDT 24
Finished Jul 01 12:45:58 PM PDT 24
Peak memory 238624 kb
Host smart-f01f17f4-38b3-46ea-b2b8-aa761a5a80c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818602374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.3818602374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.2155159336
Short name T843
Test name
Test status
Simulation time 16682942731 ps
CPU time 95.65 seconds
Started Jul 01 12:22:57 PM PDT 24
Finished Jul 01 12:24:34 PM PDT 24
Peak memory 231820 kb
Host smart-611bf2e1-e290-4623-ab07-4c6e12c6040f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155159336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2155159336 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.113008757
Short name T682
Test name
Test status
Simulation time 2695428638 ps
CPU time 24 seconds
Started Jul 01 12:22:58 PM PDT 24
Finished Jul 01 12:23:23 PM PDT 24
Peak memory 239320 kb
Host smart-13e6304b-7c7e-4f3b-a6b3-1fde6db6ff70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113008757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.113008757 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.2806234816
Short name T599
Test name
Test status
Simulation time 1335153080 ps
CPU time 5.08 seconds
Started Jul 01 12:23:03 PM PDT 24
Finished Jul 01 12:23:10 PM PDT 24
Peak memory 218180 kb
Host smart-924acb37-1e38-4ee7-8e03-81a0e50d4d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806234816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2806234816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.565281686
Short name T896
Test name
Test status
Simulation time 32232022 ps
CPU time 1.34 seconds
Started Jul 01 12:23:03 PM PDT 24
Finished Jul 01 12:23:05 PM PDT 24
Peak memory 219004 kb
Host smart-de46ce5f-fb13-4e84-a1af-92d27f10e16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565281686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.565281686 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.1138894422
Short name T446
Test name
Test status
Simulation time 42792862000 ps
CPU time 1083.43 seconds
Started Jul 01 12:22:42 PM PDT 24
Finished Jul 01 12:40:46 PM PDT 24
Peak memory 300656 kb
Host smart-a4fbe15b-4a64-46b7-8d66-ed14e74655fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138894422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.1138894422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.3486811971
Short name T906
Test name
Test status
Simulation time 1133961585 ps
CPU time 41.34 seconds
Started Jul 01 12:22:45 PM PDT 24
Finished Jul 01 12:23:27 PM PDT 24
Peak memory 226232 kb
Host smart-1214bf2d-7c92-44e1-8082-445a53222d15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486811971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3486811971 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.4114047615
Short name T58
Test name
Test status
Simulation time 645800851 ps
CPU time 12.35 seconds
Started Jul 01 12:22:43 PM PDT 24
Finished Jul 01 12:22:56 PM PDT 24
Peak memory 225760 kb
Host smart-86b331ca-21b7-4553-8380-76338b9b8cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114047615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.4114047615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.1147544841
Short name T411
Test name
Test status
Simulation time 38520856414 ps
CPU time 321.81 seconds
Started Jul 01 12:23:03 PM PDT 24
Finished Jul 01 12:28:26 PM PDT 24
Peak memory 271668 kb
Host smart-841d42e6-fb4b-4f1f-a28f-534440625064
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1147544841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1147544841 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.489158769
Short name T749
Test name
Test status
Simulation time 124900517 ps
CPU time 5.16 seconds
Started Jul 01 12:22:53 PM PDT 24
Finished Jul 01 12:22:59 PM PDT 24
Peak memory 218340 kb
Host smart-0181267c-4f6c-48bb-95fa-80d8beea94fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489158769 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.kmac_test_vectors_kmac.489158769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.1986945182
Short name T794
Test name
Test status
Simulation time 104503254 ps
CPU time 5.87 seconds
Started Jul 01 12:22:57 PM PDT 24
Finished Jul 01 12:23:04 PM PDT 24
Peak memory 218172 kb
Host smart-4ccad4e9-c4bb-4633-bb9a-d0e8f24a32f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986945182 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.1986945182 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.2133168860
Short name T732
Test name
Test status
Simulation time 181651548898 ps
CPU time 2209.12 seconds
Started Jul 01 12:22:47 PM PDT 24
Finished Jul 01 12:59:37 PM PDT 24
Peak memory 396024 kb
Host smart-631e1f40-3ee5-4496-a5ed-560741385ae0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2133168860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.2133168860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.1212431941
Short name T285
Test name
Test status
Simulation time 61650518433 ps
CPU time 2094.72 seconds
Started Jul 01 12:22:46 PM PDT 24
Finished Jul 01 12:57:42 PM PDT 24
Peak memory 384720 kb
Host smart-a5852add-9088-4555-9230-2a74083ba6bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1212431941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.1212431941 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.3561127105
Short name T724
Test name
Test status
Simulation time 314044024828 ps
CPU time 1753.51 seconds
Started Jul 01 12:22:45 PM PDT 24
Finished Jul 01 12:52:00 PM PDT 24
Peak memory 346628 kb
Host smart-6538b0c6-0d7d-4342-afe8-c9b6fa8e3bf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3561127105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.3561127105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.2728805061
Short name T816
Test name
Test status
Simulation time 185419012988 ps
CPU time 1225.11 seconds
Started Jul 01 12:22:47 PM PDT 24
Finished Jul 01 12:43:13 PM PDT 24
Peak memory 298916 kb
Host smart-90d93f1d-142f-41f1-a225-f4a4c7d1a8db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2728805061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2728805061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.1135753127
Short name T404
Test name
Test status
Simulation time 370919226532 ps
CPU time 6107.46 seconds
Started Jul 01 12:22:52 PM PDT 24
Finished Jul 01 02:04:41 PM PDT 24
Peak memory 656536 kb
Host smart-59b5d983-171c-4819-b460-4fcc19ca978e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1135753127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.1135753127 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.2113822811
Short name T542
Test name
Test status
Simulation time 215105183675 ps
CPU time 4738.9 seconds
Started Jul 01 12:22:54 PM PDT 24
Finished Jul 01 01:41:54 PM PDT 24
Peak memory 579032 kb
Host smart-4105bcf7-61ed-46f3-8ace-59c2f9405c52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2113822811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.2113822811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.1204102777
Short name T535
Test name
Test status
Simulation time 18431682 ps
CPU time 0.85 seconds
Started Jul 01 12:07:45 PM PDT 24
Finished Jul 01 12:07:47 PM PDT 24
Peak memory 217876 kb
Host smart-b0f61818-bb6a-4493-83e2-028035731852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204102777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1204102777 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.1614563871
Short name T271
Test name
Test status
Simulation time 9958313614 ps
CPU time 67.19 seconds
Started Jul 01 12:07:28 PM PDT 24
Finished Jul 01 12:08:36 PM PDT 24
Peak memory 229808 kb
Host smart-96dad14a-3e6f-4b03-af67-25470c8c3600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614563871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1614563871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.3874770203
Short name T201
Test name
Test status
Simulation time 437508536 ps
CPU time 37.68 seconds
Started Jul 01 12:07:36 PM PDT 24
Finished Jul 01 12:08:15 PM PDT 24
Peak memory 232988 kb
Host smart-8f1def5e-63b6-480d-b5bc-65d9bef91991
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3874770203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3874770203 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.4071929632
Short name T200
Test name
Test status
Simulation time 1579184425 ps
CPU time 27.46 seconds
Started Jul 01 12:07:34 PM PDT 24
Finished Jul 01 12:08:02 PM PDT 24
Peak memory 224988 kb
Host smart-472171ce-35af-490d-b942-f43ab9ccd4a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4071929632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.4071929632 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.1077831400
Short name T9
Test name
Test status
Simulation time 5544193747 ps
CPU time 7.04 seconds
Started Jul 01 12:07:40 PM PDT 24
Finished Jul 01 12:07:47 PM PDT 24
Peak memory 218384 kb
Host smart-4afc9d6d-28d3-4c70-9852-75561cb60e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077831400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1077831400 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_error.957999091
Short name T769
Test name
Test status
Simulation time 49940086302 ps
CPU time 170.39 seconds
Started Jul 01 12:07:34 PM PDT 24
Finished Jul 01 12:10:25 PM PDT 24
Peak memory 242976 kb
Host smart-3ae0b89c-cb66-4d12-accf-d8187dcd058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957999091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.957999091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.4137083772
Short name T374
Test name
Test status
Simulation time 427908462 ps
CPU time 3.74 seconds
Started Jul 01 12:07:34 PM PDT 24
Finished Jul 01 12:07:39 PM PDT 24
Peak memory 218136 kb
Host smart-811380a3-38c0-40d8-922f-d2ab2e253a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137083772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.4137083772 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.3013225671
Short name T67
Test name
Test status
Simulation time 62979659 ps
CPU time 1.36 seconds
Started Jul 01 12:07:40 PM PDT 24
Finished Jul 01 12:07:42 PM PDT 24
Peak memory 219312 kb
Host smart-1051a627-7686-4b8c-9b19-d46faf3b7877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013225671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3013225671 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.1159644002
Short name T210
Test name
Test status
Simulation time 31953984646 ps
CPU time 1321.54 seconds
Started Jul 01 12:07:20 PM PDT 24
Finished Jul 01 12:29:22 PM PDT 24
Peak memory 332236 kb
Host smart-0e74976a-07a6-4429-992c-c3e57638fbcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159644002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.1159644002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.3384650294
Short name T541
Test name
Test status
Simulation time 17773271267 ps
CPU time 254.98 seconds
Started Jul 01 12:07:30 PM PDT 24
Finished Jul 01 12:11:45 PM PDT 24
Peak memory 247192 kb
Host smart-8c42bec9-1d6c-4062-b586-14248b897718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384650294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3384650294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.2701521830
Short name T28
Test name
Test status
Simulation time 4734528541 ps
CPU time 62.84 seconds
Started Jul 01 12:07:39 PM PDT 24
Finished Jul 01 12:08:43 PM PDT 24
Peak memory 271540 kb
Host smart-1c5ef9aa-2601-40b9-8e60-134f101499cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701521830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2701521830 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.4171349627
Short name T730
Test name
Test status
Simulation time 12294908302 ps
CPU time 78.03 seconds
Started Jul 01 12:07:20 PM PDT 24
Finished Jul 01 12:08:39 PM PDT 24
Peak memory 230176 kb
Host smart-b4ed2681-2342-4e86-8dd9-1a533bdfe029
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171349627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.4171349627 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.4002272670
Short name T207
Test name
Test status
Simulation time 398653565 ps
CPU time 9.02 seconds
Started Jul 01 12:07:21 PM PDT 24
Finished Jul 01 12:07:31 PM PDT 24
Peak memory 226136 kb
Host smart-5aafe396-10a8-4aa7-9031-30addab2822e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002272670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.4002272670 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.1504900250
Short name T618
Test name
Test status
Simulation time 57289153531 ps
CPU time 161.6 seconds
Started Jul 01 12:07:39 PM PDT 24
Finished Jul 01 12:10:22 PM PDT 24
Peak memory 246004 kb
Host smart-cc019d28-185a-4f80-be3b-6938c1f7fac0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1504900250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1504900250 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.3029069533
Short name T549
Test name
Test status
Simulation time 137650083 ps
CPU time 6.12 seconds
Started Jul 01 12:07:30 PM PDT 24
Finished Jul 01 12:07:37 PM PDT 24
Peak memory 218200 kb
Host smart-190fcb9b-6c44-4aae-b719-848c20a98f02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029069533 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.3029069533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.3364023353
Short name T607
Test name
Test status
Simulation time 247722239 ps
CPU time 6.75 seconds
Started Jul 01 12:07:30 PM PDT 24
Finished Jul 01 12:07:38 PM PDT 24
Peak memory 218144 kb
Host smart-d5889b48-5890-4a23-ad0c-522d55a7f65a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364023353 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3364023353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.4153470263
Short name T335
Test name
Test status
Simulation time 87971526263 ps
CPU time 2270.47 seconds
Started Jul 01 12:07:23 PM PDT 24
Finished Jul 01 12:45:14 PM PDT 24
Peak memory 406408 kb
Host smart-9503ec1a-fe2d-4ab8-b226-cd63efef73ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4153470263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.4153470263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.2382951965
Short name T376
Test name
Test status
Simulation time 192907736269 ps
CPU time 2324.32 seconds
Started Jul 01 12:07:20 PM PDT 24
Finished Jul 01 12:46:05 PM PDT 24
Peak memory 389700 kb
Host smart-4e49c34a-69c6-4120-a5b2-1c9bbe235145
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2382951965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2382951965 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.65217479
Short name T495
Test name
Test status
Simulation time 479217865615 ps
CPU time 1764.55 seconds
Started Jul 01 12:07:25 PM PDT 24
Finished Jul 01 12:36:50 PM PDT 24
Peak memory 342972 kb
Host smart-685bd1cb-5466-4dd0-9221-1041a4ed8a90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=65217479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.65217479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.4266050933
Short name T232
Test name
Test status
Simulation time 44522707808 ps
CPU time 1135.24 seconds
Started Jul 01 12:07:24 PM PDT 24
Finished Jul 01 12:26:20 PM PDT 24
Peak memory 300580 kb
Host smart-ce8459bc-f314-49f0-b7a6-8c860498a476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4266050933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.4266050933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.3535265313
Short name T580
Test name
Test status
Simulation time 475808542425 ps
CPU time 6101.43 seconds
Started Jul 01 12:07:24 PM PDT 24
Finished Jul 01 01:49:07 PM PDT 24
Peak memory 662984 kb
Host smart-9edceb5f-8c26-4738-996a-1c5ebfe0f482
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3535265313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3535265313 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.4083792778
Short name T825
Test name
Test status
Simulation time 604572600867 ps
CPU time 5265.11 seconds
Started Jul 01 12:07:24 PM PDT 24
Finished Jul 01 01:35:10 PM PDT 24
Peak memory 571960 kb
Host smart-7f6dd539-ea3e-4b5a-b0ec-e23065215557
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4083792778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.4083792778 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.1268404585
Short name T836
Test name
Test status
Simulation time 17765308 ps
CPU time 0.82 seconds
Started Jul 01 12:23:29 PM PDT 24
Finished Jul 01 12:23:31 PM PDT 24
Peak memory 217904 kb
Host smart-7e462cbd-a677-4b2d-a3df-244c772cbc6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268404585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.1268404585 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_burst_write.2660059827
Short name T352
Test name
Test status
Simulation time 27239375869 ps
CPU time 1511.36 seconds
Started Jul 01 12:23:09 PM PDT 24
Finished Jul 01 12:48:22 PM PDT 24
Peak memory 242672 kb
Host smart-e00cb44d-65d7-4ab9-8067-878fff2799cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660059827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.2660059827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.1578755023
Short name T637
Test name
Test status
Simulation time 7100144268 ps
CPU time 122.34 seconds
Started Jul 01 12:23:18 PM PDT 24
Finished Jul 01 12:25:21 PM PDT 24
Peak memory 235500 kb
Host smart-c4593ddf-3ace-4907-9a93-7b68facd69fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578755023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.1578755023 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.3031331931
Short name T172
Test name
Test status
Simulation time 24578662431 ps
CPU time 384 seconds
Started Jul 01 12:23:18 PM PDT 24
Finished Jul 01 12:29:43 PM PDT 24
Peak memory 259116 kb
Host smart-5ba577c7-05a9-436d-8c9d-9e91f32694f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031331931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3031331931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.350799659
Short name T242
Test name
Test status
Simulation time 1187698858 ps
CPU time 9.26 seconds
Started Jul 01 12:23:24 PM PDT 24
Finished Jul 01 12:23:34 PM PDT 24
Peak memory 218112 kb
Host smart-7a71b616-298e-45e8-9345-f8368b89d854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350799659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.350799659 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.61508586
Short name T12
Test name
Test status
Simulation time 47355301 ps
CPU time 1.4 seconds
Started Jul 01 12:23:29 PM PDT 24
Finished Jul 01 12:23:31 PM PDT 24
Peak memory 218200 kb
Host smart-55241698-afb7-4699-b4db-2c01c444ad01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61508586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.61508586 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.1661016918
Short name T985
Test name
Test status
Simulation time 655787872368 ps
CPU time 3503.39 seconds
Started Jul 01 12:23:03 PM PDT 24
Finished Jul 01 01:21:28 PM PDT 24
Peak memory 465432 kb
Host smart-4b644957-39a5-4aaf-9e35-dd8024de2104
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661016918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.1661016918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.1351820068
Short name T522
Test name
Test status
Simulation time 769413269 ps
CPU time 21.37 seconds
Started Jul 01 12:23:12 PM PDT 24
Finished Jul 01 12:23:34 PM PDT 24
Peak memory 226228 kb
Host smart-96e39cd1-4dd4-4db8-af54-50a2acd063fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351820068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1351820068 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.2722195201
Short name T506
Test name
Test status
Simulation time 7919284366 ps
CPU time 32.86 seconds
Started Jul 01 12:23:06 PM PDT 24
Finished Jul 01 12:23:39 PM PDT 24
Peak memory 226220 kb
Host smart-630706cf-1629-46ca-9e0d-3882c960dbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722195201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2722195201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.2287774450
Short name T909
Test name
Test status
Simulation time 224438354797 ps
CPU time 1983.6 seconds
Started Jul 01 12:23:24 PM PDT 24
Finished Jul 01 12:56:29 PM PDT 24
Peak memory 413748 kb
Host smart-724bf674-bdbf-4b6d-850a-223e14ca1c5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2287774450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2287774450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.3682898915
Short name T60
Test name
Test status
Simulation time 483550570 ps
CPU time 5.62 seconds
Started Jul 01 12:23:15 PM PDT 24
Finished Jul 01 12:23:21 PM PDT 24
Peak memory 218208 kb
Host smart-2407d400-0ce5-4678-91a3-59bf4ed245f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682898915 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.3682898915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.561429809
Short name T220
Test name
Test status
Simulation time 432704705 ps
CPU time 5.83 seconds
Started Jul 01 12:23:19 PM PDT 24
Finished Jul 01 12:23:26 PM PDT 24
Peak memory 218336 kb
Host smart-368e1d2b-c647-4937-86f9-3c9171edc31f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561429809 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.kmac_test_vectors_kmac_xof.561429809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.3632571442
Short name T147
Test name
Test status
Simulation time 42102436465 ps
CPU time 2077.02 seconds
Started Jul 01 12:23:07 PM PDT 24
Finished Jul 01 12:57:45 PM PDT 24
Peak memory 396764 kb
Host smart-1fb1ce09-d92d-4d09-84d5-578c0109e441
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3632571442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.3632571442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.2935782540
Short name T780
Test name
Test status
Simulation time 19244812183 ps
CPU time 1806.08 seconds
Started Jul 01 12:23:13 PM PDT 24
Finished Jul 01 12:53:20 PM PDT 24
Peak memory 383188 kb
Host smart-f71db207-77a6-4331-8d6e-97a9e7551663
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2935782540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.2935782540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.3690628791
Short name T728
Test name
Test status
Simulation time 73004945883 ps
CPU time 1748.81 seconds
Started Jul 01 12:23:14 PM PDT 24
Finished Jul 01 12:52:24 PM PDT 24
Peak memory 342208 kb
Host smart-316c4796-27ef-47b1-b75e-b9aad39ade80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3690628791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.3690628791 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.1696890868
Short name T902
Test name
Test status
Simulation time 13233651622 ps
CPU time 1037.35 seconds
Started Jul 01 12:23:15 PM PDT 24
Finished Jul 01 12:40:33 PM PDT 24
Peak memory 298712 kb
Host smart-ad20ac2b-2362-4eba-a08c-fa05a7da826c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1696890868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.1696890868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.637430124
Short name T310
Test name
Test status
Simulation time 63065706129 ps
CPU time 5420.29 seconds
Started Jul 01 12:23:15 PM PDT 24
Finished Jul 01 01:53:37 PM PDT 24
Peak memory 683744 kb
Host smart-41bdf857-e35a-42fd-871b-2b4200e9b389
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=637430124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.637430124 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.2104976597
Short name T291
Test name
Test status
Simulation time 209448300169 ps
CPU time 4187.68 seconds
Started Jul 01 12:23:14 PM PDT 24
Finished Jul 01 01:33:02 PM PDT 24
Peak memory 573316 kb
Host smart-1e73ad29-dc55-4009-b24a-297bed6be116
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2104976597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.2104976597 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.1843786467
Short name T657
Test name
Test status
Simulation time 17888764 ps
CPU time 0.8 seconds
Started Jul 01 12:23:48 PM PDT 24
Finished Jul 01 12:23:49 PM PDT 24
Peak memory 217912 kb
Host smart-55ebdd7f-15f7-4f55-8e08-c313304abd41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843786467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.1843786467 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.3983321607
Short name T885
Test name
Test status
Simulation time 5033958253 ps
CPU time 34.27 seconds
Started Jul 01 12:23:44 PM PDT 24
Finished Jul 01 12:24:19 PM PDT 24
Peak memory 226272 kb
Host smart-370566f4-4600-4070-8f80-343c53cd13c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983321607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.3983321607 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.3247854818
Short name T362
Test name
Test status
Simulation time 116995342573 ps
CPU time 1320 seconds
Started Jul 01 12:23:31 PM PDT 24
Finished Jul 01 12:45:31 PM PDT 24
Peak memory 242724 kb
Host smart-8f3385b9-8ea0-4803-964b-c7496219072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247854818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3247854818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.1963722243
Short name T51
Test name
Test status
Simulation time 38875408285 ps
CPU time 231.04 seconds
Started Jul 01 12:23:43 PM PDT 24
Finished Jul 01 12:27:35 PM PDT 24
Peak memory 241168 kb
Host smart-c0ef09b7-98d7-42c0-9ead-6cfdceceaf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963722243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1963722243 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.2848270033
Short name T171
Test name
Test status
Simulation time 4999797555 ps
CPU time 156.7 seconds
Started Jul 01 12:23:43 PM PDT 24
Finished Jul 01 12:26:21 PM PDT 24
Peak memory 242864 kb
Host smart-e37a79ba-85db-49bd-8765-ecf9f2bf8ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848270033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2848270033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.3936705918
Short name T282
Test name
Test status
Simulation time 609979937 ps
CPU time 1.88 seconds
Started Jul 01 12:23:42 PM PDT 24
Finished Jul 01 12:23:44 PM PDT 24
Peak memory 218128 kb
Host smart-9b1afce3-ea52-4769-bae1-a4e3a80bce4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936705918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3936705918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.1622216139
Short name T413
Test name
Test status
Simulation time 10722102706 ps
CPU time 330.19 seconds
Started Jul 01 12:23:29 PM PDT 24
Finished Jul 01 12:29:00 PM PDT 24
Peak memory 245680 kb
Host smart-c09350c6-3efe-4dce-ac57-6ab49d4c1c87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622216139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.1622216139 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.1060435139
Short name T578
Test name
Test status
Simulation time 21966085915 ps
CPU time 158.49 seconds
Started Jul 01 12:23:31 PM PDT 24
Finished Jul 01 12:26:10 PM PDT 24
Peak memory 238040 kb
Host smart-de98d92b-3b83-4021-9b37-fd0813c2d288
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060435139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1060435139 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.2683718054
Short name T311
Test name
Test status
Simulation time 2613255197 ps
CPU time 57.89 seconds
Started Jul 01 12:23:30 PM PDT 24
Finished Jul 01 12:24:29 PM PDT 24
Peak memory 226256 kb
Host smart-52fdeb88-5b33-4f94-8266-b1baf654c353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683718054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2683718054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.1832284446
Short name T494
Test name
Test status
Simulation time 28545241910 ps
CPU time 768.02 seconds
Started Jul 01 12:23:41 PM PDT 24
Finished Jul 01 12:36:30 PM PDT 24
Peak memory 298672 kb
Host smart-fbfb44a3-3a0b-4487-9811-fe98af782c15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1832284446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1832284446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.2225499894
Short name T246
Test name
Test status
Simulation time 1376237284 ps
CPU time 5.82 seconds
Started Jul 01 12:23:36 PM PDT 24
Finished Jul 01 12:23:43 PM PDT 24
Peak memory 218148 kb
Host smart-853a42d3-4375-4b9d-b5fc-01aab1b1c195
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225499894 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.2225499894 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.4259396134
Short name T945
Test name
Test status
Simulation time 902133168 ps
CPU time 6.23 seconds
Started Jul 01 12:23:41 PM PDT 24
Finished Jul 01 12:23:48 PM PDT 24
Peak memory 219096 kb
Host smart-0f0cd844-63fe-4e26-85cd-2780e8089ab9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259396134 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.4259396134 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.2992828589
Short name T279
Test name
Test status
Simulation time 80402823326 ps
CPU time 1858.73 seconds
Started Jul 01 12:23:30 PM PDT 24
Finished Jul 01 12:54:29 PM PDT 24
Peak memory 391528 kb
Host smart-7788942d-bb50-478d-891d-beb875c9d476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2992828589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.2992828589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.1125924375
Short name T613
Test name
Test status
Simulation time 41676191432 ps
CPU time 1898.6 seconds
Started Jul 01 12:23:35 PM PDT 24
Finished Jul 01 12:55:14 PM PDT 24
Peak memory 384624 kb
Host smart-4a7ea571-6234-43c1-93e3-1de20fad7623
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1125924375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.1125924375 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.2536896795
Short name T820
Test name
Test status
Simulation time 72413061985 ps
CPU time 1835.27 seconds
Started Jul 01 12:23:38 PM PDT 24
Finished Jul 01 12:54:14 PM PDT 24
Peak memory 339108 kb
Host smart-1b2b4b55-5ece-4457-88b9-f0828fc9e9c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2536896795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2536896795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.1080798105
Short name T94
Test name
Test status
Simulation time 20916109041 ps
CPU time 1155.56 seconds
Started Jul 01 12:23:35 PM PDT 24
Finished Jul 01 12:42:51 PM PDT 24
Peak memory 299056 kb
Host smart-3e345a41-b0d5-4e21-9018-983ef09db0d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1080798105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.1080798105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.1121947199
Short name T269
Test name
Test status
Simulation time 59387977736 ps
CPU time 5316.52 seconds
Started Jul 01 12:23:35 PM PDT 24
Finished Jul 01 01:52:13 PM PDT 24
Peak memory 638172 kb
Host smart-4eccc72a-7fdd-4dfb-a4e6-8d25132332c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1121947199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.1121947199 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.2819493127
Short name T260
Test name
Test status
Simulation time 62693095507 ps
CPU time 4514.43 seconds
Started Jul 01 12:23:36 PM PDT 24
Finished Jul 01 01:38:52 PM PDT 24
Peak memory 577004 kb
Host smart-f0780c80-9d52-40ef-a4ad-1a863cda84e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2819493127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2819493127 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.1160307668
Short name T828
Test name
Test status
Simulation time 155149933 ps
CPU time 0.86 seconds
Started Jul 01 12:24:10 PM PDT 24
Finished Jul 01 12:24:11 PM PDT 24
Peak memory 217928 kb
Host smart-68c98e28-8b0b-469d-a90c-0de2ca936028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160307668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1160307668 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.2448485467
Short name T946
Test name
Test status
Simulation time 34286701697 ps
CPU time 203.04 seconds
Started Jul 01 12:24:05 PM PDT 24
Finished Jul 01 12:27:28 PM PDT 24
Peak memory 243020 kb
Host smart-8bf31276-abe7-4ab9-8722-0189cb1c86b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448485467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2448485467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.4167104689
Short name T566
Test name
Test status
Simulation time 12882227360 ps
CPU time 258.16 seconds
Started Jul 01 12:23:52 PM PDT 24
Finished Jul 01 12:28:11 PM PDT 24
Peak memory 242656 kb
Host smart-a8b3d2a7-8298-44d6-bc8e-20a1d114a77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167104689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.4167104689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.3609745127
Short name T52
Test name
Test status
Simulation time 17418490018 ps
CPU time 417.75 seconds
Started Jul 01 12:24:04 PM PDT 24
Finished Jul 01 12:31:02 PM PDT 24
Peak memory 253960 kb
Host smart-3c2cc877-ab0a-459a-bf42-3316358933c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609745127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3609745127 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.2045534398
Short name T440
Test name
Test status
Simulation time 24976581749 ps
CPU time 409.04 seconds
Started Jul 01 12:24:05 PM PDT 24
Finished Jul 01 12:30:54 PM PDT 24
Peak memory 263688 kb
Host smart-465f6967-e3d2-49ec-bf04-eac44bcf6d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045534398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2045534398 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.3873043030
Short name T995
Test name
Test status
Simulation time 1739194809 ps
CPU time 7.04 seconds
Started Jul 01 12:24:07 PM PDT 24
Finished Jul 01 12:24:15 PM PDT 24
Peak memory 218300 kb
Host smart-70189f9a-434d-4ca5-baba-a8078cd5881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873043030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3873043030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.1054190050
Short name T757
Test name
Test status
Simulation time 81898673 ps
CPU time 1.37 seconds
Started Jul 01 12:24:09 PM PDT 24
Finished Jul 01 12:24:11 PM PDT 24
Peak memory 219096 kb
Host smart-6bb2160b-513a-4678-9ee1-64e398bc7b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054190050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1054190050 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.1024083442
Short name T596
Test name
Test status
Simulation time 10764399157 ps
CPU time 217.54 seconds
Started Jul 01 12:23:48 PM PDT 24
Finished Jul 01 12:27:27 PM PDT 24
Peak memory 242748 kb
Host smart-f55a61ea-34f2-49a9-8640-302fc20b1d34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024083442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.1024083442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.2060488453
Short name T974
Test name
Test status
Simulation time 21152462466 ps
CPU time 326.16 seconds
Started Jul 01 12:23:54 PM PDT 24
Finished Jul 01 12:29:21 PM PDT 24
Peak memory 247944 kb
Host smart-f9090807-11f3-498b-b6cd-ac137b83355d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060488453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.2060488453 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.4159232647
Short name T936
Test name
Test status
Simulation time 1343004836 ps
CPU time 9.58 seconds
Started Jul 01 12:23:50 PM PDT 24
Finished Jul 01 12:23:59 PM PDT 24
Peak memory 226196 kb
Host smart-9515411f-c80a-47ca-a7a2-c5159ec3a843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159232647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.4159232647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.2606290968
Short name T964
Test name
Test status
Simulation time 21856670741 ps
CPU time 515.15 seconds
Started Jul 01 12:24:09 PM PDT 24
Finished Jul 01 12:32:45 PM PDT 24
Peak memory 259180 kb
Host smart-4168f491-a253-4742-adc3-a8101538b0f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2606290968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2606290968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.800723798
Short name T1023
Test name
Test status
Simulation time 421531539 ps
CPU time 6.55 seconds
Started Jul 01 12:24:05 PM PDT 24
Finished Jul 01 12:24:12 PM PDT 24
Peak memory 219092 kb
Host smart-eb67c26b-158d-410a-981c-50cd58a8fe80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800723798 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.kmac_test_vectors_kmac.800723798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.2817398717
Short name T581
Test name
Test status
Simulation time 734304224 ps
CPU time 6.72 seconds
Started Jul 01 12:24:04 PM PDT 24
Finished Jul 01 12:24:12 PM PDT 24
Peak memory 219140 kb
Host smart-ab85b218-477c-4c65-a960-92982f463bfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817398717 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.2817398717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.2607306180
Short name T965
Test name
Test status
Simulation time 65660586266 ps
CPU time 2203.46 seconds
Started Jul 01 12:23:53 PM PDT 24
Finished Jul 01 01:00:37 PM PDT 24
Peak memory 390472 kb
Host smart-d251667d-da30-4199-93c7-2b6a89e37e28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2607306180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.2607306180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.2104579662
Short name T803
Test name
Test status
Simulation time 22380078627 ps
CPU time 1963 seconds
Started Jul 01 12:23:53 PM PDT 24
Finished Jul 01 12:56:37 PM PDT 24
Peak memory 391960 kb
Host smart-2b46ccfc-1599-471b-b879-5e4160985666
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2104579662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.2104579662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.3971383981
Short name T117
Test name
Test status
Simulation time 70847522996 ps
CPU time 1843.99 seconds
Started Jul 01 12:24:00 PM PDT 24
Finished Jul 01 12:54:45 PM PDT 24
Peak memory 342412 kb
Host smart-34bc03ba-4864-45bb-824d-18e5d595af9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3971383981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.3971383981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.3442153944
Short name T842
Test name
Test status
Simulation time 11212561739 ps
CPU time 1260.37 seconds
Started Jul 01 12:24:00 PM PDT 24
Finished Jul 01 12:45:01 PM PDT 24
Peak memory 303764 kb
Host smart-84bae4d9-6e54-44c7-9f86-3eb5f63e0181
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3442153944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.3442153944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.1160148890
Short name T934
Test name
Test status
Simulation time 1157885664123 ps
CPU time 6218.34 seconds
Started Jul 01 12:24:00 PM PDT 24
Finished Jul 01 02:07:40 PM PDT 24
Peak memory 641528 kb
Host smart-b49d4227-70c7-456a-ad81-6e55100f781b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1160148890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.1160148890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.1065995617
Short name T214
Test name
Test status
Simulation time 218658145741 ps
CPU time 5492.16 seconds
Started Jul 01 12:24:03 PM PDT 24
Finished Jul 01 01:55:37 PM PDT 24
Peak memory 574484 kb
Host smart-57c00205-3ecb-47e4-b219-994b307f67fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1065995617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.1065995617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.1629113042
Short name T111
Test name
Test status
Simulation time 27689023 ps
CPU time 0.83 seconds
Started Jul 01 12:24:48 PM PDT 24
Finished Jul 01 12:24:50 PM PDT 24
Peak memory 217824 kb
Host smart-b13e50cf-dd94-4930-b968-4a1c9a12222a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629113042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1629113042 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.3394329027
Short name T486
Test name
Test status
Simulation time 14223336161 ps
CPU time 205.69 seconds
Started Jul 01 12:24:38 PM PDT 24
Finished Jul 01 12:28:04 PM PDT 24
Peak memory 241600 kb
Host smart-8a51d9a2-9e8f-4958-9eef-aea5e87b2f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394329027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3394329027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.1657796805
Short name T716
Test name
Test status
Simulation time 25834265415 ps
CPU time 1273.45 seconds
Started Jul 01 12:24:19 PM PDT 24
Finished Jul 01 12:45:34 PM PDT 24
Peak memory 238108 kb
Host smart-020132b9-5478-4a5e-9f94-d915ec662051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657796805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1657796805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.2905140518
Short name T910
Test name
Test status
Simulation time 1116275961 ps
CPU time 13.19 seconds
Started Jul 01 12:24:41 PM PDT 24
Finished Jul 01 12:24:55 PM PDT 24
Peak memory 226088 kb
Host smart-81c01b71-026d-42a0-b4ab-b4ad2c94fe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905140518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2905140518 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.3957584193
Short name T990
Test name
Test status
Simulation time 4909945186 ps
CPU time 98.12 seconds
Started Jul 01 12:24:48 PM PDT 24
Finished Jul 01 12:26:27 PM PDT 24
Peak memory 242692 kb
Host smart-be864903-6e96-4cba-903c-4ad97683ed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957584193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.3957584193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.17986699
Short name T312
Test name
Test status
Simulation time 650594208 ps
CPU time 5.33 seconds
Started Jul 01 12:24:47 PM PDT 24
Finished Jul 01 12:24:53 PM PDT 24
Peak memory 218108 kb
Host smart-a25ae581-e2ee-404c-8767-48b093c1dc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17986699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.17986699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.3089991883
Short name T663
Test name
Test status
Simulation time 106984970 ps
CPU time 1.29 seconds
Started Jul 01 12:24:47 PM PDT 24
Finished Jul 01 12:24:49 PM PDT 24
Peak memory 219160 kb
Host smart-7e311d1b-bd6e-4cee-84ec-09da539a9c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089991883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3089991883 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.3804383372
Short name T963
Test name
Test status
Simulation time 348022004979 ps
CPU time 1374.62 seconds
Started Jul 01 12:24:20 PM PDT 24
Finished Jul 01 12:47:16 PM PDT 24
Peak memory 314488 kb
Host smart-7d8b825a-10df-4899-aaf2-9da5a73bc9cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804383372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.3804383372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.3917079867
Short name T389
Test name
Test status
Simulation time 11834533915 ps
CPU time 353.25 seconds
Started Jul 01 12:24:19 PM PDT 24
Finished Jul 01 12:30:13 PM PDT 24
Peak memory 250180 kb
Host smart-f4502d20-1b72-4e34-baf0-4e1a8a154785
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917079867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.3917079867 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.407995113
Short name T537
Test name
Test status
Simulation time 971348348 ps
CPU time 12.01 seconds
Started Jul 01 12:24:15 PM PDT 24
Finished Jul 01 12:24:28 PM PDT 24
Peak memory 219144 kb
Host smart-bd9686ea-3db8-4b87-8aa5-9167e06a299d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407995113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.407995113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.1008388273
Short name T1048
Test name
Test status
Simulation time 10249114776 ps
CPU time 246.58 seconds
Started Jul 01 12:24:50 PM PDT 24
Finished Jul 01 12:28:57 PM PDT 24
Peak memory 242688 kb
Host smart-49d71a63-8319-48f0-8ad4-caeacd241999
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1008388273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.1008388273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.4100100185
Short name T435
Test name
Test status
Simulation time 1000474336 ps
CPU time 6.9 seconds
Started Jul 01 12:24:38 PM PDT 24
Finished Jul 01 12:24:45 PM PDT 24
Peak memory 218140 kb
Host smart-3e06602e-3cac-436c-9590-126beab18ac1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100100185 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.4100100185 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.3653933260
Short name T805
Test name
Test status
Simulation time 2380414699 ps
CPU time 6.26 seconds
Started Jul 01 12:24:35 PM PDT 24
Finished Jul 01 12:24:42 PM PDT 24
Peak memory 218428 kb
Host smart-9ecb62e9-a66b-46c1-b0a2-c989f99feb41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653933260 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.3653933260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.936142015
Short name T358
Test name
Test status
Simulation time 480300019273 ps
CPU time 2627.33 seconds
Started Jul 01 12:24:20 PM PDT 24
Finished Jul 01 01:08:08 PM PDT 24
Peak memory 391676 kb
Host smart-de67ded6-5997-4de1-94e0-1c9a7c6585fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=936142015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.936142015 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.3787993519
Short name T502
Test name
Test status
Simulation time 781322741731 ps
CPU time 2097.21 seconds
Started Jul 01 12:24:24 PM PDT 24
Finished Jul 01 12:59:22 PM PDT 24
Peak memory 390164 kb
Host smart-08317c92-7dd0-448e-8618-3320b3abda2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3787993519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3787993519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.329209010
Short name T1003
Test name
Test status
Simulation time 154461599916 ps
CPU time 1744.3 seconds
Started Jul 01 12:24:24 PM PDT 24
Finished Jul 01 12:53:29 PM PDT 24
Peak memory 337572 kb
Host smart-97dbc166-44cf-48fa-aca7-1179e3cdeb15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=329209010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.329209010 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.4266211469
Short name T973
Test name
Test status
Simulation time 50522589600 ps
CPU time 1376.94 seconds
Started Jul 01 12:24:31 PM PDT 24
Finished Jul 01 12:47:29 PM PDT 24
Peak memory 305088 kb
Host smart-44c75a10-bbd6-49eb-b46c-d7c7a277f908
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4266211469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.4266211469 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.596700279
Short name T396
Test name
Test status
Simulation time 263633876625 ps
CPU time 6414.02 seconds
Started Jul 01 12:24:30 PM PDT 24
Finished Jul 01 02:11:26 PM PDT 24
Peak memory 652776 kb
Host smart-3abb79ce-21b5-4e89-8b0d-264d0db62511
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=596700279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.596700279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.1206587333
Short name T252
Test name
Test status
Simulation time 1369351669003 ps
CPU time 5050.08 seconds
Started Jul 01 12:24:31 PM PDT 24
Finished Jul 01 01:48:42 PM PDT 24
Peak memory 567020 kb
Host smart-fbd47fd0-fd50-49f7-92eb-36b335ba0b0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1206587333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.1206587333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.676589569
Short name T773
Test name
Test status
Simulation time 147987150 ps
CPU time 0.89 seconds
Started Jul 01 12:25:15 PM PDT 24
Finished Jul 01 12:25:16 PM PDT 24
Peak memory 217932 kb
Host smart-119c388c-cdf8-4fcb-bec6-a1fbf7867979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676589569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.676589569 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.1688694263
Short name T703
Test name
Test status
Simulation time 9990636858 ps
CPU time 80.03 seconds
Started Jul 01 12:25:10 PM PDT 24
Finished Jul 01 12:26:31 PM PDT 24
Peak memory 231244 kb
Host smart-0c27e011-fc3c-44f4-b010-81a3fb7bffe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688694263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1688694263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.1081203131
Short name T296
Test name
Test status
Simulation time 56656797401 ps
CPU time 1125.81 seconds
Started Jul 01 12:24:51 PM PDT 24
Finished Jul 01 12:43:38 PM PDT 24
Peak memory 237648 kb
Host smart-b0a62c02-b76d-4bb1-98fc-3304bf0112fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081203131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1081203131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.3822310601
Short name T57
Test name
Test status
Simulation time 16701774733 ps
CPU time 175.77 seconds
Started Jul 01 12:25:11 PM PDT 24
Finished Jul 01 12:28:08 PM PDT 24
Peak memory 240100 kb
Host smart-fabfb457-d6b8-43be-85f7-72d34e6d9826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822310601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3822310601 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.537152337
Short name T516
Test name
Test status
Simulation time 8004175798 ps
CPU time 195.22 seconds
Started Jul 01 12:25:10 PM PDT 24
Finished Jul 01 12:28:27 PM PDT 24
Peak memory 250976 kb
Host smart-e8ff0d72-d98e-4573-af48-ce4fd07c2e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537152337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.537152337 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.1291171478
Short name T927
Test name
Test status
Simulation time 1500536403 ps
CPU time 11.94 seconds
Started Jul 01 12:25:11 PM PDT 24
Finished Jul 01 12:25:23 PM PDT 24
Peak memory 218192 kb
Host smart-30883b5a-ffeb-4842-8715-fc5973e3a3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291171478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1291171478 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.4283325917
Short name T751
Test name
Test status
Simulation time 185312669 ps
CPU time 1.61 seconds
Started Jul 01 12:25:10 PM PDT 24
Finished Jul 01 12:25:13 PM PDT 24
Peak memory 218212 kb
Host smart-6a03c606-a09f-4ea1-aaf3-7a688542a038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283325917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.4283325917 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.1066902268
Short name T499
Test name
Test status
Simulation time 51375371881 ps
CPU time 474.63 seconds
Started Jul 01 12:24:52 PM PDT 24
Finished Jul 01 12:32:47 PM PDT 24
Peak memory 260192 kb
Host smart-dc9490c8-1344-44b2-a89b-96cdffd1fe84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066902268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.1066902268 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.3664691456
Short name T968
Test name
Test status
Simulation time 20050506150 ps
CPU time 135.12 seconds
Started Jul 01 12:24:53 PM PDT 24
Finished Jul 01 12:27:08 PM PDT 24
Peak memory 234560 kb
Host smart-2a5cf35c-4dc4-493b-b302-6bb53e857079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664691456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3664691456 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.2508173486
Short name T837
Test name
Test status
Simulation time 14880732536 ps
CPU time 80.57 seconds
Started Jul 01 12:24:51 PM PDT 24
Finished Jul 01 12:26:12 PM PDT 24
Peak memory 226136 kb
Host smart-b1ff72c9-97cd-4a23-a6d2-6d8e18227811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508173486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2508173486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.1708200693
Short name T931
Test name
Test status
Simulation time 52465212013 ps
CPU time 494.27 seconds
Started Jul 01 12:25:16 PM PDT 24
Finished Jul 01 12:33:31 PM PDT 24
Peak memory 259484 kb
Host smart-011dace9-74f3-45ee-bcd9-739eebc2c428
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1708200693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1708200693 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.1707303675
Short name T914
Test name
Test status
Simulation time 999989510 ps
CPU time 6.57 seconds
Started Jul 01 12:25:04 PM PDT 24
Finished Jul 01 12:25:11 PM PDT 24
Peak memory 218108 kb
Host smart-5f2b1510-7e08-47d4-b071-061782da74db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707303675 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.1707303675 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.3766908028
Short name T320
Test name
Test status
Simulation time 1255155028 ps
CPU time 6.68 seconds
Started Jul 01 12:25:05 PM PDT 24
Finished Jul 01 12:25:13 PM PDT 24
Peak memory 218212 kb
Host smart-8d4c3f7d-777e-4f23-bd7d-38c6f758f3e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766908028 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.3766908028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.984576036
Short name T809
Test name
Test status
Simulation time 88099416132 ps
CPU time 2096.22 seconds
Started Jul 01 12:24:59 PM PDT 24
Finished Jul 01 12:59:57 PM PDT 24
Peak memory 395556 kb
Host smart-9490c50a-5eb4-4efc-a1cb-7126e4e507ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=984576036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.984576036 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.745267048
Short name T492
Test name
Test status
Simulation time 77588946219 ps
CPU time 2027.75 seconds
Started Jul 01 12:25:03 PM PDT 24
Finished Jul 01 12:58:51 PM PDT 24
Peak memory 376676 kb
Host smart-5e10e24e-06c4-4004-b8d9-b344a7c6e44c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=745267048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.745267048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.3854947196
Short name T483
Test name
Test status
Simulation time 588230276891 ps
CPU time 1787.37 seconds
Started Jul 01 12:24:59 PM PDT 24
Finished Jul 01 12:54:47 PM PDT 24
Peak memory 341692 kb
Host smart-fe899fba-6f4d-4bf9-b1f9-8eeae06af0c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3854947196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.3854947196 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.1994400627
Short name T503
Test name
Test status
Simulation time 53419540391 ps
CPU time 1258.97 seconds
Started Jul 01 12:25:05 PM PDT 24
Finished Jul 01 12:46:05 PM PDT 24
Peak memory 307084 kb
Host smart-05e0134b-3336-48d2-af44-84bfd3c2eef1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1994400627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.1994400627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.3294591254
Short name T391
Test name
Test status
Simulation time 226590636864 ps
CPU time 5742.43 seconds
Started Jul 01 12:25:04 PM PDT 24
Finished Jul 01 02:00:48 PM PDT 24
Peak memory 651596 kb
Host smart-5e8271a3-774c-4d30-915c-4d30af4d9559
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3294591254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.3294591254 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.1904703873
Short name T393
Test name
Test status
Simulation time 221116266107 ps
CPU time 5255.75 seconds
Started Jul 01 12:25:03 PM PDT 24
Finished Jul 01 01:52:40 PM PDT 24
Peak memory 578712 kb
Host smart-7c47718f-a81a-4ce5-a193-42b067e90bf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1904703873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.1904703873 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.3716742391
Short name T937
Test name
Test status
Simulation time 25470692 ps
CPU time 0.86 seconds
Started Jul 01 12:25:49 PM PDT 24
Finished Jul 01 12:25:50 PM PDT 24
Peak memory 217864 kb
Host smart-57709829-a8a1-41a4-8fdf-0e8c0a85ad40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716742391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.3716742391 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.606173016
Short name T866
Test name
Test status
Simulation time 67224463782 ps
CPU time 168.42 seconds
Started Jul 01 12:25:42 PM PDT 24
Finished Jul 01 12:28:31 PM PDT 24
Peak memory 238108 kb
Host smart-24ee19b9-f8ba-41c9-a83e-f702058a0080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606173016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.606173016 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.2905405886
Short name T450
Test name
Test status
Simulation time 7750995076 ps
CPU time 157.96 seconds
Started Jul 01 12:25:26 PM PDT 24
Finished Jul 01 12:28:05 PM PDT 24
Peak memory 227124 kb
Host smart-1343775d-3a32-4a95-a6aa-3b844ccad485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905405886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2905405886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1469918995
Short name T409
Test name
Test status
Simulation time 19505659063 ps
CPU time 421.16 seconds
Started Jul 01 12:25:36 PM PDT 24
Finished Jul 01 12:32:38 PM PDT 24
Peak memory 252812 kb
Host smart-838fd382-c91d-4f50-b370-8a20c6d60491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469918995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1469918995 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.2208014999
Short name T994
Test name
Test status
Simulation time 4955517781 ps
CPU time 330.74 seconds
Started Jul 01 12:25:48 PM PDT 24
Finished Jul 01 12:31:19 PM PDT 24
Peak memory 259048 kb
Host smart-2e70d74f-a3bc-498b-8250-ef2557edd236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208014999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2208014999 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.416697552
Short name T6
Test name
Test status
Simulation time 3026984792 ps
CPU time 10.86 seconds
Started Jul 01 12:25:49 PM PDT 24
Finished Jul 01 12:26:00 PM PDT 24
Peak memory 218212 kb
Host smart-1ac21b0d-1627-4d7a-9ed6-896a8358a6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416697552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.416697552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.1365261991
Short name T77
Test name
Test status
Simulation time 34525770 ps
CPU time 1.29 seconds
Started Jul 01 12:25:50 PM PDT 24
Finished Jul 01 12:25:51 PM PDT 24
Peak memory 218156 kb
Host smart-7f8c770e-31bf-494f-8d13-90c9e8992511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365261991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1365261991 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.3804082314
Short name T329
Test name
Test status
Simulation time 54508718152 ps
CPU time 354.12 seconds
Started Jul 01 12:25:14 PM PDT 24
Finished Jul 01 12:31:09 PM PDT 24
Peak memory 253460 kb
Host smart-79cf6bc9-4217-45e3-8d07-3dce35606049
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804082314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.3804082314 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.2789174852
Short name T704
Test name
Test status
Simulation time 4577244146 ps
CPU time 207.45 seconds
Started Jul 01 12:25:19 PM PDT 24
Finished Jul 01 12:28:47 PM PDT 24
Peak memory 237568 kb
Host smart-4fc2a800-ca20-426d-a48b-ea05fe2962e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789174852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2789174852 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.4279119394
Short name T264
Test name
Test status
Simulation time 2918975420 ps
CPU time 30.87 seconds
Started Jul 01 12:25:16 PM PDT 24
Finished Jul 01 12:25:47 PM PDT 24
Peak memory 224472 kb
Host smart-ff4ec7fc-4060-47a3-9c5f-a55861fb9268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279119394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.4279119394 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.1528069885
Short name T56
Test name
Test status
Simulation time 20324824425 ps
CPU time 1450.29 seconds
Started Jul 01 12:25:50 PM PDT 24
Finished Jul 01 12:50:01 PM PDT 24
Peak memory 381316 kb
Host smart-a6b7f54a-c6c1-485a-85ee-fc728fcadcc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1528069885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1528069885 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.2204387794
Short name T158
Test name
Test status
Simulation time 301884928 ps
CPU time 6.45 seconds
Started Jul 01 12:25:36 PM PDT 24
Finished Jul 01 12:25:43 PM PDT 24
Peak memory 218072 kb
Host smart-0deb557b-f3a4-43b7-a520-ffa7c5068ab3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204387794 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.2204387794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.2567822064
Short name T592
Test name
Test status
Simulation time 296523101 ps
CPU time 6.51 seconds
Started Jul 01 12:25:36 PM PDT 24
Finished Jul 01 12:25:43 PM PDT 24
Peak memory 218148 kb
Host smart-bb643168-078c-4b6e-90e6-c2aefca07348
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567822064 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.2567822064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.2585280469
Short name T275
Test name
Test status
Simulation time 21836847670 ps
CPU time 1828.82 seconds
Started Jul 01 12:25:27 PM PDT 24
Finished Jul 01 12:55:57 PM PDT 24
Peak memory 388560 kb
Host smart-ac50da43-72a9-4ab6-bb72-840d371f8e90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2585280469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2585280469 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.3400119966
Short name T367
Test name
Test status
Simulation time 218682503061 ps
CPU time 1903.6 seconds
Started Jul 01 12:25:26 PM PDT 24
Finished Jul 01 12:57:10 PM PDT 24
Peak memory 379052 kb
Host smart-31e25015-571d-4098-8cb5-8ee58143c127
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3400119966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.3400119966 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.386254540
Short name T695
Test name
Test status
Simulation time 194522905148 ps
CPU time 1673.39 seconds
Started Jul 01 12:25:26 PM PDT 24
Finished Jul 01 12:53:20 PM PDT 24
Peak memory 334940 kb
Host smart-9f08bbb4-fc83-48f3-aeaa-3546be5aa76c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=386254540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.386254540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.1880489329
Short name T564
Test name
Test status
Simulation time 679262910608 ps
CPU time 5335.75 seconds
Started Jul 01 12:25:33 PM PDT 24
Finished Jul 01 01:54:29 PM PDT 24
Peak memory 628108 kb
Host smart-65700cc4-39a2-4f43-9478-0b7e74a5b6d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1880489329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.1880489329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.1281665536
Short name T961
Test name
Test status
Simulation time 200641861662 ps
CPU time 4422.58 seconds
Started Jul 01 12:25:33 PM PDT 24
Finished Jul 01 01:39:17 PM PDT 24
Peak memory 570536 kb
Host smart-2a962c0b-c44c-4541-b244-01fdad17ca2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1281665536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.1281665536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.1220037804
Short name T766
Test name
Test status
Simulation time 43960791 ps
CPU time 0.81 seconds
Started Jul 01 12:26:23 PM PDT 24
Finished Jul 01 12:26:24 PM PDT 24
Peak memory 217812 kb
Host smart-bf688416-1d91-4346-8d13-013219b9f7d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220037804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1220037804 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.1117399487
Short name T257
Test name
Test status
Simulation time 6987961907 ps
CPU time 102.14 seconds
Started Jul 01 12:26:15 PM PDT 24
Finished Jul 01 12:27:58 PM PDT 24
Peak memory 231520 kb
Host smart-7ea4fd9f-b2de-4943-a751-d2b6aa4b22ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117399487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1117399487 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.279658696
Short name T734
Test name
Test status
Simulation time 2436998924 ps
CPU time 60.28 seconds
Started Jul 01 12:25:53 PM PDT 24
Finished Jul 01 12:26:54 PM PDT 24
Peak memory 224180 kb
Host smart-c73cb488-455a-46b1-aac4-287bcdaae778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279658696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.279658696 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.1891165226
Short name T852
Test name
Test status
Simulation time 7240832307 ps
CPU time 50.92 seconds
Started Jul 01 12:26:14 PM PDT 24
Finished Jul 01 12:27:05 PM PDT 24
Peak memory 236564 kb
Host smart-6cacad42-a41a-400c-8b3a-ee587203d916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891165226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1891165226 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.4069794373
Short name T74
Test name
Test status
Simulation time 1531163224 ps
CPU time 32.34 seconds
Started Jul 01 12:26:16 PM PDT 24
Finished Jul 01 12:26:48 PM PDT 24
Peak memory 233272 kb
Host smart-db39a947-7f74-4378-a2d8-2f4a4620318d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069794373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.4069794373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.2827617564
Short name T305
Test name
Test status
Simulation time 3274521248 ps
CPU time 7.86 seconds
Started Jul 01 12:26:22 PM PDT 24
Finished Jul 01 12:26:31 PM PDT 24
Peak memory 218188 kb
Host smart-c68efddf-6ad5-4ac6-a6ed-09714dec01c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827617564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2827617564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.2466220426
Short name T89
Test name
Test status
Simulation time 185425726 ps
CPU time 1.43 seconds
Started Jul 01 12:26:22 PM PDT 24
Finished Jul 01 12:26:24 PM PDT 24
Peak memory 218212 kb
Host smart-1aeb3fb8-fa25-4690-81bd-0eeec90a2faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466220426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2466220426 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.1631997021
Short name T463
Test name
Test status
Simulation time 7071123752 ps
CPU time 373.86 seconds
Started Jul 01 12:25:52 PM PDT 24
Finished Jul 01 12:32:06 PM PDT 24
Peak memory 253456 kb
Host smart-fc1e9d2c-45bb-4a85-8be9-5d74e0f2af6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631997021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.1631997021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.619634989
Short name T554
Test name
Test status
Simulation time 10439454940 ps
CPU time 355.13 seconds
Started Jul 01 12:25:53 PM PDT 24
Finished Jul 01 12:31:48 PM PDT 24
Peak memory 248592 kb
Host smart-9a6a7817-8cb1-4bf5-9bca-ec88396e7af5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619634989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.619634989 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.1910803060
Short name T384
Test name
Test status
Simulation time 4202715244 ps
CPU time 50.42 seconds
Started Jul 01 12:25:53 PM PDT 24
Finished Jul 01 12:26:43 PM PDT 24
Peak memory 226380 kb
Host smart-9e424107-5a7e-4d38-8823-7861d7cb2497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910803060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1910803060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.603576736
Short name T546
Test name
Test status
Simulation time 49025475440 ps
CPU time 1747.58 seconds
Started Jul 01 12:26:23 PM PDT 24
Finished Jul 01 12:55:31 PM PDT 24
Peak memory 381060 kb
Host smart-96ee0242-6ce5-4cb8-a7b7-32ec9d980b71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=603576736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.603576736 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.93739135
Short name T348
Test name
Test status
Simulation time 558304998 ps
CPU time 7.05 seconds
Started Jul 01 12:26:18 PM PDT 24
Finished Jul 01 12:26:25 PM PDT 24
Peak memory 219092 kb
Host smart-eab7f614-3a67-4db6-af50-8c2503bc75e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93739135 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.kmac_test_vectors_kmac.93739135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.3580140930
Short name T453
Test name
Test status
Simulation time 262295083 ps
CPU time 6.72 seconds
Started Jul 01 12:26:18 PM PDT 24
Finished Jul 01 12:26:25 PM PDT 24
Peak memory 219088 kb
Host smart-05a8d5c6-42d3-4164-a2a9-e85c50acff43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580140930 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.3580140930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.3949960253
Short name T688
Test name
Test status
Simulation time 430362782194 ps
CPU time 2335.02 seconds
Started Jul 01 12:25:59 PM PDT 24
Finished Jul 01 01:04:55 PM PDT 24
Peak memory 402972 kb
Host smart-e19afe03-e759-4155-9dc8-9c3c186779a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3949960253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.3949960253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.3370385446
Short name T874
Test name
Test status
Simulation time 129535265351 ps
CPU time 2070.99 seconds
Started Jul 01 12:25:59 PM PDT 24
Finished Jul 01 01:00:31 PM PDT 24
Peak memory 387712 kb
Host smart-4a656af6-5025-49d6-b48c-9277c1a9276b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3370385446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.3370385446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.4273570526
Short name T1043
Test name
Test status
Simulation time 22121425746 ps
CPU time 1508.8 seconds
Started Jul 01 12:26:04 PM PDT 24
Finished Jul 01 12:51:14 PM PDT 24
Peak memory 343580 kb
Host smart-51a19351-146c-492b-a49e-0796e583e087
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4273570526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.4273570526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.1236980675
Short name T259
Test name
Test status
Simulation time 221088208858 ps
CPU time 1359.93 seconds
Started Jul 01 12:26:04 PM PDT 24
Finished Jul 01 12:48:44 PM PDT 24
Peak memory 298776 kb
Host smart-e55c4068-c769-4c7c-90bf-385307ee1889
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1236980675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.1236980675 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.783684091
Short name T388
Test name
Test status
Simulation time 353643729361 ps
CPU time 6205.33 seconds
Started Jul 01 12:26:04 PM PDT 24
Finished Jul 01 02:09:31 PM PDT 24
Peak memory 649360 kb
Host smart-a5502131-6af6-42d9-945f-f6a38321496f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=783684091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.783684091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.4281024625
Short name T428
Test name
Test status
Simulation time 1142529388119 ps
CPU time 5481.09 seconds
Started Jul 01 12:26:10 PM PDT 24
Finished Jul 01 01:57:32 PM PDT 24
Peak memory 562744 kb
Host smart-e857b778-0768-4345-bd42-6f78cec2076b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4281024625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.4281024625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.2051473441
Short name T646
Test name
Test status
Simulation time 39208814 ps
CPU time 0.77 seconds
Started Jul 01 12:26:52 PM PDT 24
Finished Jul 01 12:26:53 PM PDT 24
Peak memory 217940 kb
Host smart-abf27aa1-8798-44a7-84db-4c9a8c7112a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051473441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2051473441 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.718896740
Short name T289
Test name
Test status
Simulation time 52672571743 ps
CPU time 273.91 seconds
Started Jul 01 12:26:41 PM PDT 24
Finished Jul 01 12:31:15 PM PDT 24
Peak memory 244316 kb
Host smart-cffba8cb-1d6f-46ad-a2b9-0ffc0312905a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718896740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.718896740 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.3246863567
Short name T894
Test name
Test status
Simulation time 66032484386 ps
CPU time 834.14 seconds
Started Jul 01 12:26:28 PM PDT 24
Finished Jul 01 12:40:23 PM PDT 24
Peak memory 235572 kb
Host smart-4c014aef-2c8e-4bea-ac6e-d3bca6ba6d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246863567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3246863567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.1803079062
Short name T459
Test name
Test status
Simulation time 8953051783 ps
CPU time 245.79 seconds
Started Jul 01 12:26:42 PM PDT 24
Finished Jul 01 12:30:49 PM PDT 24
Peak memory 243304 kb
Host smart-e80a63cf-74f2-44ef-bbfe-1fb6343c68e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803079062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1803079062 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_key_error.4257998864
Short name T883
Test name
Test status
Simulation time 1149908285 ps
CPU time 9.96 seconds
Started Jul 01 12:26:46 PM PDT 24
Finished Jul 01 12:26:57 PM PDT 24
Peak memory 218132 kb
Host smart-75aa1e55-8541-4e01-bc07-adc95b6a3584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257998864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.4257998864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.1889712518
Short name T48
Test name
Test status
Simulation time 478629391 ps
CPU time 26.85 seconds
Started Jul 01 12:26:46 PM PDT 24
Finished Jul 01 12:27:14 PM PDT 24
Peak memory 234748 kb
Host smart-3acb1a08-e36d-4e15-8e2c-8a6b8156b6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889712518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1889712518 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.3321811702
Short name T426
Test name
Test status
Simulation time 2771295818 ps
CPU time 224.45 seconds
Started Jul 01 12:26:26 PM PDT 24
Finished Jul 01 12:30:11 PM PDT 24
Peak memory 242704 kb
Host smart-6f347a19-09e2-44a5-a7c1-14473b8cbddf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321811702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.3321811702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.4206061759
Short name T694
Test name
Test status
Simulation time 9423632059 ps
CPU time 233.27 seconds
Started Jul 01 12:26:26 PM PDT 24
Finished Jul 01 12:30:20 PM PDT 24
Peak memory 241504 kb
Host smart-dba7677a-080b-4ad5-982d-da0a737e365d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206061759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.4206061759 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.3903687157
Short name T145
Test name
Test status
Simulation time 2135844812 ps
CPU time 48.84 seconds
Started Jul 01 12:26:22 PM PDT 24
Finished Jul 01 12:27:12 PM PDT 24
Peak memory 218092 kb
Host smart-f3a24176-a5b4-4c39-a116-c4e4b275dba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903687157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3903687157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.1897668427
Short name T893
Test name
Test status
Simulation time 26725393619 ps
CPU time 998.79 seconds
Started Jul 01 12:26:53 PM PDT 24
Finished Jul 01 12:43:32 PM PDT 24
Peak memory 349516 kb
Host smart-91fe434e-a76b-408c-ae60-d5a5100cb498
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1897668427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1897668427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.1839579744
Short name T301
Test name
Test status
Simulation time 482486941 ps
CPU time 6.15 seconds
Started Jul 01 12:26:45 PM PDT 24
Finished Jul 01 12:26:52 PM PDT 24
Peak memory 219140 kb
Host smart-da8f1b57-816b-47a2-985e-31013ff52b27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839579744 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.1839579744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3332312081
Short name T857
Test name
Test status
Simulation time 321381838 ps
CPU time 6.44 seconds
Started Jul 01 12:26:46 PM PDT 24
Finished Jul 01 12:26:53 PM PDT 24
Peak memory 219084 kb
Host smart-fa9b3b24-26b6-42ee-8bf9-4fdfd2b8b918
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332312081 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3332312081 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.1884293181
Short name T958
Test name
Test status
Simulation time 41428254105 ps
CPU time 1977.96 seconds
Started Jul 01 12:26:31 PM PDT 24
Finished Jul 01 12:59:30 PM PDT 24
Peak memory 397352 kb
Host smart-69b04e77-6c23-41b8-827b-f0a40c9805b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1884293181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.1884293181 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.3198146834
Short name T798
Test name
Test status
Simulation time 75726254890 ps
CPU time 1916.61 seconds
Started Jul 01 12:26:37 PM PDT 24
Finished Jul 01 12:58:35 PM PDT 24
Peak memory 379664 kb
Host smart-2495a9cf-2cea-475a-b525-848400b8e82c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3198146834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.3198146834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.2885066222
Short name T405
Test name
Test status
Simulation time 28546836998 ps
CPU time 1449.37 seconds
Started Jul 01 12:26:40 PM PDT 24
Finished Jul 01 12:50:50 PM PDT 24
Peak memory 338184 kb
Host smart-d38edc61-ee6f-4261-b062-7067d86be7d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2885066222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.2885066222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.2607241620
Short name T265
Test name
Test status
Simulation time 10919864763 ps
CPU time 1141.69 seconds
Started Jul 01 12:26:36 PM PDT 24
Finished Jul 01 12:45:39 PM PDT 24
Peak memory 297616 kb
Host smart-0a16cc8b-6fd7-4bd2-b12a-6722563a2dcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2607241620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.2607241620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.3614928933
Short name T262
Test name
Test status
Simulation time 230241321462 ps
CPU time 6063.22 seconds
Started Jul 01 12:26:46 PM PDT 24
Finished Jul 01 02:07:51 PM PDT 24
Peak memory 653236 kb
Host smart-6112882e-3c5d-4972-9540-e095be03a2ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3614928933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.3614928933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.568239789
Short name T445
Test name
Test status
Simulation time 636323835636 ps
CPU time 5376.84 seconds
Started Jul 01 12:26:41 PM PDT 24
Finished Jul 01 01:56:20 PM PDT 24
Peak memory 581012 kb
Host smart-48baf9fd-3c02-4364-a928-f196047e48df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=568239789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.568239789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.3531259464
Short name T839
Test name
Test status
Simulation time 13347210 ps
CPU time 0.82 seconds
Started Jul 01 12:27:21 PM PDT 24
Finished Jul 01 12:27:22 PM PDT 24
Peak memory 217932 kb
Host smart-58582f82-c553-4792-bd30-b5af964631f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531259464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3531259464 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.3998435731
Short name T611
Test name
Test status
Simulation time 5676985564 ps
CPU time 149.8 seconds
Started Jul 01 12:27:11 PM PDT 24
Finished Jul 01 12:29:41 PM PDT 24
Peak memory 238220 kb
Host smart-d5398a6a-de12-4fb4-8204-b2dd5ca40379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998435731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3998435731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.3516034004
Short name T538
Test name
Test status
Simulation time 8583645790 ps
CPU time 162.85 seconds
Started Jul 01 12:27:14 PM PDT 24
Finished Jul 01 12:29:58 PM PDT 24
Peak memory 237680 kb
Host smart-45d75fb2-4a2c-47f4-bdd7-335b70da6afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516034004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3516034004 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.424456783
Short name T983
Test name
Test status
Simulation time 8014604222 ps
CPU time 206.6 seconds
Started Jul 01 12:27:15 PM PDT 24
Finished Jul 01 12:30:43 PM PDT 24
Peak memory 259096 kb
Host smart-f2da9a5b-8667-4e7e-b870-1711ac0d1842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424456783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.424456783 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.1831740079
Short name T807
Test name
Test status
Simulation time 6825827044 ps
CPU time 9.36 seconds
Started Jul 01 12:27:15 PM PDT 24
Finished Jul 01 12:27:25 PM PDT 24
Peak memory 218292 kb
Host smart-0076b8a8-0079-4527-ac59-d85eeef07559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831740079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1831740079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.3200115569
Short name T701
Test name
Test status
Simulation time 39279289 ps
CPU time 1.37 seconds
Started Jul 01 12:27:21 PM PDT 24
Finished Jul 01 12:27:23 PM PDT 24
Peak memory 219048 kb
Host smart-99ef2b32-431d-44f7-9f8f-8911fc1477e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200115569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3200115569 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.963671242
Short name T218
Test name
Test status
Simulation time 241210059977 ps
CPU time 2494.2 seconds
Started Jul 01 12:26:58 PM PDT 24
Finished Jul 01 01:08:33 PM PDT 24
Peak memory 430296 kb
Host smart-1130c7f4-468d-4f51-8426-21b046f1548e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963671242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_an
d_output.963671242 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.3303397241
Short name T517
Test name
Test status
Simulation time 12650530763 ps
CPU time 170.64 seconds
Started Jul 01 12:26:58 PM PDT 24
Finished Jul 01 12:29:49 PM PDT 24
Peak memory 236424 kb
Host smart-f9d62804-2200-4f14-8c30-d47fcd0e2258
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303397241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3303397241 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.1888425989
Short name T649
Test name
Test status
Simulation time 1350727096 ps
CPU time 27.08 seconds
Started Jul 01 12:27:01 PM PDT 24
Finished Jul 01 12:27:28 PM PDT 24
Peak memory 226072 kb
Host smart-6286b23d-14bd-4aed-a0f8-f595689d27a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888425989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.1888425989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.2835445669
Short name T697
Test name
Test status
Simulation time 63388723236 ps
CPU time 1193.69 seconds
Started Jul 01 12:27:20 PM PDT 24
Finished Jul 01 12:47:14 PM PDT 24
Peak memory 373084 kb
Host smart-2f4d632c-02c1-4255-bb32-48208b07a0c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2835445669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2835445669 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.19258698
Short name T744
Test name
Test status
Simulation time 383581554 ps
CPU time 6.15 seconds
Started Jul 01 12:27:04 PM PDT 24
Finished Jul 01 12:27:11 PM PDT 24
Peak memory 218168 kb
Host smart-02096db6-39bd-4308-8741-9f190dcf6b12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19258698 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.kmac_test_vectors_kmac.19258698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.2296037131
Short name T466
Test name
Test status
Simulation time 457038739 ps
CPU time 5.95 seconds
Started Jul 01 12:27:04 PM PDT 24
Finished Jul 01 12:27:11 PM PDT 24
Peak memory 219052 kb
Host smart-93edaed1-409f-456b-80cf-f2a2fa8191ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296037131 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.2296037131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.708446900
Short name T133
Test name
Test status
Simulation time 26732538149 ps
CPU time 1963.38 seconds
Started Jul 01 12:26:59 PM PDT 24
Finished Jul 01 12:59:43 PM PDT 24
Peak memory 397868 kb
Host smart-b81e7fba-6768-412c-bcd8-327346f6c907
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=708446900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.708446900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.149891632
Short name T1059
Test name
Test status
Simulation time 80705499316 ps
CPU time 2115.01 seconds
Started Jul 01 12:27:01 PM PDT 24
Finished Jul 01 01:02:16 PM PDT 24
Peak memory 387528 kb
Host smart-59a92c0b-7858-455b-b555-184bdde6b0b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=149891632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.149891632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.3435652797
Short name T672
Test name
Test status
Simulation time 62730485447 ps
CPU time 1486.22 seconds
Started Jul 01 12:27:04 PM PDT 24
Finished Jul 01 12:51:51 PM PDT 24
Peak memory 338768 kb
Host smart-51250924-80a8-47ee-9b60-97c31778d45a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3435652797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.3435652797 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.2200288863
Short name T662
Test name
Test status
Simulation time 175116601147 ps
CPU time 1236.66 seconds
Started Jul 01 12:27:05 PM PDT 24
Finished Jul 01 12:47:42 PM PDT 24
Peak memory 296712 kb
Host smart-2b5c28ed-5962-4c80-b820-717a43f14248
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2200288863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.2200288863 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.1442975275
Short name T647
Test name
Test status
Simulation time 914100802542 ps
CPU time 6229.47 seconds
Started Jul 01 12:27:04 PM PDT 24
Finished Jul 01 02:10:55 PM PDT 24
Peak memory 669948 kb
Host smart-29b5ec35-e969-4133-b449-df0d034e8a6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1442975275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.1442975275 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.533375765
Short name T530
Test name
Test status
Simulation time 231690375830 ps
CPU time 4840.22 seconds
Started Jul 01 12:27:03 PM PDT 24
Finished Jul 01 01:47:45 PM PDT 24
Peak memory 578644 kb
Host smart-a2a88a0b-7221-439e-a3dd-6aa9568f8401
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=533375765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.533375765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.3893509957
Short name T575
Test name
Test status
Simulation time 29293612 ps
CPU time 0.84 seconds
Started Jul 01 12:27:46 PM PDT 24
Finished Jul 01 12:27:49 PM PDT 24
Peak memory 217872 kb
Host smart-6eeae692-4709-4ec7-8d24-db62aa7613f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893509957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3893509957 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.1675290512
Short name T379
Test name
Test status
Simulation time 14258404220 ps
CPU time 171.9 seconds
Started Jul 01 12:27:38 PM PDT 24
Finished Jul 01 12:30:31 PM PDT 24
Peak memory 238848 kb
Host smart-c8214fd7-41f8-4138-92f2-5136fb1bfdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675290512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.1675290512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.754262742
Short name T527
Test name
Test status
Simulation time 141266083299 ps
CPU time 1321.4 seconds
Started Jul 01 12:27:30 PM PDT 24
Finished Jul 01 12:49:32 PM PDT 24
Peak memory 242716 kb
Host smart-e0364aac-fa59-4bbf-9040-ec0d23d6b4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754262742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.754262742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.690221183
Short name T341
Test name
Test status
Simulation time 3080462924 ps
CPU time 68.75 seconds
Started Jul 01 12:27:39 PM PDT 24
Finished Jul 01 12:28:48 PM PDT 24
Peak memory 230264 kb
Host smart-d2ab41f7-157f-45a1-9a74-b11fe09fbe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690221183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.690221183 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.2061562244
Short name T1013
Test name
Test status
Simulation time 7831640347 ps
CPU time 98.38 seconds
Started Jul 01 12:27:39 PM PDT 24
Finished Jul 01 12:29:18 PM PDT 24
Peak memory 242680 kb
Host smart-47bd9c72-56fa-4094-999c-d0d5a0e2bfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061562244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.2061562244 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.916651085
Short name T640
Test name
Test status
Simulation time 630195130 ps
CPU time 6.82 seconds
Started Jul 01 12:27:44 PM PDT 24
Finished Jul 01 12:27:52 PM PDT 24
Peak memory 218132 kb
Host smart-481e06e8-756e-4021-a7ba-5046fcb737ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916651085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.916651085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.4257079290
Short name T68
Test name
Test status
Simulation time 42098303 ps
CPU time 1.42 seconds
Started Jul 01 12:27:45 PM PDT 24
Finished Jul 01 12:27:47 PM PDT 24
Peak memory 218204 kb
Host smart-f3d1f09f-705b-4eae-8434-4eaedf637462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257079290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.4257079290 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.1887373173
Short name T500
Test name
Test status
Simulation time 37113308350 ps
CPU time 974.95 seconds
Started Jul 01 12:27:25 PM PDT 24
Finished Jul 01 12:43:41 PM PDT 24
Peak memory 305568 kb
Host smart-88663d90-b7df-4e03-a69c-a5e936b932b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887373173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.1887373173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.1468749800
Short name T122
Test name
Test status
Simulation time 20899104938 ps
CPU time 399.93 seconds
Started Jul 01 12:27:25 PM PDT 24
Finished Jul 01 12:34:06 PM PDT 24
Peak memory 251076 kb
Host smart-a6dfa68b-604c-42e2-bbda-345eb3a29038
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468749800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1468749800 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.1472310216
Short name T295
Test name
Test status
Simulation time 4942775869 ps
CPU time 80.18 seconds
Started Jul 01 12:27:24 PM PDT 24
Finished Jul 01 12:28:45 PM PDT 24
Peak memory 221824 kb
Host smart-8e380ca8-dacf-4476-9775-a92f6b92d58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472310216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1472310216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.2909725324
Short name T951
Test name
Test status
Simulation time 19768145008 ps
CPU time 1456.42 seconds
Started Jul 01 12:27:45 PM PDT 24
Finished Jul 01 12:52:02 PM PDT 24
Peak memory 403080 kb
Host smart-b45f496b-c6de-4186-92bc-2a7a792eeb86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2909725324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2909725324 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.2190219221
Short name T343
Test name
Test status
Simulation time 195258931 ps
CPU time 6.08 seconds
Started Jul 01 12:27:41 PM PDT 24
Finished Jul 01 12:27:48 PM PDT 24
Peak memory 218164 kb
Host smart-38dfad20-6ad0-499b-93d2-90f5e605a06c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190219221 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.2190219221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.2776573535
Short name T238
Test name
Test status
Simulation time 261903430 ps
CPU time 7 seconds
Started Jul 01 12:27:39 PM PDT 24
Finished Jul 01 12:27:47 PM PDT 24
Peak memory 218136 kb
Host smart-b3de98ca-f1c3-49f7-a13a-a5c070bf83db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776573535 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.2776573535 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.2653033926
Short name T420
Test name
Test status
Simulation time 383224831575 ps
CPU time 2130.71 seconds
Started Jul 01 12:27:28 PM PDT 24
Finished Jul 01 01:03:00 PM PDT 24
Peak memory 392376 kb
Host smart-cde07b72-d6df-4d57-b195-fd115b1edffb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2653033926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.2653033926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.3860179645
Short name T34
Test name
Test status
Simulation time 18881102331 ps
CPU time 1751.85 seconds
Started Jul 01 12:27:30 PM PDT 24
Finished Jul 01 12:56:43 PM PDT 24
Peak memory 375416 kb
Host smart-18f52ae2-90e3-4494-851d-1951f451b63c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3860179645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.3860179645 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.2307254147
Short name T239
Test name
Test status
Simulation time 57818751669 ps
CPU time 1679.49 seconds
Started Jul 01 12:27:30 PM PDT 24
Finished Jul 01 12:55:30 PM PDT 24
Peak memory 341340 kb
Host smart-7f18d3ee-9c5d-46cf-9e8c-e58eece5cf5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2307254147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.2307254147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.246584377
Short name T417
Test name
Test status
Simulation time 129093185888 ps
CPU time 1231.69 seconds
Started Jul 01 12:27:31 PM PDT 24
Finished Jul 01 12:48:04 PM PDT 24
Peak memory 295380 kb
Host smart-321489c8-aa9b-4462-92a3-4c942e490910
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=246584377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.246584377 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.1203201759
Short name T431
Test name
Test status
Simulation time 700579349261 ps
CPU time 5794.48 seconds
Started Jul 01 12:27:31 PM PDT 24
Finished Jul 01 02:04:07 PM PDT 24
Peak memory 645548 kb
Host smart-8a0b7bb9-d4f6-4495-8f28-2937c85dc02a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1203201759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.1203201759 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.1408768325
Short name T116
Test name
Test status
Simulation time 454704303262 ps
CPU time 5442.08 seconds
Started Jul 01 12:27:34 PM PDT 24
Finished Jul 01 01:58:18 PM PDT 24
Peak memory 582096 kb
Host smart-f36aa897-5540-418b-bbce-cb60297547d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1408768325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.1408768325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.5438613
Short name T319
Test name
Test status
Simulation time 48055397 ps
CPU time 0.8 seconds
Started Jul 01 12:08:18 PM PDT 24
Finished Jul 01 12:08:19 PM PDT 24
Peak memory 217880 kb
Host smart-66aa553d-fc3a-4277-b235-a4b802faae75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5438613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.5438613 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.3047750602
Short name T741
Test name
Test status
Simulation time 555586526 ps
CPU time 3.22 seconds
Started Jul 01 12:08:00 PM PDT 24
Finished Jul 01 12:08:04 PM PDT 24
Peak memory 220536 kb
Host smart-af79f77d-43b9-436b-b67a-ead5db45bbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047750602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3047750602 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.1294411708
Short name T727
Test name
Test status
Simulation time 30029338883 ps
CPU time 192.37 seconds
Started Jul 01 12:08:00 PM PDT 24
Finished Jul 01 12:11:13 PM PDT 24
Peak memory 238484 kb
Host smart-c9bdbef3-efc9-4bc2-8183-7e9232fbf0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294411708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.1294411708 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.3624234750
Short name T745
Test name
Test status
Simulation time 21048585080 ps
CPU time 971.08 seconds
Started Jul 01 12:07:51 PM PDT 24
Finished Jul 01 12:24:03 PM PDT 24
Peak memory 236816 kb
Host smart-25f1e465-f137-4443-b2bc-cd20636b85d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624234750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3624234750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.1414129581
Short name T39
Test name
Test status
Simulation time 414601912 ps
CPU time 35.07 seconds
Started Jul 01 12:08:06 PM PDT 24
Finished Jul 01 12:08:42 PM PDT 24
Peak memory 226392 kb
Host smart-58cdfa35-7d2b-4aca-9b0f-c3bf6045b29a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1414129581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1414129581 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.2489285448
Short name T633
Test name
Test status
Simulation time 98169031 ps
CPU time 0.87 seconds
Started Jul 01 12:08:06 PM PDT 24
Finished Jul 01 12:08:08 PM PDT 24
Peak memory 217724 kb
Host smart-ec169625-469e-432c-b323-357e548f7438
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2489285448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.2489285448 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.1906452485
Short name T10
Test name
Test status
Simulation time 2885704250 ps
CPU time 30.9 seconds
Started Jul 01 12:08:10 PM PDT 24
Finished Jul 01 12:08:41 PM PDT 24
Peak memory 218248 kb
Host smart-47cd9999-f198-4d4b-979d-b334df23841f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906452485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.1906452485 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.1464274890
Short name T511
Test name
Test status
Simulation time 15574320768 ps
CPU time 398.71 seconds
Started Jul 01 12:08:01 PM PDT 24
Finished Jul 01 12:14:40 PM PDT 24
Peak memory 253076 kb
Host smart-e0a45560-6a75-4c39-bce8-2c58d31c15f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464274890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1464274890 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.2945606769
Short name T173
Test name
Test status
Simulation time 61558215492 ps
CPU time 447.45 seconds
Started Jul 01 12:08:06 PM PDT 24
Finished Jul 01 12:15:34 PM PDT 24
Peak memory 254772 kb
Host smart-06c95544-8553-4bec-ba77-c622698d98d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945606769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2945606769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.276372758
Short name T1033
Test name
Test status
Simulation time 1010504512 ps
CPU time 2.21 seconds
Started Jul 01 12:08:06 PM PDT 24
Finished Jul 01 12:08:09 PM PDT 24
Peak memory 218008 kb
Host smart-05a6d4ac-6e4b-4311-ac13-38506089020a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276372758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.276372758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.184648510
Short name T42
Test name
Test status
Simulation time 298577234 ps
CPU time 1.9 seconds
Started Jul 01 12:08:11 PM PDT 24
Finished Jul 01 12:08:13 PM PDT 24
Peak memory 224380 kb
Host smart-ec5fcea1-f92c-408c-b049-f70b5e23c68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184648510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.184648510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.1250920923
Short name T877
Test name
Test status
Simulation time 63716255980 ps
CPU time 1641.25 seconds
Started Jul 01 12:07:46 PM PDT 24
Finished Jul 01 12:35:08 PM PDT 24
Peak memory 342728 kb
Host smart-30a35ec6-f2a8-4f62-8f7f-6701f64c86e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250920923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.1250920923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.3934777460
Short name T774
Test name
Test status
Simulation time 2614716442 ps
CPU time 50.59 seconds
Started Jul 01 12:08:00 PM PDT 24
Finished Jul 01 12:08:52 PM PDT 24
Peak memory 228332 kb
Host smart-ad11e394-c8a2-402d-8826-97059aad0ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934777460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3934777460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.3694269481
Short name T487
Test name
Test status
Simulation time 6098087821 ps
CPU time 195.46 seconds
Started Jul 01 12:07:51 PM PDT 24
Finished Jul 01 12:11:08 PM PDT 24
Peak memory 240116 kb
Host smart-b3493deb-a687-4d2a-a95e-3415c83d8751
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694269481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3694269481 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_stress_all.3803617252
Short name T399
Test name
Test status
Simulation time 1975606077 ps
CPU time 53.03 seconds
Started Jul 01 12:08:10 PM PDT 24
Finished Jul 01 12:09:04 PM PDT 24
Peak memory 227452 kb
Host smart-df76e1b7-13e7-48d5-9f9c-79fb8977c470
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3803617252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3803617252 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.1354518351
Short name T363
Test name
Test status
Simulation time 829361977 ps
CPU time 5.33 seconds
Started Jul 01 12:07:56 PM PDT 24
Finished Jul 01 12:08:02 PM PDT 24
Peak memory 219152 kb
Host smart-f3708301-006f-4ac0-84e4-917b92e3e294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354518351 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.1354518351 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.3957574253
Short name T385
Test name
Test status
Simulation time 240083047 ps
CPU time 6.77 seconds
Started Jul 01 12:07:55 PM PDT 24
Finished Jul 01 12:08:03 PM PDT 24
Peak memory 218128 kb
Host smart-6689f342-764b-487e-b5f8-ec4ce4877db3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957574253 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.3957574253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.246127442
Short name T721
Test name
Test status
Simulation time 103912907291 ps
CPU time 2425.98 seconds
Started Jul 01 12:07:51 PM PDT 24
Finished Jul 01 12:48:17 PM PDT 24
Peak memory 395532 kb
Host smart-d4e66927-0fbc-4e48-9656-942556644195
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=246127442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.246127442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.4120654638
Short name T518
Test name
Test status
Simulation time 95572520172 ps
CPU time 2498.05 seconds
Started Jul 01 12:07:51 PM PDT 24
Finished Jul 01 12:49:30 PM PDT 24
Peak memory 386344 kb
Host smart-fac8b666-81d5-46bd-8dce-791c2e602bba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4120654638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.4120654638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.1990708976
Short name T782
Test name
Test status
Simulation time 525133911097 ps
CPU time 1862.38 seconds
Started Jul 01 12:07:51 PM PDT 24
Finished Jul 01 12:38:54 PM PDT 24
Peak memory 331156 kb
Host smart-ae972b03-e787-401e-93b7-8f4d15d32b9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1990708976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.1990708976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.2404213771
Short name T615
Test name
Test status
Simulation time 37748783854 ps
CPU time 1306.37 seconds
Started Jul 01 12:07:57 PM PDT 24
Finished Jul 01 12:29:44 PM PDT 24
Peak memory 300604 kb
Host smart-6d822a8e-da6d-4f70-8d19-5b7a48452e02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2404213771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.2404213771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.3628850416
Short name T604
Test name
Test status
Simulation time 370458204086 ps
CPU time 6038.58 seconds
Started Jul 01 12:07:56 PM PDT 24
Finished Jul 01 01:48:37 PM PDT 24
Peak memory 662592 kb
Host smart-38727c42-14ae-4cab-8d49-ed1f2797b5d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3628850416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.3628850416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.3395054034
Short name T770
Test name
Test status
Simulation time 244954261537 ps
CPU time 5401.31 seconds
Started Jul 01 12:07:56 PM PDT 24
Finished Jul 01 01:37:59 PM PDT 24
Peak memory 577540 kb
Host smart-abac9b07-c6c0-4129-8488-5acf15fa3fc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3395054034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.3395054034 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.1389494686
Short name T998
Test name
Test status
Simulation time 36761222 ps
CPU time 0.79 seconds
Started Jul 01 12:08:41 PM PDT 24
Finished Jul 01 12:08:42 PM PDT 24
Peak memory 217868 kb
Host smart-23f42054-854f-438f-bb51-be52579fd062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389494686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1389494686 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.2099588915
Short name T712
Test name
Test status
Simulation time 13720324049 ps
CPU time 330.94 seconds
Started Jul 01 12:08:19 PM PDT 24
Finished Jul 01 12:13:51 PM PDT 24
Peak memory 247720 kb
Host smart-c1138d52-a85f-435d-af05-79453a383b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099588915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2099588915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.120607164
Short name T860
Test name
Test status
Simulation time 78588475762 ps
CPU time 249.71 seconds
Started Jul 01 12:08:20 PM PDT 24
Finished Jul 01 12:12:31 PM PDT 24
Peak memory 242476 kb
Host smart-56079c8a-16ba-4372-900e-61de164e1a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120607164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.120607164 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.393426645
Short name T879
Test name
Test status
Simulation time 46344580430 ps
CPU time 1044.59 seconds
Started Jul 01 12:08:15 PM PDT 24
Finished Jul 01 12:25:41 PM PDT 24
Peak memory 242632 kb
Host smart-3d19fee1-c65c-4190-8afb-5de7e36b5521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393426645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.393426645 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.631917369
Short name T281
Test name
Test status
Simulation time 3580609217 ps
CPU time 29.64 seconds
Started Jul 01 12:08:40 PM PDT 24
Finished Jul 01 12:09:10 PM PDT 24
Peak memory 224308 kb
Host smart-b5ea03d0-2fea-4710-9e47-c071f42924e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=631917369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.631917369 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.2721226572
Short name T700
Test name
Test status
Simulation time 53758175 ps
CPU time 1.07 seconds
Started Jul 01 12:08:42 PM PDT 24
Finished Jul 01 12:08:44 PM PDT 24
Peak memory 217780 kb
Host smart-f6cf6875-7d0f-46ba-912c-3e0220be6261
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2721226572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2721226572 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.775640594
Short name T11
Test name
Test status
Simulation time 17185915223 ps
CPU time 67.99 seconds
Started Jul 01 12:08:41 PM PDT 24
Finished Jul 01 12:09:49 PM PDT 24
Peak memory 219936 kb
Host smart-9d077579-e4bf-4f0d-9a0e-b333b1c61bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775640594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.775640594 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.4007844302
Short name T684
Test name
Test status
Simulation time 3823010348 ps
CPU time 126.11 seconds
Started Jul 01 12:08:20 PM PDT 24
Finished Jul 01 12:10:27 PM PDT 24
Peak memory 236244 kb
Host smart-7d91e0ec-5a66-42c2-bd3e-155925aec227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007844302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.4007844302 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.4291049197
Short name T875
Test name
Test status
Simulation time 3151962274 ps
CPU time 252.83 seconds
Started Jul 01 12:08:36 PM PDT 24
Finished Jul 01 12:12:50 PM PDT 24
Peak memory 255464 kb
Host smart-074a38fc-42de-47a4-81fd-adeb1044121a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291049197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.4291049197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.2013487262
Short name T851
Test name
Test status
Simulation time 1344569063 ps
CPU time 10.41 seconds
Started Jul 01 12:08:36 PM PDT 24
Finished Jul 01 12:08:47 PM PDT 24
Peak memory 218016 kb
Host smart-944fb240-1fc3-46d2-b321-d0ec951a8c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013487262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2013487262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.2215788195
Short name T25
Test name
Test status
Simulation time 36546733 ps
CPU time 1.32 seconds
Started Jul 01 12:08:39 PM PDT 24
Finished Jul 01 12:08:41 PM PDT 24
Peak memory 218196 kb
Host smart-cc84877e-f955-4a34-b4e1-ac800122c966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215788195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2215788195 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.1430313124
Short name T474
Test name
Test status
Simulation time 54672234957 ps
CPU time 1994.23 seconds
Started Jul 01 12:08:16 PM PDT 24
Finished Jul 01 12:41:31 PM PDT 24
Peak memory 379320 kb
Host smart-1c9dce13-7b55-472e-83f5-79c5cd0ca846
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430313124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.1430313124 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.4122228517
Short name T83
Test name
Test status
Simulation time 4051739240 ps
CPU time 271.7 seconds
Started Jul 01 12:08:24 PM PDT 24
Finished Jul 01 12:12:57 PM PDT 24
Peak memory 245460 kb
Host smart-41d25fda-99cd-4d3a-8060-4513f5727e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122228517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.4122228517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.351398333
Short name T488
Test name
Test status
Simulation time 2323653317 ps
CPU time 48.74 seconds
Started Jul 01 12:08:14 PM PDT 24
Finished Jul 01 12:09:04 PM PDT 24
Peak memory 226328 kb
Host smart-94fa9869-7dee-4b1f-8058-d951186523b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351398333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.351398333 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.91207062
Short name T622
Test name
Test status
Simulation time 5949154047 ps
CPU time 36.92 seconds
Started Jul 01 12:08:16 PM PDT 24
Finished Jul 01 12:08:54 PM PDT 24
Peak memory 226336 kb
Host smart-d7f8442c-4e8a-4c61-9b55-f35154a0746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91207062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.91207062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.3145427653
Short name T540
Test name
Test status
Simulation time 121829916053 ps
CPU time 820.59 seconds
Started Jul 01 12:08:40 PM PDT 24
Finished Jul 01 12:22:21 PM PDT 24
Peak memory 294432 kb
Host smart-2ffcb67c-cab2-40d3-8e0d-a5839dc92f56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3145427653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3145427653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.151908636
Short name T609
Test name
Test status
Simulation time 110706448 ps
CPU time 5.84 seconds
Started Jul 01 12:08:18 PM PDT 24
Finished Jul 01 12:08:25 PM PDT 24
Peak memory 218392 kb
Host smart-8517d3ba-070e-4933-b1cb-bcb9af6e0dd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151908636 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.kmac_test_vectors_kmac.151908636 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.450017451
Short name T1007
Test name
Test status
Simulation time 134966441 ps
CPU time 5.36 seconds
Started Jul 01 12:08:20 PM PDT 24
Finished Jul 01 12:08:26 PM PDT 24
Peak memory 219108 kb
Host smart-0e48e817-86fc-4833-ba6f-898c60d1c168
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450017451 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.kmac_test_vectors_kmac_xof.450017451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.3609024815
Short name T485
Test name
Test status
Simulation time 464997203736 ps
CPU time 2595.45 seconds
Started Jul 01 12:08:18 PM PDT 24
Finished Jul 01 12:51:34 PM PDT 24
Peak memory 397840 kb
Host smart-8c4fcf11-2789-488b-8511-2fe005ce5f54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3609024815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.3609024815 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.3304454233
Short name T699
Test name
Test status
Simulation time 100460792145 ps
CPU time 1963.18 seconds
Started Jul 01 12:08:15 PM PDT 24
Finished Jul 01 12:40:59 PM PDT 24
Peak memory 382088 kb
Host smart-5ad51354-e5a6-4089-98f5-da373635969f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3304454233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.3304454233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.79180586
Short name T197
Test name
Test status
Simulation time 15411599237 ps
CPU time 1551.25 seconds
Started Jul 01 12:08:14 PM PDT 24
Finished Jul 01 12:34:07 PM PDT 24
Peak memory 338716 kb
Host smart-67f0efe4-af64-44c8-88fd-411ddbf14aa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=79180586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.79180586 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.427046213
Short name T195
Test name
Test status
Simulation time 69104706172 ps
CPU time 1170.76 seconds
Started Jul 01 12:08:14 PM PDT 24
Finished Jul 01 12:27:46 PM PDT 24
Peak memory 294164 kb
Host smart-471f8bd4-943c-4150-9139-cd51d0a6dffb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=427046213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.427046213 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.2636349816
Short name T302
Test name
Test status
Simulation time 69919099586 ps
CPU time 4924.76 seconds
Started Jul 01 12:08:14 PM PDT 24
Finished Jul 01 01:30:21 PM PDT 24
Peak memory 652876 kb
Host smart-4fe28bde-7593-41bb-9ee6-43524e4d0fe6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2636349816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.2636349816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.4270594234
Short name T345
Test name
Test status
Simulation time 110372578870 ps
CPU time 4643.2 seconds
Started Jul 01 12:08:19 PM PDT 24
Finished Jul 01 01:25:44 PM PDT 24
Peak memory 574792 kb
Host smart-a65ba89e-2155-4144-acd7-1cd808ca37f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4270594234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.4270594234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.66738679
Short name T539
Test name
Test status
Simulation time 68069222 ps
CPU time 0.88 seconds
Started Jul 01 12:08:59 PM PDT 24
Finished Jul 01 12:09:00 PM PDT 24
Peak memory 217904 kb
Host smart-0588237b-4d1c-4753-8b90-be8ce938abff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66738679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.66738679 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.2160270679
Short name T1041
Test name
Test status
Simulation time 9276058613 ps
CPU time 209.94 seconds
Started Jul 01 12:08:50 PM PDT 24
Finished Jul 01 12:12:20 PM PDT 24
Peak memory 240880 kb
Host smart-b280ad75-3f1b-438c-980d-55aed3029823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160270679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.2160270679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.2392125460
Short name T853
Test name
Test status
Simulation time 39595754762 ps
CPU time 144.54 seconds
Started Jul 01 12:08:50 PM PDT 24
Finished Jul 01 12:11:15 PM PDT 24
Peak memory 236400 kb
Host smart-07d4b89f-a5f1-4c8a-9987-83a1d887fdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392125460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2392125460 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.1307929548
Short name T468
Test name
Test status
Simulation time 27329214978 ps
CPU time 677.04 seconds
Started Jul 01 12:08:39 PM PDT 24
Finished Jul 01 12:19:57 PM PDT 24
Peak memory 234508 kb
Host smart-e3050b05-cf72-4a26-8a10-7cf2c469b538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307929548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1307929548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.4031162254
Short name T841
Test name
Test status
Simulation time 71600280 ps
CPU time 1.27 seconds
Started Jul 01 12:08:55 PM PDT 24
Finished Jul 01 12:08:57 PM PDT 24
Peak memory 217996 kb
Host smart-dd4a3f21-831a-4be6-9d15-ae64a72223a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4031162254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.4031162254 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.1874701230
Short name T928
Test name
Test status
Simulation time 107483001 ps
CPU time 1.16 seconds
Started Jul 01 12:08:57 PM PDT 24
Finished Jul 01 12:08:59 PM PDT 24
Peak memory 217996 kb
Host smart-4faf090f-2f79-4d8d-b8dd-4d69fdfb122d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1874701230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1874701230 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.2117668022
Short name T144
Test name
Test status
Simulation time 10728577084 ps
CPU time 55.44 seconds
Started Jul 01 12:08:57 PM PDT 24
Finished Jul 01 12:09:53 PM PDT 24
Peak memory 219632 kb
Host smart-67917d02-fb60-4388-afde-ff1bbb795b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117668022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.2117668022 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.4158520973
Short name T423
Test name
Test status
Simulation time 2969720613 ps
CPU time 66.66 seconds
Started Jul 01 12:08:54 PM PDT 24
Finished Jul 01 12:10:02 PM PDT 24
Peak memory 229820 kb
Host smart-9666bdc6-5405-4261-91df-8056df9691ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158520973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.4158520973 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.4282567765
Short name T1037
Test name
Test status
Simulation time 36489100308 ps
CPU time 243.3 seconds
Started Jul 01 12:08:54 PM PDT 24
Finished Jul 01 12:12:58 PM PDT 24
Peak memory 251892 kb
Host smart-98de8490-fd82-4a79-a533-318a6de35d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282567765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.4282567765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.4218044058
Short name T783
Test name
Test status
Simulation time 1315453362 ps
CPU time 4.97 seconds
Started Jul 01 12:08:55 PM PDT 24
Finished Jul 01 12:09:01 PM PDT 24
Peak memory 218008 kb
Host smart-e5962960-c452-4c72-a65f-7510f1db1a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218044058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.4218044058 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.3053198744
Short name T984
Test name
Test status
Simulation time 90494061 ps
CPU time 1.41 seconds
Started Jul 01 12:08:55 PM PDT 24
Finished Jul 01 12:08:57 PM PDT 24
Peak memory 218104 kb
Host smart-0f210fa7-ecbb-45c8-aa42-b01f8e51a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053198744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.3053198744 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.3644704692
Short name T1004
Test name
Test status
Simulation time 28061086177 ps
CPU time 961.89 seconds
Started Jul 01 12:08:40 PM PDT 24
Finished Jul 01 12:24:43 PM PDT 24
Peak memory 299748 kb
Host smart-a8cd6175-7cbc-4c29-87e5-c1e3a71ffebf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644704692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.3644704692 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_sideload.3152808748
Short name T986
Test name
Test status
Simulation time 58327877911 ps
CPU time 510.29 seconds
Started Jul 01 12:08:40 PM PDT 24
Finished Jul 01 12:17:11 PM PDT 24
Peak memory 255012 kb
Host smart-ac67387d-4329-401d-9c23-eca7f1fe575c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152808748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3152808748 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.1889613179
Short name T223
Test name
Test status
Simulation time 3335847499 ps
CPU time 60.93 seconds
Started Jul 01 12:08:39 PM PDT 24
Finished Jul 01 12:09:41 PM PDT 24
Peak memory 222844 kb
Host smart-0a08418d-2764-4c72-845e-c684bc1ab28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889613179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1889613179 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.2894465336
Short name T84
Test name
Test status
Simulation time 51314139683 ps
CPU time 1459.28 seconds
Started Jul 01 12:08:59 PM PDT 24
Finished Jul 01 12:33:19 PM PDT 24
Peak memory 340884 kb
Host smart-9e5a9f87-a158-4ca7-8f29-ba1d13fcf359
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2894465336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2894465336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.4101145008
Short name T24
Test name
Test status
Simulation time 97270189282 ps
CPU time 1915.2 seconds
Started Jul 01 12:08:57 PM PDT 24
Finished Jul 01 12:40:53 PM PDT 24
Peak memory 317884 kb
Host smart-66094dfb-37da-4aff-8c55-4bd23261a974
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101145008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.4101145008 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.3779753232
Short name T784
Test name
Test status
Simulation time 1133463642 ps
CPU time 5.82 seconds
Started Jul 01 12:08:44 PM PDT 24
Finished Jul 01 12:08:51 PM PDT 24
Peak memory 218096 kb
Host smart-711b3fe9-ae34-466b-9452-ce176fbc66a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779753232 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.3779753232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.3225866340
Short name T685
Test name
Test status
Simulation time 244381648 ps
CPU time 6.48 seconds
Started Jul 01 12:08:49 PM PDT 24
Finished Jul 01 12:08:56 PM PDT 24
Peak memory 218156 kb
Host smart-b2e82192-6ac9-47b8-8030-6bcacfc1135a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225866340 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.3225866340 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.2683465418
Short name T203
Test name
Test status
Simulation time 121429618454 ps
CPU time 2098.89 seconds
Started Jul 01 12:08:42 PM PDT 24
Finished Jul 01 12:43:42 PM PDT 24
Peak memory 395804 kb
Host smart-0f49196d-52ff-4e95-8978-288bd422c3fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2683465418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.2683465418 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.3569219197
Short name T410
Test name
Test status
Simulation time 315985650665 ps
CPU time 1955.97 seconds
Started Jul 01 12:08:44 PM PDT 24
Finished Jul 01 12:41:21 PM PDT 24
Peak memory 349364 kb
Host smart-ca2da88e-f2ab-4b12-b984-a561b3a427a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3569219197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.3569219197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.275814786
Short name T306
Test name
Test status
Simulation time 26117975866 ps
CPU time 1138.54 seconds
Started Jul 01 12:08:44 PM PDT 24
Finished Jul 01 12:27:44 PM PDT 24
Peak memory 297756 kb
Host smart-dd6044d4-822e-4ea2-ba25-45229b88ee82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=275814786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.275814786 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.3795148593
Short name T597
Test name
Test status
Simulation time 226541720086 ps
CPU time 6013.3 seconds
Started Jul 01 12:08:44 PM PDT 24
Finished Jul 01 01:48:59 PM PDT 24
Peak memory 659720 kb
Host smart-d0be0684-0ce8-432a-8775-c8a2f1e9c78a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3795148593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.3795148593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.3746108159
Short name T593
Test name
Test status
Simulation time 251581580087 ps
CPU time 4589.55 seconds
Started Jul 01 12:08:44 PM PDT 24
Finished Jul 01 01:25:15 PM PDT 24
Peak memory 578384 kb
Host smart-3b572ff8-d154-4b04-b3b5-67917dfa9dee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3746108159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.3746108159 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.3582087233
Short name T110
Test name
Test status
Simulation time 30520024 ps
CPU time 0.84 seconds
Started Jul 01 12:09:25 PM PDT 24
Finished Jul 01 12:09:26 PM PDT 24
Peak memory 217908 kb
Host smart-f8def2df-7f9e-48fd-b81b-0fee4a668ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582087233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3582087233 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.1320532105
Short name T641
Test name
Test status
Simulation time 7556994894 ps
CPU time 161.18 seconds
Started Jul 01 12:09:15 PM PDT 24
Finished Jul 01 12:11:57 PM PDT 24
Peak memory 238080 kb
Host smart-dda77e4e-e54f-4bf8-a24a-82400eef9c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320532105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1320532105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.3456346893
Short name T439
Test name
Test status
Simulation time 1632022501 ps
CPU time 70.5 seconds
Started Jul 01 12:09:13 PM PDT 24
Finished Jul 01 12:10:24 PM PDT 24
Peak memory 228424 kb
Host smart-d86702da-67b4-42d0-af9d-81079196a368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456346893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.3456346893 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.3836903407
Short name T654
Test name
Test status
Simulation time 18025416828 ps
CPU time 729.12 seconds
Started Jul 01 12:09:02 PM PDT 24
Finished Jul 01 12:21:12 PM PDT 24
Peak memory 235796 kb
Host smart-087c6b53-6843-40f9-9557-90d4aa8784e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836903407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3836903407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.2944590034
Short name T247
Test name
Test status
Simulation time 1969342519 ps
CPU time 16.37 seconds
Started Jul 01 12:09:18 PM PDT 24
Finished Jul 01 12:09:35 PM PDT 24
Peak memory 226872 kb
Host smart-e42aa924-050c-436c-9f60-f0e97dcb2905
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2944590034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2944590034 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.2302443308
Short name T1029
Test name
Test status
Simulation time 22016282 ps
CPU time 1.09 seconds
Started Jul 01 12:09:19 PM PDT 24
Finished Jul 01 12:09:21 PM PDT 24
Peak memory 217980 kb
Host smart-f4b56d23-0284-4c8f-a373-3bdea59334c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2302443308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2302443308 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.926994030
Short name T886
Test name
Test status
Simulation time 682171249 ps
CPU time 4.49 seconds
Started Jul 01 12:09:18 PM PDT 24
Finished Jul 01 12:09:23 PM PDT 24
Peak memory 218036 kb
Host smart-cb6bd996-60e3-4af5-8523-032f45d8765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926994030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.926994030 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_error.1329162908
Short name T149
Test name
Test status
Simulation time 16401902376 ps
CPU time 342.87 seconds
Started Jul 01 12:09:17 PM PDT 24
Finished Jul 01 12:15:01 PM PDT 24
Peak memory 259060 kb
Host smart-68039f29-d4e0-4ba9-839a-927392eab0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329162908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.1329162908 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.3589144293
Short name T284
Test name
Test status
Simulation time 11466785097 ps
CPU time 17.25 seconds
Started Jul 01 12:09:19 PM PDT 24
Finished Jul 01 12:09:37 PM PDT 24
Peak memory 225956 kb
Host smart-a5f7144c-ebd0-46c5-8b25-a8866d6832c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589144293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3589144293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.3984965380
Short name T621
Test name
Test status
Simulation time 1209111469 ps
CPU time 16.76 seconds
Started Jul 01 12:09:23 PM PDT 24
Finished Jul 01 12:09:41 PM PDT 24
Peak memory 230600 kb
Host smart-86384bbc-82b5-43a7-a822-837dc696f974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984965380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3984965380 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.2766198763
Short name T572
Test name
Test status
Simulation time 476399226796 ps
CPU time 2742.77 seconds
Started Jul 01 12:09:01 PM PDT 24
Finished Jul 01 12:54:44 PM PDT 24
Peak memory 432676 kb
Host smart-e12e893f-62a8-401c-87d7-e69478dfe393
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766198763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.2766198763 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.4229365472
Short name T926
Test name
Test status
Simulation time 1351853383 ps
CPU time 80.44 seconds
Started Jul 01 12:09:19 PM PDT 24
Finished Jul 01 12:10:40 PM PDT 24
Peak memory 231256 kb
Host smart-5b1cfd93-7fa3-4514-9d98-f319bc4ae20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229365472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.4229365472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.1546880370
Short name T583
Test name
Test status
Simulation time 5685000467 ps
CPU time 475.1 seconds
Started Jul 01 12:09:06 PM PDT 24
Finished Jul 01 12:17:02 PM PDT 24
Peak memory 255500 kb
Host smart-00cbaf87-8242-448d-8672-47223706dd94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546880370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.1546880370 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.900432693
Short name T698
Test name
Test status
Simulation time 3252465868 ps
CPU time 63.39 seconds
Started Jul 01 12:08:58 PM PDT 24
Finished Jul 01 12:10:02 PM PDT 24
Peak memory 222520 kb
Host smart-a4e121cc-3bc7-41ec-a143-52cb4a167594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900432693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.900432693 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all_with_rand_reset.4162411598
Short name T137
Test name
Test status
Simulation time 14760774427 ps
CPU time 496.44 seconds
Started Jul 01 12:09:25 PM PDT 24
Finished Jul 01 12:17:42 PM PDT 24
Peak memory 273584 kb
Host smart-9414687f-3e61-4408-a928-a43136223eb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162411598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.4162411598 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.2310563469
Short name T287
Test name
Test status
Simulation time 775178562 ps
CPU time 6.31 seconds
Started Jul 01 12:09:14 PM PDT 24
Finished Jul 01 12:09:21 PM PDT 24
Peak memory 218160 kb
Host smart-571df8df-de06-4ef6-8b83-0624733c75dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310563469 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.2310563469 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.1760395003
Short name T370
Test name
Test status
Simulation time 186190674 ps
CPU time 6.21 seconds
Started Jul 01 12:09:16 PM PDT 24
Finished Jul 01 12:09:22 PM PDT 24
Peak memory 218136 kb
Host smart-838e3561-fc1e-40fa-bda2-1f044af42d71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760395003 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.1760395003 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.3334888695
Short name T1051
Test name
Test status
Simulation time 107774413185 ps
CPU time 2507.63 seconds
Started Jul 01 12:09:03 PM PDT 24
Finished Jul 01 12:50:52 PM PDT 24
Peak memory 402380 kb
Host smart-9f6a600b-97e4-477b-a3ff-834b89cf06fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3334888695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.3334888695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.3656012040
Short name T997
Test name
Test status
Simulation time 384519496112 ps
CPU time 2419.72 seconds
Started Jul 01 12:09:03 PM PDT 24
Finished Jul 01 12:49:24 PM PDT 24
Peak memory 386900 kb
Host smart-6bc5bd10-df1c-4b3e-b657-a4d233fac14e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3656012040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.3656012040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.207695439
Short name T528
Test name
Test status
Simulation time 281786715710 ps
CPU time 1918.49 seconds
Started Jul 01 12:09:07 PM PDT 24
Finished Jul 01 12:41:07 PM PDT 24
Peak memory 339828 kb
Host smart-467eeb3a-bfcb-4c1b-bd40-7bbc99a778ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=207695439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.207695439 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.2446734627
Short name T469
Test name
Test status
Simulation time 11100989608 ps
CPU time 1102.08 seconds
Started Jul 01 12:09:09 PM PDT 24
Finished Jul 01 12:27:31 PM PDT 24
Peak memory 299148 kb
Host smart-46b462a4-f635-4165-8f9b-504bb7660555
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2446734627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.2446734627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.2024805723
Short name T571
Test name
Test status
Simulation time 64258177452 ps
CPU time 5603.35 seconds
Started Jul 01 12:09:09 PM PDT 24
Finished Jul 01 01:42:33 PM PDT 24
Peak memory 657008 kb
Host smart-2cd8f218-c331-44b3-b072-bdfa1ee01330
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2024805723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.2024805723 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.2286684675
Short name T443
Test name
Test status
Simulation time 105885894700 ps
CPU time 4699.77 seconds
Started Jul 01 12:09:08 PM PDT 24
Finished Jul 01 01:27:29 PM PDT 24
Peak memory 582312 kb
Host smart-78350103-623b-48c4-b97d-0994f06044f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2286684675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.2286684675 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.3928418264
Short name T437
Test name
Test status
Simulation time 24409664 ps
CPU time 0.77 seconds
Started Jul 01 12:09:57 PM PDT 24
Finished Jul 01 12:09:59 PM PDT 24
Peak memory 217820 kb
Host smart-48598d9e-1b8d-4929-8363-dff503115376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928418264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.3928418264 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.1643718670
Short name T510
Test name
Test status
Simulation time 62801346793 ps
CPU time 330.9 seconds
Started Jul 01 12:09:40 PM PDT 24
Finished Jul 01 12:15:11 PM PDT 24
Peak memory 249708 kb
Host smart-c4d7f623-7425-4bb3-85ef-1491628890bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643718670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1643718670 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.2655127863
Short name T317
Test name
Test status
Simulation time 4707549574 ps
CPU time 245.43 seconds
Started Jul 01 12:09:39 PM PDT 24
Finished Jul 01 12:13:45 PM PDT 24
Peak memory 244388 kb
Host smart-81099615-d857-48fc-8622-cdd138edad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655127863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.2655127863 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.3355825365
Short name T361
Test name
Test status
Simulation time 18657954585 ps
CPU time 865.57 seconds
Started Jul 01 12:09:30 PM PDT 24
Finished Jul 01 12:23:56 PM PDT 24
Peak memory 235852 kb
Host smart-8334f792-89f3-482e-b501-0c180446562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355825365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3355825365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.2634555591
Short name T493
Test name
Test status
Simulation time 338106567 ps
CPU time 6.9 seconds
Started Jul 01 12:09:46 PM PDT 24
Finished Jul 01 12:09:53 PM PDT 24
Peak memory 218012 kb
Host smart-022caa4b-1b11-4da4-8dfd-5f7b3e01af09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2634555591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.2634555591 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.1328541039
Short name T563
Test name
Test status
Simulation time 52974294 ps
CPU time 1.07 seconds
Started Jul 01 12:09:46 PM PDT 24
Finished Jul 01 12:09:48 PM PDT 24
Peak memory 217840 kb
Host smart-a64617b0-c762-4aa5-8958-001973c9e01e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1328541039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1328541039 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.1770097327
Short name T1024
Test name
Test status
Simulation time 8043378580 ps
CPU time 42.61 seconds
Started Jul 01 12:09:54 PM PDT 24
Finished Jul 01 12:10:37 PM PDT 24
Peak memory 218308 kb
Host smart-06923eb0-d554-433a-8fbd-d7faa481d68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770097327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1770097327 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.1678451250
Short name T501
Test name
Test status
Simulation time 33579478296 ps
CPU time 337.51 seconds
Started Jul 01 12:09:42 PM PDT 24
Finished Jul 01 12:15:21 PM PDT 24
Peak memory 248976 kb
Host smart-b29287b3-e51a-40db-bca3-e69eb12c1aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678451250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.1678451250 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.4042197795
Short name T718
Test name
Test status
Simulation time 3562626059 ps
CPU time 77.68 seconds
Started Jul 01 12:09:47 PM PDT 24
Finished Jul 01 12:11:05 PM PDT 24
Peak memory 242780 kb
Host smart-428d4a0e-dd3c-45e8-9667-75a13e225467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042197795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.4042197795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.2983118643
Short name T448
Test name
Test status
Simulation time 1864528986 ps
CPU time 4.46 seconds
Started Jul 01 12:09:45 PM PDT 24
Finished Jul 01 12:09:50 PM PDT 24
Peak memory 218140 kb
Host smart-9fa2aa14-abed-49a8-aaa6-396453e33960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983118643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2983118643 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.1563709557
Short name T1008
Test name
Test status
Simulation time 28290959 ps
CPU time 1.17 seconds
Started Jul 01 12:09:52 PM PDT 24
Finished Jul 01 12:09:53 PM PDT 24
Peak memory 218168 kb
Host smart-99605eae-8991-41d2-813b-492c163e79de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563709557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1563709557 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.3417513145
Short name T221
Test name
Test status
Simulation time 272120027330 ps
CPU time 2497.29 seconds
Started Jul 01 12:09:32 PM PDT 24
Finished Jul 01 12:51:10 PM PDT 24
Peak memory 406684 kb
Host smart-f444c6d1-ff2b-4395-bf5b-e60ed352f558
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417513145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.3417513145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.1993682865
Short name T748
Test name
Test status
Simulation time 17401516415 ps
CPU time 377.16 seconds
Started Jul 01 12:09:42 PM PDT 24
Finished Jul 01 12:16:00 PM PDT 24
Peak memory 252120 kb
Host smart-976cb9a2-940a-4e2c-aef8-2058839a75f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993682865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1993682865 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.704008022
Short name T390
Test name
Test status
Simulation time 7720303592 ps
CPU time 185.38 seconds
Started Jul 01 12:09:32 PM PDT 24
Finished Jul 01 12:12:38 PM PDT 24
Peak memory 242672 kb
Host smart-8253b023-71ed-42b7-83d1-5f255feac996
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704008022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.704008022 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.3999255622
Short name T742
Test name
Test status
Simulation time 12007631245 ps
CPU time 63.85 seconds
Started Jul 01 12:09:25 PM PDT 24
Finished Jul 01 12:10:29 PM PDT 24
Peak memory 225712 kb
Host smart-a80c294f-51e5-4d9b-a868-36408c5bb83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999255622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3999255622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.2921257041
Short name T833
Test name
Test status
Simulation time 28669157250 ps
CPU time 898.63 seconds
Started Jul 01 12:09:55 PM PDT 24
Finished Jul 01 12:24:55 PM PDT 24
Peak memory 326800 kb
Host smart-b93c4c0c-d48f-4705-8f6e-4aa03d22b5f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2921257041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.2921257041 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.1758588528
Short name T128
Test name
Test status
Simulation time 247145953 ps
CPU time 6.05 seconds
Started Jul 01 12:09:40 PM PDT 24
Finished Jul 01 12:09:47 PM PDT 24
Peak memory 218212 kb
Host smart-70f80881-88bd-45de-bbef-e4fa90c45477
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758588528 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.1758588528 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.1329507537
Short name T543
Test name
Test status
Simulation time 129618864 ps
CPU time 6 seconds
Started Jul 01 12:09:41 PM PDT 24
Finished Jul 01 12:09:47 PM PDT 24
Peak memory 218156 kb
Host smart-dd446dfd-bba0-454e-8f4c-68ca58222c09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329507537 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.1329507537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.1843400819
Short name T496
Test name
Test status
Simulation time 20348483116 ps
CPU time 1848.03 seconds
Started Jul 01 12:09:31 PM PDT 24
Finished Jul 01 12:40:20 PM PDT 24
Peak memory 396032 kb
Host smart-09236484-bc93-40da-86c6-cf1b52962874
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1843400819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1843400819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.2238715366
Short name T1046
Test name
Test status
Simulation time 497325271426 ps
CPU time 2270.53 seconds
Started Jul 01 12:09:30 PM PDT 24
Finished Jul 01 12:47:22 PM PDT 24
Peak memory 390640 kb
Host smart-f006e10b-85a1-4297-ab34-742798c11ec5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2238715366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.2238715366 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.3023405510
Short name T332
Test name
Test status
Simulation time 30341251637 ps
CPU time 1483.74 seconds
Started Jul 01 12:09:30 PM PDT 24
Finished Jul 01 12:34:15 PM PDT 24
Peak memory 340452 kb
Host smart-8cd15c9b-2f60-4317-8284-34aa3d353fe3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3023405510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3023405510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.2884730385
Short name T614
Test name
Test status
Simulation time 66411906101 ps
CPU time 1054.18 seconds
Started Jul 01 12:09:36 PM PDT 24
Finished Jul 01 12:27:11 PM PDT 24
Peak memory 299268 kb
Host smart-04f1997b-1a39-471a-80bc-d7c717dd82cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2884730385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.2884730385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.308878972
Short name T823
Test name
Test status
Simulation time 237064534449 ps
CPU time 6054.33 seconds
Started Jul 01 12:09:36 PM PDT 24
Finished Jul 01 01:50:32 PM PDT 24
Peak memory 659964 kb
Host smart-98db5e19-194f-4b4b-b6be-9bcdc00f5081
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=308878972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.308878972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.1816091882
Short name T482
Test name
Test status
Simulation time 55837754684 ps
CPU time 4407.29 seconds
Started Jul 01 12:09:35 PM PDT 24
Finished Jul 01 01:23:03 PM PDT 24
Peak memory 583724 kb
Host smart-ced241d0-ceda-4cdb-a6a3-dd87078f3830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1816091882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.1816091882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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