Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177064 |
1 |
|
|
T1 |
135 |
|
T2 |
1304 |
|
T7 |
1307 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
86510 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
70181 |
1 |
|
|
T1 |
2 |
|
T2 |
1284 |
|
T7 |
31 |
seven_bytes |
2875 |
1 |
|
|
T1 |
4 |
|
T7 |
37 |
|
T18 |
13 |
six_bytes |
2896 |
1 |
|
|
T1 |
4 |
|
T7 |
32 |
|
T18 |
23 |
five_bytes |
2868 |
1 |
|
|
T1 |
3 |
|
T7 |
35 |
|
T18 |
12 |
four_bytes |
2870 |
1 |
|
|
T1 |
1 |
|
T7 |
38 |
|
T18 |
22 |
three_bytes |
3019 |
1 |
|
|
T1 |
7 |
|
T7 |
34 |
|
T18 |
22 |
two_bytes |
3001 |
1 |
|
|
T1 |
3 |
|
T7 |
45 |
|
T18 |
19 |
one_byte |
2844 |
1 |
|
|
T1 |
1 |
|
T7 |
36 |
|
T18 |
19 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173602 |
1 |
|
|
T1 |
133 |
|
T2 |
1264 |
|
T7 |
1287 |
auto[1] |
3462 |
1 |
|
|
T1 |
2 |
|
T2 |
40 |
|
T7 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177064 |
1 |
|
|
T1 |
135 |
|
T2 |
1304 |
|
T7 |
1307 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177049 |
1 |
|
|
T1 |
135 |
|
T2 |
1304 |
|
T7 |
1307 |
auto[1] |
15 |
1 |
|
|
T178 |
1 |
|
T111 |
1 |
|
T112 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1285 |
1 |
|
|
T2 |
20 |
|
T7 |
5 |
|
T19 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3462 |
1 |
|
|
T1 |
2 |
|
T2 |
40 |
|
T7 |
20 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175419 |
1 |
|
|
T1 |
1071 |
|
T2 |
780 |
|
T7 |
596 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
85867 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
68913 |
1 |
|
|
T1 |
38 |
|
T2 |
767 |
|
T7 |
18 |
seven_bytes |
2995 |
1 |
|
|
T1 |
20 |
|
T7 |
18 |
|
T18 |
5 |
six_bytes |
2996 |
1 |
|
|
T1 |
22 |
|
T7 |
9 |
|
T18 |
6 |
five_bytes |
2970 |
1 |
|
|
T1 |
34 |
|
T7 |
17 |
|
T18 |
9 |
four_bytes |
2903 |
1 |
|
|
T1 |
22 |
|
T7 |
18 |
|
T18 |
7 |
three_bytes |
2957 |
1 |
|
|
T1 |
26 |
|
T7 |
15 |
|
T18 |
9 |
two_bytes |
2850 |
1 |
|
|
T1 |
27 |
|
T7 |
13 |
|
T18 |
9 |
one_byte |
2968 |
1 |
|
|
T1 |
26 |
|
T7 |
9 |
|
T18 |
14 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171939 |
1 |
|
|
T1 |
1059 |
|
T2 |
754 |
|
T7 |
584 |
auto[1] |
3480 |
1 |
|
|
T1 |
12 |
|
T2 |
26 |
|
T7 |
12 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175419 |
1 |
|
|
T1 |
1071 |
|
T2 |
780 |
|
T7 |
596 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175406 |
1 |
|
|
T1 |
1071 |
|
T2 |
780 |
|
T7 |
596 |
auto[1] |
13 |
1 |
|
|
T17 |
1 |
|
T179 |
1 |
|
T112 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1253 |
1 |
|
|
T1 |
1 |
|
T2 |
13 |
|
T7 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3480 |
1 |
|
|
T1 |
12 |
|
T2 |
26 |
|
T7 |
12 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
343832 |
1 |
|
|
T1 |
1621 |
|
T2 |
1027 |
|
T7 |
2201 |
auto[1] |
644 |
1 |
|
|
T8 |
100 |
|
T9 |
98 |
|
T10 |
57 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
173435 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
129700 |
1 |
|
|
T1 |
41 |
|
T2 |
1009 |
|
T7 |
58 |
seven_bytes |
5986 |
1 |
|
|
T1 |
57 |
|
T7 |
48 |
|
T18 |
46 |
six_bytes |
5915 |
1 |
|
|
T1 |
37 |
|
T7 |
59 |
|
T18 |
48 |
five_bytes |
5995 |
1 |
|
|
T1 |
33 |
|
T7 |
50 |
|
T18 |
46 |
four_bytes |
6025 |
1 |
|
|
T1 |
44 |
|
T7 |
64 |
|
T18 |
49 |
three_bytes |
5800 |
1 |
|
|
T1 |
43 |
|
T7 |
61 |
|
T18 |
32 |
two_bytes |
5810 |
1 |
|
|
T1 |
36 |
|
T7 |
55 |
|
T18 |
45 |
one_byte |
5810 |
1 |
|
|
T1 |
49 |
|
T7 |
62 |
|
T18 |
36 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337704 |
1 |
|
|
T1 |
1603 |
|
T2 |
991 |
|
T7 |
2173 |
auto[1] |
6772 |
1 |
|
|
T1 |
18 |
|
T2 |
36 |
|
T7 |
28 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
344476 |
1 |
|
|
T1 |
1621 |
|
T2 |
1027 |
|
T7 |
2201 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
344450 |
1 |
|
|
T1 |
1621 |
|
T2 |
1027 |
|
T7 |
2201 |
auto[1] |
26 |
1 |
|
|
T180 |
3 |
|
T8 |
1 |
|
T181 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2392 |
1 |
|
|
T1 |
2 |
|
T2 |
18 |
|
T7 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6772 |
1 |
|
|
T1 |
18 |
|
T2 |
36 |
|
T7 |
28 |