Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253550276	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

180408819

1

T1

158445

T2

52799

T3

323166

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	224476866	1			T1	206634		T2	69849		T3	432617
values[0x0]	100671931	1			T1	62600		T2	14147		T3	205263
values[0x1]	108810298	1			T1	67039		T2	15322		T3	224610

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197215927	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

236743168

1

T1

200562

T2

64911

T3

442460

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2257148	1			T1	1310		T2	439		T3	3412
valid_sources[0x01]	1297273	1			T1	1428		T2	333		T3	3392
valid_sources[0x02]	2016897	1			T1	1327		T2	368		T3	3418
valid_sources[0x03]	1482856	1			T1	1249		T2	406		T3	3386
valid_sources[0x04]	1309466	1			T1	1428		T2	425		T3	3296
valid_sources[0x05]	1303320	1			T1	1453		T2	419		T3	3359
valid_sources[0x06]	1308230	1			T1	1177		T2	392		T3	3326
valid_sources[0x07]	2145807	1			T1	1149		T2	387		T3	3444
valid_sources[0x08]	2159661	1			T1	1425		T2	383		T3	3314
valid_sources[0x09]	2254444	1			T1	1183		T2	365		T3	3329
valid_sources[0x0a]	1295020	1			T1	1424		T2	433		T3	3439
valid_sources[0x0b]	2328034	1			T1	1280		T2	362		T3	3344
valid_sources[0x0c]	1759437	1			T1	1100		T2	360		T3	3322
valid_sources[0x0d]	2187517	1			T1	1350		T2	361		T3	3364
valid_sources[0x0e]	1657654	1			T1	1350		T2	342		T3	3330
valid_sources[0x0f]	1301824	1			T1	1344		T2	435		T3	3466
valid_sources[0x10]	1304406	1			T1	1324		T2	430		T3	3224
valid_sources[0x11]	1299503	1			T1	1256		T2	351		T3	3444
valid_sources[0x12]	2196726	1			T1	1204		T2	415		T3	3332
valid_sources[0x13]	1305739	1			T1	1278		T2	390		T3	3339
valid_sources[0x14]	1406754	1			T1	1296		T2	398		T3	3192
valid_sources[0x15]	1451778	1			T1	1408		T2	404		T3	3344
valid_sources[0x16]	1301504	1			T1	1223		T2	376		T3	3348
valid_sources[0x17]	1302863	1			T1	1311		T2	365		T3	3367
valid_sources[0x18]	1404475	1			T1	1268		T2	394		T3	3342
valid_sources[0x19]	3227990	1			T1	1293		T2	352		T3	3378
valid_sources[0x1a]	1305131	1			T1	1496		T2	422		T3	3195
valid_sources[0x1b]	1445448	1			T1	1213		T2	447		T3	3299
valid_sources[0x1c]	3304896	1			T1	1442		T2	380		T3	3385
valid_sources[0x1d]	1961929	1			T1	1214		T2	392		T3	3484
valid_sources[0x1e]	1410623	1			T1	1376		T2	363		T3	3415
valid_sources[0x1f]	1302332	1			T1	1292		T2	378		T3	3378
valid_sources[0x20]	1291293	1			T1	1235		T2	364		T3	3354
valid_sources[0x21]	3279713	1			T1	1321		T2	433		T3	3252
valid_sources[0x22]	2179993	1			T1	1319		T2	395		T3	3385
valid_sources[0x23]	1302703	1			T1	1263		T2	395		T3	3317
valid_sources[0x24]	2139761	1			T1	1256		T2	387		T3	3374
valid_sources[0x25]	2206470	1			T1	1296		T2	383		T3	3370
valid_sources[0x26]	2178894	1			T1	1318		T2	426		T3	3378
valid_sources[0x27]	1294677	1			T1	1388		T2	401		T3	3319
valid_sources[0x28]	1301152	1			T1	1444		T2	364		T3	3237
valid_sources[0x29]	1301148	1			T1	1328		T2	346		T3	3379
valid_sources[0x2a]	1302543	1			T1	1267		T2	395		T3	3447
valid_sources[0x2b]	1297718	1			T1	1247		T2	361		T3	3568
valid_sources[0x2c]	1376747	1			T1	1248		T2	372		T3	3380
valid_sources[0x2d]	1303161	1			T1	1352		T2	335		T3	3458
valid_sources[0x2e]	1420051	1			T1	1279		T2	387		T3	3239
valid_sources[0x2f]	2142101	1			T1	1547		T2	406		T3	3357
valid_sources[0x30]	1754932	1			T1	1305		T2	407		T3	3533
valid_sources[0x31]	1301240	1			T1	1313		T2	400		T3	3377
valid_sources[0x32]	1302565	1			T1	1327		T2	365		T3	3324
valid_sources[0x33]	1302549	1			T1	1155		T2	393		T3	3285
valid_sources[0x34]	1299520	1			T1	1103		T2	403		T3	3371
valid_sources[0x35]	1304362	1			T1	1383		T2	364		T3	3351
valid_sources[0x36]	1311997	1			T1	1253		T2	390		T3	3364
valid_sources[0x37]	3687489	1			T1	1424		T2	415		T3	3479
valid_sources[0x38]	1302425	1			T1	1362		T2	385		T3	3503
valid_sources[0x39]	1300012	1			T1	1365		T2	384		T3	3364
valid_sources[0x3a]	1551774	1			T1	1372		T2	476		T3	3437
valid_sources[0x3b]	2164177	1			T1	1386		T2	409		T3	3407
valid_sources[0x3c]	1470231	1			T1	1400		T2	386		T3	3457
valid_sources[0x3d]	2408441	1			T1	1323		T2	371		T3	3232
valid_sources[0x3e]	1401872	1			T1	1412		T2	391		T3	3574
valid_sources[0x3f]	2850208	1			T1	1395		T2	386		T3	3312
valid_sources[0x40]	1300230	1			T1	1204		T2	332		T3	3312
valid_sources[0x41]	1299747	1			T1	1210		T2	412		T3	3407
valid_sources[0x42]	1485130	1			T1	1192		T2	373		T3	3466
valid_sources[0x43]	1297495	1			T1	1339		T2	353		T3	3331
valid_sources[0x44]	1306729	1			T1	1457		T2	417		T3	3409
valid_sources[0x45]	3620928	1			T1	1398		T2	429		T3	3403
valid_sources[0x46]	2181586	1			T1	1128		T2	400		T3	3409
valid_sources[0x47]	1299754	1			T1	1354		T2	390		T3	3413
valid_sources[0x48]	1487770	1			T1	1418		T2	428		T3	3333
valid_sources[0x49]	1301865	1			T1	1225		T2	412		T3	3363
valid_sources[0x4a]	1306189	1			T1	1226		T2	387		T3	3441
valid_sources[0x4b]	1299665	1			T1	1173		T2	366		T3	3388
valid_sources[0x4c]	2210646	1			T1	1276		T2	410		T3	3439
valid_sources[0x4d]	1305588	1			T1	1432		T2	384		T3	3395
valid_sources[0x4e]	2180020	1			T1	1423		T2	371		T3	3416
valid_sources[0x4f]	1299744	1			T1	1320		T2	466		T3	3406
valid_sources[0x50]	1646389	1			T1	1384		T2	424		T3	3303
valid_sources[0x51]	1297925	1			T1	1401		T2	376		T3	3326
valid_sources[0x52]	1459282	1			T1	1465		T2	361		T3	3322
valid_sources[0x53]	1298303	1			T1	1360		T2	384		T3	3306
valid_sources[0x54]	1482121	1			T1	1253		T2	421		T3	3417
valid_sources[0x55]	3260342	1			T1	1318		T2	423		T3	3407
valid_sources[0x56]	1294602	1			T1	1264		T2	407		T3	3320
valid_sources[0x57]	3645578	1			T1	1429		T2	413		T3	3464
valid_sources[0x58]	1351009	1			T1	1246		T2	351		T3	3435
valid_sources[0x59]	1302020	1			T1	1411		T2	377		T3	3482
valid_sources[0x5a]	1306770	1			T1	1340		T2	391		T3	3313
valid_sources[0x5b]	2238686	1			T1	1280		T2	431		T3	3454
valid_sources[0x5c]	3661755	1			T1	1383		T2	363		T3	3387
valid_sources[0x5d]	3283598	1			T1	1230		T2	417		T3	3311
valid_sources[0x5e]	1301353	1			T1	1284		T2	321		T3	3369
valid_sources[0x5f]	1307091	1			T1	1288		T2	377		T3	3375
valid_sources[0x60]	1304216	1			T1	1414		T2	379		T3	3286
valid_sources[0x61]	1511093	1			T1	1343		T2	375		T3	3474
valid_sources[0x62]	1304406	1			T1	1399		T2	401		T3	3382
valid_sources[0x63]	1301154	1			T1	1212		T2	380		T3	3394
valid_sources[0x64]	1324002	1			T1	1171		T2	415		T3	3396
valid_sources[0x65]	1820615	1			T1	1303		T2	410		T3	3320
valid_sources[0x66]	1296900	1			T1	1303		T2	390		T3	3260
valid_sources[0x67]	1377843	1			T1	1174		T2	343		T3	3263
valid_sources[0x68]	1302148	1			T1	1339		T2	364		T3	3323
valid_sources[0x69]	1762569	1			T1	1356		T2	416		T3	3329
valid_sources[0x6a]	1431376	1			T1	1342		T2	377		T3	3465
valid_sources[0x6b]	1322048	1			T1	1321		T2	355		T3	3353
valid_sources[0x6c]	1502212	1			T1	1274		T2	345		T3	3344
valid_sources[0x6d]	1294864	1			T1	1399		T2	396		T3	3487
valid_sources[0x6e]	1316345	1			T1	1389		T2	368		T3	3388
valid_sources[0x6f]	1303321	1			T1	1176		T2	366		T3	3530
valid_sources[0x70]	1300865	1			T1	1251		T2	337		T3	3436
valid_sources[0x71]	1301159	1			T1	1299		T2	364		T3	3313
valid_sources[0x72]	1541517	1			T1	1495		T2	365		T3	3308
valid_sources[0x73]	2251059	1			T1	1203		T2	387		T3	3319
valid_sources[0x74]	2228203	1			T1	1110		T2	384		T3	3331
valid_sources[0x75]	1304020	1			T1	1221		T2	403		T3	3353
valid_sources[0x76]	2134662	1			T1	1410		T2	397		T3	3289
valid_sources[0x77]	1297895	1			T1	1297		T2	399		T3	3453
valid_sources[0x78]	1777780	1			T1	1357		T2	332		T3	3462
valid_sources[0x79]	1301397	1			T1	1276		T2	387		T3	3222
valid_sources[0x7a]	1300405	1			T1	1218		T2	393		T3	3288
valid_sources[0x7b]	1445220	1			T1	1228		T2	365		T3	3430
valid_sources[0x7c]	1299143	1			T1	1426		T2	401		T3	3430
valid_sources[0x7d]	1536696	1			T1	1195		T2	411		T3	3323
valid_sources[0x7e]	1358168	1			T1	1128		T2	395		T3	3351
valid_sources[0x7f]	1302248	1			T1	1456		T2	369		T3	3280
valid_sources[0x80]	2271217	1			T1	1369		T2	388		T3	3336

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70193987

1

T1

87437

T2

36219

T3

112719

values[0x0]

all_enables

biggest_size

59269964

1

T1

38098

T2

8804

T3

114120

values[0x1]

all_enables

biggest_size

50944868

1

T1

32910

T2

7776

T3

96327