Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254304506

1

T1

177828

T2

46519

T3

539324

full_word

180456179

1

T1

158445

T2

52799

T3

323166

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	434760345	1			T1	336273		T2	99318		T3	862490
auto[TlIntgErrCmd]	108	1			T130	3		T131	6		T132	10
auto[TlIntgErrData]	116	1			T130	5		T131	8		T132	4
auto[TlIntgErrBoth]	116	1			T130	12		T131	6		T132	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

224624013

1

T1

206634

T2

69849

T3

432617

auto[1]

210136672

1

T1

129639

T2

29469

T3

429873

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154418055	1			T1	119197		T2	33630		T3	319898
auto[TlIntgErrNone]	partial	auto[1]	99886144	1			T1	58631		T2	12889		T3	219426
auto[TlIntgErrNone]	full_word	auto[0]	70205821	1			T1	87437		T2	36219		T3	112719
auto[TlIntgErrNone]	full_word	auto[1]	110250325	1			T1	71008		T2	16580		T3	210447
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T131	1		T132	4		T183	4
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T130	2		T131	5		T132	5
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T130	1		T184	1		T187	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T132	1		T184	1		T188	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T130	3		T131	3		T132	3
auto[TlIntgErrData]	partial	auto[1]	56	1			T130	1		T131	4		T183	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T132	1		T187	1		T189	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T130	1		T131	1		T185	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T130	4		T131	5		T132	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T130	6		T131	1		T132	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T184	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T130	2		T187	1		T190	1