Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	175444	0	0
entropy_period_rd_A	2147483647	1911	0	0
intr_enable_rd_A	2147483647	2579	0	0
prefix_0_rd_A	2147483647	1824	0	0
prefix_10_rd_A	2147483647	1683	0	0
prefix_1_rd_A	2147483647	1786	0	0
prefix_2_rd_A	2147483647	1578	0	0
prefix_3_rd_A	2147483647	1803	0	0
prefix_4_rd_A	2147483647	1879	0	0
prefix_5_rd_A	2147483647	1790	0	0
prefix_6_rd_A	2147483647	1803	0	0
prefix_7_rd_A	2147483647	1813	0	0
prefix_8_rd_A	2147483647	1645	0	0
prefix_9_rd_A	2147483647	1738	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	175444	0	0
T23	188648	0	0	0
T52	165107	23697	0	0
T53	0	73620	0	0
T54	0	19177	0	0
T77	0	55816	0	0
T79	864959	0	0	0
T115	628386	0	0	0
T130	0	4	0	0
T137	0	168	0	0
T138	0	5	0	0
T139	0	9	0	0
T140	0	4	0	0
T141	0	7	0	0
T142	9543	0	0	0
T143	329785	0	0	0
T144	649368	0	0	0
T145	226362	0	0	0
T146	183723	0	0	0
T147	11048	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1911	0	0
T72	473089	0	0	0
T77	636334	243	0	0
T95	0	19	0	0
T103	0	4	0	0
T106	0	77	0	0
T138	0	6	0	0
T141	0	17	0	0
T156	0	60	0	0
T157	0	8	0	0
T158	0	9	0	0
T159	0	200	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2579	0	0
T72	473089	0	0	0
T77	636334	164	0	0
T94	0	1	0	0
T95	0	26	0	0
T103	0	5	0	0
T135	0	11	0	0
T138	0	13	0	0
T141	0	16	0	0
T156	0	30	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0
T168	0	15	0	0
T169	0	3	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1824	0	0
T72	473089	0	0	0
T77	636334	152	0	0
T94	0	5	0	0
T95	0	19	0	0
T103	0	8	0	0
T105	0	13	0	0
T138	0	13	0	0
T141	0	15	0	0
T156	0	73	0	0
T157	0	4	0	0
T158	0	2	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1683	0	0
T72	473089	0	0	0
T77	636334	167	0	0
T94	0	5	0	0
T95	0	21	0	0
T103	0	10	0	0
T105	0	2	0	0
T138	0	7	0	0
T141	0	17	0	0
T156	0	49	0	0
T157	0	4	0	0
T158	0	9	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1786	0	0
T72	473089	0	0	0
T77	636334	174	0	0
T94	0	3	0	0
T95	0	20	0	0
T103	0	5	0	0
T105	0	1	0	0
T138	0	2	0	0
T141	0	17	0	0
T156	0	33	0	0
T157	0	1	0	0
T158	0	3	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1578	0	0
T72	473089	0	0	0
T77	636334	114	0	0
T94	0	1	0	0
T95	0	16	0	0
T103	0	8	0	0
T106	0	48	0	0
T138	0	14	0	0
T141	0	14	0	0
T156	0	30	0	0
T157	0	3	0	0
T158	0	2	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1803	0	0
T72	473089	0	0	0
T77	636334	211	0	0
T94	0	12	0	0
T95	0	19	0	0
T103	0	6	0	0
T105	0	7	0	0
T106	0	63	0	0
T141	0	21	0	0
T156	0	21	0	0
T157	0	1	0	0
T158	0	3	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1879	0	0
T72	473089	0	0	0
T77	636334	155	0	0
T94	0	2	0	0
T95	0	18	0	0
T103	0	10	0	0
T105	0	9	0	0
T138	0	10	0	0
T141	0	17	0	0
T156	0	100	0	0
T157	0	2	0	0
T158	0	6	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1790	0	0
T72	473089	0	0	0
T77	636334	133	0	0
T94	0	1	0	0
T95	0	28	0	0
T103	0	5	0	0
T105	0	2	0	0
T106	0	57	0	0
T138	0	25	0	0
T141	0	6	0	0
T156	0	84	0	0
T159	0	260	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1803	0	0
T72	473089	0	0	0
T77	636334	177	0	0
T94	0	6	0	0
T95	0	17	0	0
T103	0	4	0	0
T106	0	52	0	0
T138	0	14	0	0
T141	0	16	0	0
T156	0	39	0	0
T157	0	5	0	0
T159	0	208	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1813	0	0
T72	473089	0	0	0
T77	636334	156	0	0
T95	0	25	0	0
T103	0	9	0	0
T105	0	5	0	0
T106	0	62	0	0
T138	0	13	0	0
T141	0	6	0	0
T156	0	21	0	0
T157	0	5	0	0
T158	0	1	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1645	0	0
T72	473089	0	0	0
T77	636334	141	0	0
T94	0	2	0	0
T95	0	15	0	0
T103	0	2	0	0
T105	0	2	0	0
T106	0	53	0	0
T138	0	10	0	0
T141	0	16	0	0
T156	0	37	0	0
T157	0	2	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1738	0	0
T72	473089	0	0	0
T77	636334	199	0	0
T94	0	3	0	0
T95	0	8	0	0
T103	0	12	0	0
T105	0	8	0	0
T138	0	10	0	0
T141	0	6	0	0
T156	0	36	0	0
T157	0	1	0	0
T158	0	6	0	0
T160	482735	0	0	0
T161	1292	0	0	0
T162	133367	0	0	0
T163	18533	0	0	0
T164	196510	0	0	0
T165	105674	0	0	0
T166	25220	0	0	0
T167	492092	0	0	0