Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	258633497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

185010654

1

T1

324487

T2

3941

T3

177381

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	229920206	1			T1	408649		T2	4585		T3	227403
values[0x0]	102818658	1			T1	197055		T2	1206		T3	107307
values[0x1]	110905287	1			T1	208844		T2	1383		T3	115825

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201095987	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

242548164

1

T1

428851

T2

4675

T3

237060

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1306559	1			T1	3140		T2	1		T3	1722
valid_sources[0x01]	1956312	1			T1	3195		T2	1		T3	1772
valid_sources[0x02]	1310909	1			T1	3233		T2	1		T3	1753
valid_sources[0x03]	1320600	1			T1	3240		T2	3		T3	1740
valid_sources[0x04]	1304159	1			T1	3181		T3	1723		T36	1279
valid_sources[0x05]	3666271	1			T1	3241		T2	3		T3	1833
valid_sources[0x06]	1310275	1			T1	3210		T2	1		T3	1678
valid_sources[0x07]	1302020	1			T1	3102		T2	3		T3	1853
valid_sources[0x08]	1309582	1			T1	3159		T2	2		T3	1815
valid_sources[0x09]	1303050	1			T1	3126		T2	4		T3	1694
valid_sources[0x0a]	1310256	1			T1	3218		T2	1		T3	1767
valid_sources[0x0b]	1391820	1			T1	3286		T2	5		T3	1728
valid_sources[0x0c]	1300831	1			T1	3231		T2	4		T3	1754
valid_sources[0x0d]	1306185	1			T1	3289		T2	3		T3	1774
valid_sources[0x0e]	1310877	1			T1	3216		T2	3		T3	1836
valid_sources[0x0f]	1302006	1			T1	3148		T2	2		T3	1712
valid_sources[0x10]	1304858	1			T1	3174		T2	1		T3	1751
valid_sources[0x11]	1853350	1			T1	3142		T2	3		T3	1738
valid_sources[0x12]	2160692	1			T1	3204		T2	4		T3	1740
valid_sources[0x13]	1308708	1			T1	3284		T2	2		T3	1757
valid_sources[0x14]	2603265	1			T1	3273		T2	1		T3	1775
valid_sources[0x15]	1304754	1			T1	3192		T2	3		T3	1766
valid_sources[0x16]	1951871	1			T1	3092		T2	2		T3	1749
valid_sources[0x17]	1384009	1			T1	3068		T2	3		T3	1810
valid_sources[0x18]	1302035	1			T1	3127		T2	2		T3	1764
valid_sources[0x19]	1337806	1			T1	3109		T2	2		T3	1753
valid_sources[0x1a]	1316142	1			T1	3243		T3	1818		T36	1278
valid_sources[0x1b]	1462094	1			T1	3325		T2	3		T3	1762
valid_sources[0x1c]	1310443	1			T1	3167		T2	2		T3	1765
valid_sources[0x1d]	6859662	1			T1	3146		T2	3		T3	1884
valid_sources[0x1e]	1695094	1			T1	3200		T2	2		T3	1764
valid_sources[0x1f]	1305773	1			T1	3128		T2	4		T3	1866
valid_sources[0x20]	1324845	1			T1	3102		T3	1725		T36	1327
valid_sources[0x21]	2198368	1			T1	3154		T2	1		T3	1714
valid_sources[0x22]	3334173	1			T1	3169		T3	1740		T36	1378
valid_sources[0x23]	1300873	1			T1	3233		T2	2		T3	1684
valid_sources[0x24]	1974469	1			T1	3174		T2	1		T3	1732
valid_sources[0x25]	1309077	1			T1	3138		T2	2		T3	1766
valid_sources[0x26]	1359616	1			T1	3215		T2	3		T3	1790
valid_sources[0x27]	1300107	1			T1	3149		T2	2		T3	1788
valid_sources[0x28]	1460199	1			T1	3167		T2	1		T3	1788
valid_sources[0x29]	1461960	1			T1	3206		T2	1		T3	1820
valid_sources[0x2a]	1437215	1			T1	3129		T2	2		T3	1780
valid_sources[0x2b]	1772550	1			T1	3259		T2	2		T3	1803
valid_sources[0x2c]	1310803	1			T1	3260		T2	3		T3	1750
valid_sources[0x2d]	2295565	1			T1	3344		T2	2		T3	1773
valid_sources[0x2e]	1396980	1			T1	3135		T2	2		T3	1785
valid_sources[0x2f]	1507125	1			T1	3229		T2	3		T3	1743
valid_sources[0x30]	2139401	1			T1	3120		T2	2		T3	1798
valid_sources[0x31]	1964902	1			T1	3117		T2	2		T3	1736
valid_sources[0x32]	1314190	1			T1	3120		T2	1		T3	1709
valid_sources[0x33]	1328640	1			T1	3092		T2	3		T3	1724
valid_sources[0x34]	1313735	1			T1	3167		T2	2		T3	1772
valid_sources[0x35]	2121970	1			T1	3251		T2	1		T3	1783
valid_sources[0x36]	1300094	1			T1	3149		T2	5		T3	1790
valid_sources[0x37]	1767381	1			T1	3173		T2	4		T3	1782
valid_sources[0x38]	1430979	1			T1	3178		T3	1745		T36	1242
valid_sources[0x39]	1309417	1			T1	3125		T2	1		T3	1704
valid_sources[0x3a]	1311979	1			T1	3206		T2	5		T3	1658
valid_sources[0x3b]	1321089	1			T1	3191		T2	4		T3	1761
valid_sources[0x3c]	1302598	1			T1	3231		T2	5		T3	1798
valid_sources[0x3d]	1305423	1			T1	3214		T2	2		T3	1775
valid_sources[0x3e]	3281763	1			T1	3178		T2	3		T3	1817
valid_sources[0x3f]	1302734	1			T1	3218		T2	2		T3	1761
valid_sources[0x40]	2189291	1			T1	3252		T2	4		T3	1772
valid_sources[0x41]	1307486	1			T1	3186		T2	3		T3	1716
valid_sources[0x42]	1419522	1			T1	3188		T2	4		T3	1708
valid_sources[0x43]	1304131	1			T1	3138		T2	4		T3	1756
valid_sources[0x44]	1458226	1			T1	3192		T3	1795		T36	1314
valid_sources[0x45]	1307316	1			T1	3221		T2	2		T3	1680
valid_sources[0x46]	1343388	1			T1	3184		T3	1750		T36	1207
valid_sources[0x47]	3619210	1			T1	3174		T2	2		T3	1705
valid_sources[0x48]	1311782	1			T1	3234		T2	3		T3	1679
valid_sources[0x49]	1331844	1			T1	3132		T2	5		T3	1716
valid_sources[0x4a]	1319368	1			T1	3205		T2	2		T3	1758
valid_sources[0x4b]	1309226	1			T1	3182		T3	1732		T36	1211
valid_sources[0x4c]	2213972	1			T1	3127		T2	3		T3	1729
valid_sources[0x4d]	1304020	1			T1	3161		T2	1		T3	1736
valid_sources[0x4e]	1300547	1			T1	3195		T2	1		T3	1814
valid_sources[0x4f]	1305493	1			T1	3108		T2	3		T3	1841
valid_sources[0x50]	1311595	1			T1	3155		T2	2		T3	1768
valid_sources[0x51]	1300063	1			T1	3113		T3	1760		T36	1272
valid_sources[0x52]	1298235	1			T1	3211		T2	3		T3	1781
valid_sources[0x53]	3638840	1			T1	3141		T2	2		T3	1777
valid_sources[0x54]	1305383	1			T1	3332		T2	2		T3	1731
valid_sources[0x55]	1311805	1			T1	3256		T2	3		T3	1743
valid_sources[0x56]	1313640	1			T1	3242		T2	3		T3	1682
valid_sources[0x57]	1444167	1			T1	3300		T2	1		T3	1656
valid_sources[0x58]	1306166	1			T1	3253		T3	1729		T36	1291
valid_sources[0x59]	1308262	1			T1	3161		T2	1		T3	1789
valid_sources[0x5a]	3786063	1			T1	3183		T2	3		T3	1709
valid_sources[0x5b]	1299214	1			T1	3159		T2	2		T3	1759
valid_sources[0x5c]	1304021	1			T1	3126		T2	1		T3	1688
valid_sources[0x5d]	2211603	1			T1	3172		T3	1754		T36	1331
valid_sources[0x5e]	1331147	1			T1	3131		T2	2		T3	1768
valid_sources[0x5f]	1308281	1			T1	3147		T2	1		T3	1748
valid_sources[0x60]	1899170	1			T1	3212		T2	6594		T3	1650
valid_sources[0x61]	1310930	1			T1	3400		T2	2		T3	1711
valid_sources[0x62]	1937460	1			T1	3152		T2	3		T3	1700
valid_sources[0x63]	1334277	1			T1	3237		T2	2		T3	1754
valid_sources[0x64]	1303247	1			T1	3185		T2	1		T3	1784
valid_sources[0x65]	1308728	1			T1	3165		T2	6		T3	1762
valid_sources[0x66]	1314661	1			T1	3158		T2	1		T3	1797
valid_sources[0x67]	1365129	1			T1	3206		T2	3		T3	1761
valid_sources[0x68]	3300146	1			T1	3275		T2	4		T3	1764
valid_sources[0x69]	1306370	1			T1	3222		T2	1		T3	1739
valid_sources[0x6a]	2222336	1			T1	3199		T2	5		T3	1818
valid_sources[0x6b]	1991673	1			T1	3198		T2	3		T3	1795
valid_sources[0x6c]	1307828	1			T1	3172		T2	1		T3	1820
valid_sources[0x6d]	1307870	1			T1	3230		T2	3		T3	1707
valid_sources[0x6e]	1364275	1			T1	3266		T2	4		T3	1798
valid_sources[0x6f]	1807852	1			T1	3147		T2	4		T3	1718
valid_sources[0x70]	2209501	1			T1	3192		T3	1771		T36	1347
valid_sources[0x71]	1312470	1			T1	3175		T2	6		T3	1772
valid_sources[0x72]	2603176	1			T1	3177		T3	1702		T36	1230
valid_sources[0x73]	1299569	1			T1	3123		T3	1666		T36	1280
valid_sources[0x74]	3846250	1			T1	3244		T2	3		T3	1752
valid_sources[0x75]	1316146	1			T1	3145		T2	1		T3	1772
valid_sources[0x76]	1304532	1			T1	3203		T2	3		T3	1762
valid_sources[0x77]	3649311	1			T1	3193		T2	5		T3	1821
valid_sources[0x78]	1303938	1			T1	3168		T2	2		T3	1753
valid_sources[0x79]	1308668	1			T1	3144		T2	1		T3	1756
valid_sources[0x7a]	1302110	1			T1	3050		T2	3		T3	1707
valid_sources[0x7b]	1299779	1			T1	3245		T2	2		T3	1778
valid_sources[0x7c]	1305286	1			T1	3126		T2	2		T3	1740
valid_sources[0x7d]	1313995	1			T1	3134		T2	3		T3	1775
valid_sources[0x7e]	1333609	1			T1	3279		T2	1		T3	1795
valid_sources[0x7f]	1304043	1			T1	3190		T2	5		T3	1736
valid_sources[0x80]	2823120	1			T1	3132		T2	4		T3	1771

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71165767

1

T1

106737

T2

2623

T3

63098

values[0x0]

all_enables

biggest_size

61123114

1

T1

117418

T2

683

T3

61888

values[0x1]

all_enables

biggest_size

52721773

1

T1

100332

T2

635

T3

52395