Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259011846

1

T1

490061

T2

3233

T3

273154

full_word

185034345

1

T1

324487

T2

3941

T3

177381

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	444045921	1			T1	814548		T2	7174		T3	450535
auto[TlIntgErrCmd]	81	1			T132	2		T133	5		T134	6
auto[TlIntgErrData]	92	1			T132	3		T133	7		T134	10
auto[TlIntgErrBoth]	97	1			T132	5		T133	8		T134	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229992980

1

T1

408649

T2

4585

T3

227403

auto[1]

214053211

1

T1

405899

T2

2589

T3

223132

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158821136	1			T1	301912		T2	1962		T3	164305
auto[TlIntgErrNone]	partial	auto[1]	100190465	1			T1	188149		T2	1271		T3	108849
auto[TlIntgErrNone]	full_word	auto[0]	71171716	1			T1	106737		T2	2623		T3	63098
auto[TlIntgErrNone]	full_word	auto[1]	113862604	1			T1	217750		T2	1318		T3	114283
auto[TlIntgErrCmd]	partial	auto[0]	28	1			T132	1		T133	2		T134	4
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T132	1		T133	1		T134	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T133	1		T194	1		T191	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T133	1		T190	2		-	-
auto[TlIntgErrData]	partial	auto[0]	46	1			T132	1		T133	3		T134	6
auto[TlIntgErrData]	partial	auto[1]	37	1			T132	2		T133	3		T134	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T133	1		T134	2		T190	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T193	1		T195	1		T196	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T132	1		T133	5		T134	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T132	4		T133	3		T134	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T194	1		T196	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T170	1		T188	1		T195	1