Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	88966	0	0
entropy_period_rd_A	2147483647	1443	0	0
intr_enable_rd_A	2147483647	2058	0	0
prefix_0_rd_A	2147483647	1261	0	0
prefix_10_rd_A	2147483647	1421	0	0
prefix_1_rd_A	2147483647	1398	0	0
prefix_2_rd_A	2147483647	1440	0	0
prefix_3_rd_A	2147483647	1363	0	0
prefix_4_rd_A	2147483647	1319	0	0
prefix_5_rd_A	2147483647	1305	0	0
prefix_6_rd_A	2147483647	1333	0	0
prefix_7_rd_A	2147483647	1285	0	0
prefix_8_rd_A	2147483647	1447	0	0
prefix_9_rd_A	2147483647	1375	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	88966	0	0
T25	111714	0	0	0
T72	1135	0	0	0
T75	401409	61199	0	0
T76	0	24348	0	0
T97	0	2	0	0
T117	4028	0	0	0
T129	0	138	0	0
T135	0	112	0	0
T139	0	304	0	0
T140	0	123	0	0
T142	0	235	0	0
T144	0	2	0	0
T145	0	1	0	0
T147	119203	0	0	0
T148	884609	0	0	0
T149	10279	0	0	0
T150	703650	0	0	0
T151	43684	0	0	0
T152	245588	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1443	0	0
T96	2654	14	0	0
T97	4656	2	0	0
T103	2749	8	0	0
T134	23819	115	0	0
T165	1785	8	0	0
T166	11703	33	0	0
T167	1905	9	0	0
T168	2364	6	0	0
T169	1504	4	0	0
T170	11036	29	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2058	0	0
T96	2654	8	0	0
T97	4656	7	0	0
T103	2749	3	0	0
T134	23819	136	0	0
T165	1785	15	0	0
T166	11703	80	0	0
T167	1905	2	0	0
T171	1072	16	0	0
T172	1642	24	0	0
T173	1043	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1261	0	0
T96	2654	9	0	0
T97	4656	8	0	0
T103	2749	6	0	0
T134	23819	84	0	0
T165	1785	2	0	0
T166	11703	32	0	0
T167	1905	8	0	0
T168	2364	3	0	0
T170	11036	22	0	0
T174	2907	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1421	0	0
T96	2654	5	0	0
T97	4656	6	0	0
T103	2749	7	0	0
T134	23819	82	0	0
T165	1785	2	0	0
T166	11703	44	0	0
T167	1905	3	0	0
T168	2364	2	0	0
T169	1504	4	0	0
T170	11036	42	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1398	0	0
T96	2654	11	0	0
T97	4656	8	0	0
T103	2749	10	0	0
T134	23819	80	0	0
T165	1785	6	0	0
T166	11703	102	0	0
T167	1905	5	0	0
T168	2364	4	0	0
T170	11036	53	0	0
T174	2907	7	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1440	0	0
T96	2654	5	0	0
T97	4656	12	0	0
T103	2749	13	0	0
T134	23819	93	0	0
T166	11703	27	0	0
T167	1905	5	0	0
T168	2364	7	0	0
T169	1504	3	0	0
T170	11036	28	0	0
T174	2907	12	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1363	0	0
T96	2654	14	0	0
T97	4656	7	0	0
T103	2749	8	0	0
T134	23819	59	0	0
T165	1785	9	0	0
T166	11703	72	0	0
T167	1905	9	0	0
T168	2364	9	0	0
T170	11036	30	0	0
T174	2907	7	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1319	0	0
T96	2654	3	0	0
T97	4656	4	0	0
T103	2749	4	0	0
T134	23819	74	0	0
T165	1785	4	0	0
T166	11703	51	0	0
T167	1905	1	0	0
T168	2364	8	0	0
T169	1504	7	0	0
T170	11036	21	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1305	0	0
T96	2654	13	0	0
T97	4656	10	0	0
T103	2749	16	0	0
T129	8221	5	0	0
T134	23819	81	0	0
T165	1785	1	0	0
T166	11703	20	0	0
T167	1905	3	0	0
T169	1504	3	0	0
T170	11036	22	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1333	0	0
T96	2654	1	0	0
T97	4656	8	0	0
T103	2749	11	0	0
T134	23819	80	0	0
T165	1785	6	0	0
T166	11703	35	0	0
T167	1905	6	0	0
T168	2364	1	0	0
T170	11036	9	0	0
T174	2907	8	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1285	0	0
T96	2654	2	0	0
T97	4656	9	0	0
T103	2749	10	0	0
T134	23819	85	0	0
T165	1785	1	0	0
T166	11703	63	0	0
T167	1905	5	0	0
T168	2364	5	0	0
T169	1504	10	0	0
T170	11036	18	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1447	0	0
T96	2654	8	0	0
T103	2749	13	0	0
T134	23819	86	0	0
T166	11703	77	0	0
T167	1905	3	0	0
T168	2364	4	0	0
T169	1504	4	0	0
T170	11036	19	0	0
T174	2907	8	0	0
T175	2836	16	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1375	0	0
T96	2654	9	0	0
T97	4656	13	0	0
T103	2749	11	0	0
T134	23819	71	0	0
T165	1785	1	0	0
T166	11703	36	0	0
T167	1905	1	0	0
T168	2364	6	0	0
T169	1504	6	0	0
T170	11036	31	0	0