Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259244148

1

T1

1199

T2

552473

T3

44385

full_word

184986684

1

T1

1028

T2

343058

T3

43493

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	444230512	1			T1	2227		T2	895531		T3	87878
auto[TlIntgErrCmd]	107	1			T129	8		T142	2		T143	5
auto[TlIntgErrData]	111	1			T129	2		T142	4		T143	11
auto[TlIntgErrBoth]	102	1			T129	10		T142	4		T143	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229930298

1

T1

1171

T2

448809

T3

53621

auto[1]

214300534

1

T1

1056

T2

446722

T3

34257

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158623539	1			T1	1142		T2	331963		T3	43894
auto[TlIntgErrNone]	partial	auto[1]	100620318	1			T1	57		T2	220510		T3	491
auto[TlIntgErrNone]	full_word	auto[0]	71306630	1			T1	29		T2	116846		T3	9727
auto[TlIntgErrNone]	full_word	auto[1]	113680025	1			T1	999		T2	226212		T3	33766
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T129	4		T143	2		T193	1
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T129	4		T142	2		T143	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T189	1		T192	1		T194	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T189	1		T195	1		T191	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T142	1		T143	9		T193	4
auto[TlIntgErrData]	partial	auto[1]	53	1			T129	2		T142	2		T143	2
auto[TlIntgErrData]	full_word	auto[0]	9	1			T196	2		T191	1		T197	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T142	1		T193	1		T192	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T129	5		T142	2		T143	1
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T129	4		T142	2		T143	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T129	1		T193	1		T189	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T198	1		T191	1		T199	1